1 /** 2 * @file ctb_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the CTB Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup ctb_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_CTB_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_CTB_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup ctb 67 * @defgroup ctb_registers CTB_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the CTB Peripheral Module. 69 * @details The Cryptographic Toolbox is a combination of cryptographic engines and a secure cryptographic accelerator (SCA) used to provide advanced cryptographic security. 70 */ 71 72 /** 73 * @ingroup ctb_registers 74 * Structure type to access the CTB Registers. 75 */ 76 typedef struct { 77 __IO uint32_t ctrl; /**< <tt>\b 0x00:</tt> CTB CTRL Register */ 78 __IO uint32_t cipher_ctrl; /**< <tt>\b 0x04:</tt> CTB CIPHER_CTRL Register */ 79 __IO uint32_t hash_ctrl; /**< <tt>\b 0x08:</tt> CTB HASH_CTRL Register */ 80 __IO uint32_t crc_ctrl; /**< <tt>\b 0x0C:</tt> CTB CRC_CTRL Register */ 81 __IO uint32_t dma_src; /**< <tt>\b 0x10:</tt> CTB DMA_SRC Register */ 82 __IO uint32_t dma_dest; /**< <tt>\b 0x14:</tt> CTB DMA_DEST Register */ 83 __IO uint32_t dma_cnt; /**< <tt>\b 0x18:</tt> CTB DMA_CNT Register */ 84 __IO uint32_t maa_ctrl; /**< <tt>\b 0x1C:</tt> CTB MAA_CTRL Register */ 85 __O uint32_t din[4]; /**< <tt>\b 0x20:</tt> CTB DIN Register */ 86 __I uint32_t dout[4]; /**< <tt>\b 0x30:</tt> CTB DOUT Register */ 87 __IO uint32_t crc_poly; /**< <tt>\b 0x40:</tt> CTB CRC_POLY Register */ 88 __IO uint32_t crc_val; /**< <tt>\b 0x44:</tt> CTB CRC_VAL Register */ 89 __IO uint32_t crc_prng; /**< <tt>\b 0x48:</tt> CTB CRC_PRNG Register */ 90 __IO uint32_t ham_ecc; /**< <tt>\b 0x4C:</tt> CTB HAM_ECC Register */ 91 __IO uint32_t cipher_init[4]; /**< <tt>\b 0x50:</tt> CTB CIPHER_INIT Register */ 92 __O uint32_t cipher_key[8]; /**< <tt>\b 0x60:</tt> CTB CIPHER_KEY Register */ 93 __IO uint32_t hash_digest[16]; /**< <tt>\b 0x80:</tt> CTB HASH_DIGEST Register */ 94 __IO uint32_t hash_msg_sz[4]; /**< <tt>\b 0xC0:</tt> CTB HASH_MSG_SZ Register */ 95 __IO uint32_t aad_length[2]; /**< <tt>\b 0xD0:</tt> CTB AAD_LENGTH Register */ 96 __IO uint32_t pld_length[2]; /**< <tt>\b 0xD8:</tt> CTB PLD_LENGTH Register */ 97 __IO uint32_t tagmic[4]; /**< <tt>\b 0xE0:</tt> CTB TAGMIC Register */ 98 __IO uint32_t maa_maws; /**< <tt>\b 0xF0:</tt> CTB MAA_MAWS Register */ 99 __R uint32_t rsv_0xf4_0x6ff[387]; 100 __IO uint32_t sca_ctrl0; /**< <tt>\b 0x700:</tt> CTB SCA_CTRL0 Register */ 101 __IO uint32_t sca_ctrl1; /**< <tt>\b 0x704:</tt> CTB SCA_CTRL1 Register */ 102 __IO uint32_t sca_stat; /**< <tt>\b 0x708:</tt> CTB SCA_STAT Register */ 103 __IO uint32_t sca_ppx_addr; /**< <tt>\b 0x70C:</tt> CTB SCA_PPX_ADDR Register */ 104 __IO uint32_t sca_ppy_addr; /**< <tt>\b 0x710:</tt> CTB SCA_PPY_ADDR Register */ 105 __IO uint32_t sca_ppz_addr; /**< <tt>\b 0x714:</tt> CTB SCA_PPZ_ADDR Register */ 106 __IO uint32_t sca_pqx_addr; /**< <tt>\b 0x718:</tt> CTB SCA_PQX_ADDR Register */ 107 __IO uint32_t sca_pqy_addr; /**< <tt>\b 0x71C:</tt> CTB SCA_PQY_ADDR Register */ 108 __IO uint32_t sca_pqz_addr; /**< <tt>\b 0x720:</tt> CTB SCA_PQZ_ADDR Register */ 109 __IO uint32_t sca_rdsa_addr; /**< <tt>\b 0x724:</tt> CTB SCA_RDSA_ADDR Register */ 110 __IO uint32_t sca_res_addr; /**< <tt>\b 0x728:</tt> CTB SCA_RES_ADDR Register */ 111 __IO uint32_t sca_op_buff_addr; /**< <tt>\b 0x72C:</tt> CTB SCA_OP_BUFF_ADDR Register */ 112 __IO uint32_t sca_moddata; /**< <tt>\b 0x730:</tt> CTB SCA_MODDATA Register */ 113 __IO uint32_t sca_nrng; /**< <tt>\b 0x734:</tt> CTB SCA_NRNG Register */ 114 __IO uint32_t sca_wash; /**< <tt>\b 0x738:</tt> CTB SCA_WASH Register */ 115 } mxc_ctb_regs_t; 116 117 /* Register offsets for module CTB */ 118 /** 119 * @ingroup ctb_registers 120 * @defgroup CTB_Register_Offsets Register Offsets 121 * @brief CTB Peripheral Register Offsets from the CTB Base Peripheral Address. 122 * @{ 123 */ 124 #define MXC_R_CTB_CTRL ((uint32_t)0x00000000UL) /**< Offset from CTB Base Address: <tt> 0x0000</tt> */ 125 #define MXC_R_CTB_CIPHER_CTRL ((uint32_t)0x00000004UL) /**< Offset from CTB Base Address: <tt> 0x0004</tt> */ 126 #define MXC_R_CTB_HASH_CTRL ((uint32_t)0x00000008UL) /**< Offset from CTB Base Address: <tt> 0x0008</tt> */ 127 #define MXC_R_CTB_CRC_CTRL ((uint32_t)0x0000000CUL) /**< Offset from CTB Base Address: <tt> 0x000C</tt> */ 128 #define MXC_R_CTB_DMA_SRC ((uint32_t)0x00000010UL) /**< Offset from CTB Base Address: <tt> 0x0010</tt> */ 129 #define MXC_R_CTB_DMA_DEST ((uint32_t)0x00000014UL) /**< Offset from CTB Base Address: <tt> 0x0014</tt> */ 130 #define MXC_R_CTB_DMA_CNT ((uint32_t)0x00000018UL) /**< Offset from CTB Base Address: <tt> 0x0018</tt> */ 131 #define MXC_R_CTB_MAA_CTRL ((uint32_t)0x0000001CUL) /**< Offset from CTB Base Address: <tt> 0x001C</tt> */ 132 #define MXC_R_CTB_DIN ((uint32_t)0x00000020UL) /**< Offset from CTB Base Address: <tt> 0x0020</tt> */ 133 #define MXC_R_CTB_DOUT ((uint32_t)0x00000030UL) /**< Offset from CTB Base Address: <tt> 0x0030</tt> */ 134 #define MXC_R_CTB_CRC_POLY ((uint32_t)0x00000040UL) /**< Offset from CTB Base Address: <tt> 0x0040</tt> */ 135 #define MXC_R_CTB_CRC_VAL ((uint32_t)0x00000044UL) /**< Offset from CTB Base Address: <tt> 0x0044</tt> */ 136 #define MXC_R_CTB_CRC_PRNG ((uint32_t)0x00000048UL) /**< Offset from CTB Base Address: <tt> 0x0048</tt> */ 137 #define MXC_R_CTB_HAM_ECC ((uint32_t)0x0000004CUL) /**< Offset from CTB Base Address: <tt> 0x004C</tt> */ 138 #define MXC_R_CTB_CIPHER_INIT ((uint32_t)0x00000050UL) /**< Offset from CTB Base Address: <tt> 0x0050</tt> */ 139 #define MXC_R_CTB_CIPHER_KEY ((uint32_t)0x00000060UL) /**< Offset from CTB Base Address: <tt> 0x0060</tt> */ 140 #define MXC_R_CTB_HASH_DIGEST ((uint32_t)0x00000080UL) /**< Offset from CTB Base Address: <tt> 0x0080</tt> */ 141 #define MXC_R_CTB_HASH_MSG_SZ ((uint32_t)0x000000C0UL) /**< Offset from CTB Base Address: <tt> 0x00C0</tt> */ 142 #define MXC_R_CTB_AAD_LENGTH ((uint32_t)0x000000D0UL) /**< Offset from CTB Base Address: <tt> 0x00D0</tt> */ 143 #define MXC_R_CTB_PLD_LENGTH ((uint32_t)0x000000D8UL) /**< Offset from CTB Base Address: <tt> 0x00D8</tt> */ 144 #define MXC_R_CTB_TAGMIC ((uint32_t)0x000000E0UL) /**< Offset from CTB Base Address: <tt> 0x00E0</tt> */ 145 #define MXC_R_CTB_MAA_MAWS ((uint32_t)0x000000F0UL) /**< Offset from CTB Base Address: <tt> 0x00F0</tt> */ 146 #define MXC_R_CTB_SCA_CTRL0 ((uint32_t)0x00000700UL) /**< Offset from CTB Base Address: <tt> 0x0700</tt> */ 147 #define MXC_R_CTB_SCA_CTRL1 ((uint32_t)0x00000704UL) /**< Offset from CTB Base Address: <tt> 0x0704</tt> */ 148 #define MXC_R_CTB_SCA_STAT ((uint32_t)0x00000708UL) /**< Offset from CTB Base Address: <tt> 0x0708</tt> */ 149 #define MXC_R_CTB_SCA_PPX_ADDR ((uint32_t)0x0000070CUL) /**< Offset from CTB Base Address: <tt> 0x070C</tt> */ 150 #define MXC_R_CTB_SCA_PPY_ADDR ((uint32_t)0x00000710UL) /**< Offset from CTB Base Address: <tt> 0x0710</tt> */ 151 #define MXC_R_CTB_SCA_PPZ_ADDR ((uint32_t)0x00000714UL) /**< Offset from CTB Base Address: <tt> 0x0714</tt> */ 152 #define MXC_R_CTB_SCA_PQX_ADDR ((uint32_t)0x00000718UL) /**< Offset from CTB Base Address: <tt> 0x0718</tt> */ 153 #define MXC_R_CTB_SCA_PQY_ADDR ((uint32_t)0x0000071CUL) /**< Offset from CTB Base Address: <tt> 0x071C</tt> */ 154 #define MXC_R_CTB_SCA_PQZ_ADDR ((uint32_t)0x00000720UL) /**< Offset from CTB Base Address: <tt> 0x0720</tt> */ 155 #define MXC_R_CTB_SCA_RDSA_ADDR ((uint32_t)0x00000724UL) /**< Offset from CTB Base Address: <tt> 0x0724</tt> */ 156 #define MXC_R_CTB_SCA_RES_ADDR ((uint32_t)0x00000728UL) /**< Offset from CTB Base Address: <tt> 0x0728</tt> */ 157 #define MXC_R_CTB_SCA_OP_BUFF_ADDR ((uint32_t)0x0000072CUL) /**< Offset from CTB Base Address: <tt> 0x072C</tt> */ 158 #define MXC_R_CTB_SCA_MODDATA ((uint32_t)0x00000730UL) /**< Offset from CTB Base Address: <tt> 0x0730</tt> */ 159 #define MXC_R_CTB_SCA_NRNG ((uint32_t)0x00000734UL) /**< Offset from CTB Base Address: <tt> 0x0734</tt> */ 160 #define MXC_R_CTB_SCA_WASH ((uint32_t)0x00000738UL) /**< Offset from CTB Base Address: <tt> 0x0738</tt> */ 161 /**@} end of group ctb_registers */ 162 163 /** 164 * @ingroup ctb_registers 165 * @defgroup CTB_CTRL CTB_CTRL 166 * @brief Crypto Control Register. 167 * @{ 168 */ 169 #define MXC_F_CTB_CTRL_RST_POS 0 /**< CTRL_RST Position */ 170 #define MXC_F_CTB_CTRL_RST ((uint32_t)(0x1UL << MXC_F_CTB_CTRL_RST_POS)) /**< CTRL_RST Mask */ 171 172 #define MXC_F_CTB_CTRL_INTR_POS 1 /**< CTRL_INTR Position */ 173 #define MXC_F_CTB_CTRL_INTR ((uint32_t)(0x1UL << MXC_F_CTB_CTRL_INTR_POS)) /**< CTRL_INTR Mask */ 174 175 #define MXC_F_CTB_CTRL_SRC_POS 2 /**< CTRL_SRC Position */ 176 #define MXC_F_CTB_CTRL_SRC ((uint32_t)(0x1UL << MXC_F_CTB_CTRL_SRC_POS)) /**< CTRL_SRC Mask */ 177 178 #define MXC_F_CTB_CTRL_BSO_POS 4 /**< CTRL_BSO Position */ 179 #define MXC_F_CTB_CTRL_BSO ((uint32_t)(0x1UL << MXC_F_CTB_CTRL_BSO_POS)) /**< CTRL_BSO Mask */ 180 181 #define MXC_F_CTB_CTRL_BSI_POS 5 /**< CTRL_BSI Position */ 182 #define MXC_F_CTB_CTRL_BSI ((uint32_t)(0x1UL << MXC_F_CTB_CTRL_BSI_POS)) /**< CTRL_BSI Mask */ 183 184 #define MXC_F_CTB_CTRL_WAIT_EN_POS 6 /**< CTRL_WAIT_EN Position */ 185 #define MXC_F_CTB_CTRL_WAIT_EN ((uint32_t)(0x1UL << MXC_F_CTB_CTRL_WAIT_EN_POS)) /**< CTRL_WAIT_EN Mask */ 186 187 #define MXC_F_CTB_CTRL_WAIT_POL_POS 7 /**< CTRL_WAIT_POL Position */ 188 #define MXC_F_CTB_CTRL_WAIT_POL ((uint32_t)(0x1UL << MXC_F_CTB_CTRL_WAIT_POL_POS)) /**< CTRL_WAIT_POL Mask */ 189 190 #define MXC_F_CTB_CTRL_WRSRC_POS 8 /**< CTRL_WRSRC Position */ 191 #define MXC_F_CTB_CTRL_WRSRC ((uint32_t)(0x3UL << MXC_F_CTB_CTRL_WRSRC_POS)) /**< CTRL_WRSRC Mask */ 192 #define MXC_V_CTB_CTRL_WRSRC_NONE ((uint32_t)0x0UL) /**< CTRL_WRSRC_NONE Value */ 193 #define MXC_S_CTB_CTRL_WRSRC_NONE (MXC_V_CTB_CTRL_WRSRC_NONE << MXC_F_CTB_CTRL_WRSRC_POS) /**< CTRL_WRSRC_NONE Setting */ 194 #define MXC_V_CTB_CTRL_WRSRC_CIPHEROUTPUT ((uint32_t)0x1UL) /**< CTRL_WRSRC_CIPHEROUTPUT Value */ 195 #define MXC_S_CTB_CTRL_WRSRC_CIPHEROUTPUT (MXC_V_CTB_CTRL_WRSRC_CIPHEROUTPUT << MXC_F_CTB_CTRL_WRSRC_POS) /**< CTRL_WRSRC_CIPHEROUTPUT Setting */ 196 #define MXC_V_CTB_CTRL_WRSRC_READFIFO ((uint32_t)0x2UL) /**< CTRL_WRSRC_READFIFO Value */ 197 #define MXC_S_CTB_CTRL_WRSRC_READFIFO (MXC_V_CTB_CTRL_WRSRC_READFIFO << MXC_F_CTB_CTRL_WRSRC_POS) /**< CTRL_WRSRC_READFIFO Setting */ 198 199 #define MXC_F_CTB_CTRL_RDSRC_POS 10 /**< CTRL_RDSRC Position */ 200 #define MXC_F_CTB_CTRL_RDSRC ((uint32_t)(0x3UL << MXC_F_CTB_CTRL_RDSRC_POS)) /**< CTRL_RDSRC Mask */ 201 #define MXC_V_CTB_CTRL_RDSRC_DMADISABLED ((uint32_t)0x0UL) /**< CTRL_RDSRC_DMADISABLED Value */ 202 #define MXC_S_CTB_CTRL_RDSRC_DMADISABLED (MXC_V_CTB_CTRL_RDSRC_DMADISABLED << MXC_F_CTB_CTRL_RDSRC_POS) /**< CTRL_RDSRC_DMADISABLED Setting */ 203 #define MXC_V_CTB_CTRL_RDSRC_DMAORAPB ((uint32_t)0x1UL) /**< CTRL_RDSRC_DMAORAPB Value */ 204 #define MXC_S_CTB_CTRL_RDSRC_DMAORAPB (MXC_V_CTB_CTRL_RDSRC_DMAORAPB << MXC_F_CTB_CTRL_RDSRC_POS) /**< CTRL_RDSRC_DMAORAPB Setting */ 205 #define MXC_V_CTB_CTRL_RDSRC_RNG ((uint32_t)0x2UL) /**< CTRL_RDSRC_RNG Value */ 206 #define MXC_S_CTB_CTRL_RDSRC_RNG (MXC_V_CTB_CTRL_RDSRC_RNG << MXC_F_CTB_CTRL_RDSRC_POS) /**< CTRL_RDSRC_RNG Setting */ 207 208 #define MXC_F_CTB_CTRL_FLAG_MODE_POS 14 /**< CTRL_FLAG_MODE Position */ 209 #define MXC_F_CTB_CTRL_FLAG_MODE ((uint32_t)(0x1UL << MXC_F_CTB_CTRL_FLAG_MODE_POS)) /**< CTRL_FLAG_MODE Mask */ 210 211 #define MXC_F_CTB_CTRL_DMADNEMSK_POS 15 /**< CTRL_DMADNEMSK Position */ 212 #define MXC_F_CTB_CTRL_DMADNEMSK ((uint32_t)(0x1UL << MXC_F_CTB_CTRL_DMADNEMSK_POS)) /**< CTRL_DMADNEMSK Mask */ 213 214 #define MXC_F_CTB_CTRL_DMA_DONE_POS 24 /**< CTRL_DMA_DONE Position */ 215 #define MXC_F_CTB_CTRL_DMA_DONE ((uint32_t)(0x1UL << MXC_F_CTB_CTRL_DMA_DONE_POS)) /**< CTRL_DMA_DONE Mask */ 216 217 #define MXC_F_CTB_CTRL_GLS_DONE_POS 25 /**< CTRL_GLS_DONE Position */ 218 #define MXC_F_CTB_CTRL_GLS_DONE ((uint32_t)(0x1UL << MXC_F_CTB_CTRL_GLS_DONE_POS)) /**< CTRL_GLS_DONE Mask */ 219 220 #define MXC_F_CTB_CTRL_HSH_DONE_POS 26 /**< CTRL_HSH_DONE Position */ 221 #define MXC_F_CTB_CTRL_HSH_DONE ((uint32_t)(0x1UL << MXC_F_CTB_CTRL_HSH_DONE_POS)) /**< CTRL_HSH_DONE Mask */ 222 223 #define MXC_F_CTB_CTRL_CPH_DONE_POS 27 /**< CTRL_CPH_DONE Position */ 224 #define MXC_F_CTB_CTRL_CPH_DONE ((uint32_t)(0x1UL << MXC_F_CTB_CTRL_CPH_DONE_POS)) /**< CTRL_CPH_DONE Mask */ 225 226 #define MXC_F_CTB_CTRL_ERR_POS 29 /**< CTRL_ERR Position */ 227 #define MXC_F_CTB_CTRL_ERR ((uint32_t)(0x1UL << MXC_F_CTB_CTRL_ERR_POS)) /**< CTRL_ERR Mask */ 228 229 #define MXC_F_CTB_CTRL_RDY_POS 30 /**< CTRL_RDY Position */ 230 #define MXC_F_CTB_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_CTB_CTRL_RDY_POS)) /**< CTRL_RDY Mask */ 231 232 #define MXC_F_CTB_CTRL_DONE_POS 31 /**< CTRL_DONE Position */ 233 #define MXC_F_CTB_CTRL_DONE ((uint32_t)(0x1UL << MXC_F_CTB_CTRL_DONE_POS)) /**< CTRL_DONE Mask */ 234 235 /**@} end of group CTB_CTRL_Register */ 236 237 /** 238 * @ingroup ctb_registers 239 * @defgroup CTB_CIPHER_CTRL CTB_CIPHER_CTRL 240 * @brief Cipher Control Register. 241 * @{ 242 */ 243 #define MXC_F_CTB_CIPHER_CTRL_ENC_POS 0 /**< CIPHER_CTRL_ENC Position */ 244 #define MXC_F_CTB_CIPHER_CTRL_ENC ((uint32_t)(0x1UL << MXC_F_CTB_CIPHER_CTRL_ENC_POS)) /**< CIPHER_CTRL_ENC Mask */ 245 246 #define MXC_F_CTB_CIPHER_CTRL_KEY_POS 1 /**< CIPHER_CTRL_KEY Position */ 247 #define MXC_F_CTB_CIPHER_CTRL_KEY ((uint32_t)(0x1UL << MXC_F_CTB_CIPHER_CTRL_KEY_POS)) /**< CIPHER_CTRL_KEY Mask */ 248 249 #define MXC_F_CTB_CIPHER_CTRL_SRC_POS 2 /**< CIPHER_CTRL_SRC Position */ 250 #define MXC_F_CTB_CIPHER_CTRL_SRC ((uint32_t)(0x3UL << MXC_F_CTB_CIPHER_CTRL_SRC_POS)) /**< CIPHER_CTRL_SRC Mask */ 251 #define MXC_V_CTB_CIPHER_CTRL_SRC_CIPHERKEY ((uint32_t)0x0UL) /**< CIPHER_CTRL_SRC_CIPHERKEY Value */ 252 #define MXC_S_CTB_CIPHER_CTRL_SRC_CIPHERKEY (MXC_V_CTB_CIPHER_CTRL_SRC_CIPHERKEY << MXC_F_CTB_CIPHER_CTRL_SRC_POS) /**< CIPHER_CTRL_SRC_CIPHERKEY Setting */ 253 #define MXC_V_CTB_CIPHER_CTRL_SRC_REGFILE ((uint32_t)0x2UL) /**< CIPHER_CTRL_SRC_REGFILE Value */ 254 #define MXC_S_CTB_CIPHER_CTRL_SRC_REGFILE (MXC_V_CTB_CIPHER_CTRL_SRC_REGFILE << MXC_F_CTB_CIPHER_CTRL_SRC_POS) /**< CIPHER_CTRL_SRC_REGFILE Setting */ 255 #define MXC_V_CTB_CIPHER_CTRL_SRC_QSPIKEY_REGFILE ((uint32_t)0x3UL) /**< CIPHER_CTRL_SRC_QSPIKEY_REGFILE Value */ 256 #define MXC_S_CTB_CIPHER_CTRL_SRC_QSPIKEY_REGFILE (MXC_V_CTB_CIPHER_CTRL_SRC_QSPIKEY_REGFILE << MXC_F_CTB_CIPHER_CTRL_SRC_POS) /**< CIPHER_CTRL_SRC_QSPIKEY_REGFILE Setting */ 257 258 #define MXC_F_CTB_CIPHER_CTRL_CIPHER_POS 4 /**< CIPHER_CTRL_CIPHER Position */ 259 #define MXC_F_CTB_CIPHER_CTRL_CIPHER ((uint32_t)(0x7UL << MXC_F_CTB_CIPHER_CTRL_CIPHER_POS)) /**< CIPHER_CTRL_CIPHER Mask */ 260 #define MXC_V_CTB_CIPHER_CTRL_CIPHER_DIS ((uint32_t)0x0UL) /**< CIPHER_CTRL_CIPHER_DIS Value */ 261 #define MXC_S_CTB_CIPHER_CTRL_CIPHER_DIS (MXC_V_CTB_CIPHER_CTRL_CIPHER_DIS << MXC_F_CTB_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_DIS Setting */ 262 #define MXC_V_CTB_CIPHER_CTRL_CIPHER_AES128 ((uint32_t)0x1UL) /**< CIPHER_CTRL_CIPHER_AES128 Value */ 263 #define MXC_S_CTB_CIPHER_CTRL_CIPHER_AES128 (MXC_V_CTB_CIPHER_CTRL_CIPHER_AES128 << MXC_F_CTB_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_AES128 Setting */ 264 #define MXC_V_CTB_CIPHER_CTRL_CIPHER_AES192 ((uint32_t)0x2UL) /**< CIPHER_CTRL_CIPHER_AES192 Value */ 265 #define MXC_S_CTB_CIPHER_CTRL_CIPHER_AES192 (MXC_V_CTB_CIPHER_CTRL_CIPHER_AES192 << MXC_F_CTB_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_AES192 Setting */ 266 #define MXC_V_CTB_CIPHER_CTRL_CIPHER_AES256 ((uint32_t)0x3UL) /**< CIPHER_CTRL_CIPHER_AES256 Value */ 267 #define MXC_S_CTB_CIPHER_CTRL_CIPHER_AES256 (MXC_V_CTB_CIPHER_CTRL_CIPHER_AES256 << MXC_F_CTB_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_AES256 Setting */ 268 #define MXC_V_CTB_CIPHER_CTRL_CIPHER_DES ((uint32_t)0x4UL) /**< CIPHER_CTRL_CIPHER_DES Value */ 269 #define MXC_S_CTB_CIPHER_CTRL_CIPHER_DES (MXC_V_CTB_CIPHER_CTRL_CIPHER_DES << MXC_F_CTB_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_DES Setting */ 270 #define MXC_V_CTB_CIPHER_CTRL_CIPHER_TDES ((uint32_t)0x5UL) /**< CIPHER_CTRL_CIPHER_TDES Value */ 271 #define MXC_S_CTB_CIPHER_CTRL_CIPHER_TDES (MXC_V_CTB_CIPHER_CTRL_CIPHER_TDES << MXC_F_CTB_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_TDES Setting */ 272 273 #define MXC_F_CTB_CIPHER_CTRL_MODE_POS 8 /**< CIPHER_CTRL_MODE Position */ 274 #define MXC_F_CTB_CIPHER_CTRL_MODE ((uint32_t)(0x7UL << MXC_F_CTB_CIPHER_CTRL_MODE_POS)) /**< CIPHER_CTRL_MODE Mask */ 275 #define MXC_V_CTB_CIPHER_CTRL_MODE_ECB ((uint32_t)0x0UL) /**< CIPHER_CTRL_MODE_ECB Value */ 276 #define MXC_S_CTB_CIPHER_CTRL_MODE_ECB (MXC_V_CTB_CIPHER_CTRL_MODE_ECB << MXC_F_CTB_CIPHER_CTRL_MODE_POS) /**< CIPHER_CTRL_MODE_ECB Setting */ 277 #define MXC_V_CTB_CIPHER_CTRL_MODE_CBC ((uint32_t)0x1UL) /**< CIPHER_CTRL_MODE_CBC Value */ 278 #define MXC_S_CTB_CIPHER_CTRL_MODE_CBC (MXC_V_CTB_CIPHER_CTRL_MODE_CBC << MXC_F_CTB_CIPHER_CTRL_MODE_POS) /**< CIPHER_CTRL_MODE_CBC Setting */ 279 #define MXC_V_CTB_CIPHER_CTRL_MODE_CFB ((uint32_t)0x2UL) /**< CIPHER_CTRL_MODE_CFB Value */ 280 #define MXC_S_CTB_CIPHER_CTRL_MODE_CFB (MXC_V_CTB_CIPHER_CTRL_MODE_CFB << MXC_F_CTB_CIPHER_CTRL_MODE_POS) /**< CIPHER_CTRL_MODE_CFB Setting */ 281 #define MXC_V_CTB_CIPHER_CTRL_MODE_OFB ((uint32_t)0x3UL) /**< CIPHER_CTRL_MODE_OFB Value */ 282 #define MXC_S_CTB_CIPHER_CTRL_MODE_OFB (MXC_V_CTB_CIPHER_CTRL_MODE_OFB << MXC_F_CTB_CIPHER_CTRL_MODE_POS) /**< CIPHER_CTRL_MODE_OFB Setting */ 283 #define MXC_V_CTB_CIPHER_CTRL_MODE_CTR ((uint32_t)0x4UL) /**< CIPHER_CTRL_MODE_CTR Value */ 284 #define MXC_S_CTB_CIPHER_CTRL_MODE_CTR (MXC_V_CTB_CIPHER_CTRL_MODE_CTR << MXC_F_CTB_CIPHER_CTRL_MODE_POS) /**< CIPHER_CTRL_MODE_CTR Setting */ 285 286 #define MXC_F_CTB_CIPHER_CTRL_HVC_POS 11 /**< CIPHER_CTRL_HVC Position */ 287 #define MXC_F_CTB_CIPHER_CTRL_HVC ((uint32_t)(0x1UL << MXC_F_CTB_CIPHER_CTRL_HVC_POS)) /**< CIPHER_CTRL_HVC Mask */ 288 289 #define MXC_F_CTB_CIPHER_CTRL_DTYPE_POS 12 /**< CIPHER_CTRL_DTYPE Position */ 290 #define MXC_F_CTB_CIPHER_CTRL_DTYPE ((uint32_t)(0x1UL << MXC_F_CTB_CIPHER_CTRL_DTYPE_POS)) /**< CIPHER_CTRL_DTYPE Mask */ 291 292 #define MXC_F_CTB_CIPHER_CTRL_CCMM_POS 13 /**< CIPHER_CTRL_CCMM Position */ 293 #define MXC_F_CTB_CIPHER_CTRL_CCMM ((uint32_t)(0x7UL << MXC_F_CTB_CIPHER_CTRL_CCMM_POS)) /**< CIPHER_CTRL_CCMM Mask */ 294 295 #define MXC_F_CTB_CIPHER_CTRL_CCML_POS 16 /**< CIPHER_CTRL_CCML Position */ 296 #define MXC_F_CTB_CIPHER_CTRL_CCML ((uint32_t)(0x7UL << MXC_F_CTB_CIPHER_CTRL_CCML_POS)) /**< CIPHER_CTRL_CCML Mask */ 297 298 /**@} end of group CTB_CIPHER_CTRL_Register */ 299 300 /** 301 * @ingroup ctb_registers 302 * @defgroup CTB_HASH_CTRL CTB_HASH_CTRL 303 * @brief HASH Control Register. 304 * @{ 305 */ 306 #define MXC_F_CTB_HASH_CTRL_INIT_POS 0 /**< HASH_CTRL_INIT Position */ 307 #define MXC_F_CTB_HASH_CTRL_INIT ((uint32_t)(0x1UL << MXC_F_CTB_HASH_CTRL_INIT_POS)) /**< HASH_CTRL_INIT Mask */ 308 309 #define MXC_F_CTB_HASH_CTRL_XOR_POS 1 /**< HASH_CTRL_XOR Position */ 310 #define MXC_F_CTB_HASH_CTRL_XOR ((uint32_t)(0x1UL << MXC_F_CTB_HASH_CTRL_XOR_POS)) /**< HASH_CTRL_XOR Mask */ 311 312 #define MXC_F_CTB_HASH_CTRL_HASH_POS 2 /**< HASH_CTRL_HASH Position */ 313 #define MXC_F_CTB_HASH_CTRL_HASH ((uint32_t)(0x7UL << MXC_F_CTB_HASH_CTRL_HASH_POS)) /**< HASH_CTRL_HASH Mask */ 314 #define MXC_V_CTB_HASH_CTRL_HASH_DIS ((uint32_t)0x0UL) /**< HASH_CTRL_HASH_DIS Value */ 315 #define MXC_S_CTB_HASH_CTRL_HASH_DIS (MXC_V_CTB_HASH_CTRL_HASH_DIS << MXC_F_CTB_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_DIS Setting */ 316 #define MXC_V_CTB_HASH_CTRL_HASH_SHA1 ((uint32_t)0x1UL) /**< HASH_CTRL_HASH_SHA1 Value */ 317 #define MXC_S_CTB_HASH_CTRL_HASH_SHA1 (MXC_V_CTB_HASH_CTRL_HASH_SHA1 << MXC_F_CTB_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_SHA1 Setting */ 318 #define MXC_V_CTB_HASH_CTRL_HASH_SHA224 ((uint32_t)0x2UL) /**< HASH_CTRL_HASH_SHA224 Value */ 319 #define MXC_S_CTB_HASH_CTRL_HASH_SHA224 (MXC_V_CTB_HASH_CTRL_HASH_SHA224 << MXC_F_CTB_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_SHA224 Setting */ 320 #define MXC_V_CTB_HASH_CTRL_HASH_SHA256 ((uint32_t)0x3UL) /**< HASH_CTRL_HASH_SHA256 Value */ 321 #define MXC_S_CTB_HASH_CTRL_HASH_SHA256 (MXC_V_CTB_HASH_CTRL_HASH_SHA256 << MXC_F_CTB_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_SHA256 Setting */ 322 #define MXC_V_CTB_HASH_CTRL_HASH_SHA384 ((uint32_t)0x4UL) /**< HASH_CTRL_HASH_SHA384 Value */ 323 #define MXC_S_CTB_HASH_CTRL_HASH_SHA384 (MXC_V_CTB_HASH_CTRL_HASH_SHA384 << MXC_F_CTB_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_SHA384 Setting */ 324 #define MXC_V_CTB_HASH_CTRL_HASH_SHA512 ((uint32_t)0x5UL) /**< HASH_CTRL_HASH_SHA512 Value */ 325 #define MXC_S_CTB_HASH_CTRL_HASH_SHA512 (MXC_V_CTB_HASH_CTRL_HASH_SHA512 << MXC_F_CTB_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_SHA512 Setting */ 326 327 #define MXC_F_CTB_HASH_CTRL_LAST_POS 5 /**< HASH_CTRL_LAST Position */ 328 #define MXC_F_CTB_HASH_CTRL_LAST ((uint32_t)(0x1UL << MXC_F_CTB_HASH_CTRL_LAST_POS)) /**< HASH_CTRL_LAST Mask */ 329 330 /**@} end of group CTB_HASH_CTRL_Register */ 331 332 /** 333 * @ingroup ctb_registers 334 * @defgroup CTB_CRC_CTRL CTB_CRC_CTRL 335 * @brief CRC Control Register. 336 * @{ 337 */ 338 #define MXC_F_CTB_CRC_CTRL_CRC_POS 0 /**< CRC_CTRL_CRC Position */ 339 #define MXC_F_CTB_CRC_CTRL_CRC ((uint32_t)(0x1UL << MXC_F_CTB_CRC_CTRL_CRC_POS)) /**< CRC_CTRL_CRC Mask */ 340 341 #define MXC_F_CTB_CRC_CTRL_MSB_POS 1 /**< CRC_CTRL_MSB Position */ 342 #define MXC_F_CTB_CRC_CTRL_MSB ((uint32_t)(0x1UL << MXC_F_CTB_CRC_CTRL_MSB_POS)) /**< CRC_CTRL_MSB Mask */ 343 344 #define MXC_F_CTB_CRC_CTRL_PRNG_POS 2 /**< CRC_CTRL_PRNG Position */ 345 #define MXC_F_CTB_CRC_CTRL_PRNG ((uint32_t)(0x1UL << MXC_F_CTB_CRC_CTRL_PRNG_POS)) /**< CRC_CTRL_PRNG Mask */ 346 347 #define MXC_F_CTB_CRC_CTRL_ENT_POS 3 /**< CRC_CTRL_ENT Position */ 348 #define MXC_F_CTB_CRC_CTRL_ENT ((uint32_t)(0x1UL << MXC_F_CTB_CRC_CTRL_ENT_POS)) /**< CRC_CTRL_ENT Mask */ 349 350 #define MXC_F_CTB_CRC_CTRL_HAM_POS 4 /**< CRC_CTRL_HAM Position */ 351 #define MXC_F_CTB_CRC_CTRL_HAM ((uint32_t)(0x1UL << MXC_F_CTB_CRC_CTRL_HAM_POS)) /**< CRC_CTRL_HAM Mask */ 352 353 #define MXC_F_CTB_CRC_CTRL_HRST_POS 5 /**< CRC_CTRL_HRST Position */ 354 #define MXC_F_CTB_CRC_CTRL_HRST ((uint32_t)(0x1UL << MXC_F_CTB_CRC_CTRL_HRST_POS)) /**< CRC_CTRL_HRST Mask */ 355 356 /**@} end of group CTB_CRC_CTRL_Register */ 357 358 /** 359 * @ingroup ctb_registers 360 * @defgroup CTB_DMA_SRC CTB_DMA_SRC 361 * @brief Crypto DMA Source Address. 362 * @{ 363 */ 364 #define MXC_F_CTB_DMA_SRC_ADDR_POS 0 /**< DMA_SRC_ADDR Position */ 365 #define MXC_F_CTB_DMA_SRC_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_DMA_SRC_ADDR_POS)) /**< DMA_SRC_ADDR Mask */ 366 367 /**@} end of group CTB_DMA_SRC_Register */ 368 369 /** 370 * @ingroup ctb_registers 371 * @defgroup CTB_DMA_DEST CTB_DMA_DEST 372 * @brief Crypto DMA Destination Address. 373 * @{ 374 */ 375 #define MXC_F_CTB_DMA_DEST_ADDR_POS 0 /**< DMA_DEST_ADDR Position */ 376 #define MXC_F_CTB_DMA_DEST_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_DMA_DEST_ADDR_POS)) /**< DMA_DEST_ADDR Mask */ 377 378 /**@} end of group CTB_DMA_DEST_Register */ 379 380 /** 381 * @ingroup ctb_registers 382 * @defgroup CTB_DMA_CNT CTB_DMA_CNT 383 * @brief Crypto DMA Byte Count. 384 * @{ 385 */ 386 #define MXC_F_CTB_DMA_CNT_ADDR_POS 0 /**< DMA_CNT_ADDR Position */ 387 #define MXC_F_CTB_DMA_CNT_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_DMA_CNT_ADDR_POS)) /**< DMA_CNT_ADDR Mask */ 388 389 /**@} end of group CTB_DMA_CNT_Register */ 390 391 /** 392 * @ingroup ctb_registers 393 * @defgroup CTB_DIN CTB_DIN 394 * @brief Crypto Data Input. Data input can be written to this register instead of using 395 * the DMA. This register writes to the FIFO. This register occupies four 396 * successive words to allow the use of multi-store instructions. Words can be 397 * written to any location, they will be placed in the FIFO in the order they are 398 * written. The endian swap input control bit affects this register. 399 * @{ 400 */ 401 #define MXC_F_CTB_DIN_DATA_POS 0 /**< DIN_DATA Position */ 402 #define MXC_F_CTB_DIN_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_DIN_DATA_POS)) /**< DIN_DATA Mask */ 403 404 /**@} end of group CTB_DIN_Register */ 405 406 /** 407 * @ingroup ctb_registers 408 * @defgroup CTB_DOUT CTB_DOUT 409 * @brief Crypto Data Output. Resulting data from cipher calculation. Data is placed in 410 * the lower words of these four registers depending on the algorithm. For block 411 * cipher modes, this register holds the result of most recent encryption or 412 * decryption operation. These registers are affected by the endian swap bits. 413 * @{ 414 */ 415 #define MXC_F_CTB_DOUT_DATA_POS 0 /**< DOUT_DATA Position */ 416 #define MXC_F_CTB_DOUT_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_DOUT_DATA_POS)) /**< DOUT_DATA Mask */ 417 418 /**@} end of group CTB_DOUT_Register */ 419 420 /** 421 * @ingroup ctb_registers 422 * @defgroup CTB_CRC_POLY CTB_CRC_POLY 423 * @brief CRC Polynomial. The polynomial to be used for Galois Field calculations (CRC or 424 * LFSR) should be written to this register. This register is affected by the MSB 425 * control bit. 426 * @{ 427 */ 428 #define MXC_F_CTB_CRC_POLY_POLY_POS 0 /**< CRC_POLY_POLY Position */ 429 #define MXC_F_CTB_CRC_POLY_POLY ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_CRC_POLY_POLY_POS)) /**< CRC_POLY_POLY Mask */ 430 431 /**@} end of group CTB_CRC_POLY_Register */ 432 433 /** 434 * @ingroup ctb_registers 435 * @defgroup CTB_CRC_VAL CTB_CRC_VAL 436 * @brief CRC Value. This is the state for the Galois Field. This register holds the 437 * result of a CRC calculation or the current state of the LFSR. This register is 438 * affected by the MSB control bit. 439 * @{ 440 */ 441 #define MXC_F_CTB_CRC_VAL_VAL_POS 0 /**< CRC_VAL_VAL Position */ 442 #define MXC_F_CTB_CRC_VAL_VAL ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_CRC_VAL_VAL_POS)) /**< CRC_VAL_VAL Mask */ 443 444 /**@} end of group CTB_CRC_VAL_Register */ 445 446 /** 447 * @ingroup ctb_registers 448 * @defgroup CTB_CRC_PRNG CTB_CRC_PRNG 449 * @brief CRC PRNG Register. 450 * @{ 451 */ 452 #define MXC_F_CTB_CRC_PRNG_PRNG_POS 0 /**< CRC_PRNG_PRNG Position */ 453 #define MXC_F_CTB_CRC_PRNG_PRNG ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_CRC_PRNG_PRNG_POS)) /**< CRC_PRNG_PRNG Mask */ 454 455 /**@} end of group CTB_CRC_PRNG_Register */ 456 457 /** 458 * @ingroup ctb_registers 459 * @defgroup CTB_HAM_ECC CTB_HAM_ECC 460 * @brief Hamming ECC Register. 461 * @{ 462 */ 463 #define MXC_F_CTB_HAM_ECC_ECC_POS 0 /**< HAM_ECC_ECC Position */ 464 #define MXC_F_CTB_HAM_ECC_ECC ((uint32_t)(0xFFFFUL << MXC_F_CTB_HAM_ECC_ECC_POS)) /**< HAM_ECC_ECC Mask */ 465 466 #define MXC_F_CTB_HAM_ECC_PAR_POS 16 /**< HAM_ECC_PAR Position */ 467 #define MXC_F_CTB_HAM_ECC_PAR ((uint32_t)(0x1UL << MXC_F_CTB_HAM_ECC_PAR_POS)) /**< HAM_ECC_PAR Mask */ 468 469 /**@} end of group CTB_HAM_ECC_Register */ 470 471 /** 472 * @ingroup ctb_registers 473 * @defgroup CTB_CIPHER_INIT CTB_CIPHER_INIT 474 * @brief Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR 475 * modes, this register holds the initial value. This register is updated with each 476 * encryption or decryption operation. This register is affected by the endian swap 477 * bits. 478 * @{ 479 */ 480 #define MXC_F_CTB_CIPHER_INIT_IVEC_POS 0 /**< CIPHER_INIT_IVEC Position */ 481 #define MXC_F_CTB_CIPHER_INIT_IVEC ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_CIPHER_INIT_IVEC_POS)) /**< CIPHER_INIT_IVEC Mask */ 482 483 /**@} end of group CTB_CIPHER_INIT_Register */ 484 485 /** 486 * @ingroup ctb_registers 487 * @defgroup CTB_CIPHER_KEY CTB_CIPHER_KEY 488 * @brief Cipher Key. This register holds the key used for block cipher operations. The 489 * lower words are used for block ciphers that use shorter key lengths. This 490 * register is affected by the endian swap input control bits. 491 * @{ 492 */ 493 #define MXC_F_CTB_CIPHER_KEY_KEY_POS 0 /**< CIPHER_KEY_KEY Position */ 494 #define MXC_F_CTB_CIPHER_KEY_KEY ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_CIPHER_KEY_KEY_POS)) /**< CIPHER_KEY_KEY Mask */ 495 496 /**@} end of group CTB_CIPHER_KEY_Register */ 497 498 /** 499 * @ingroup ctb_registers 500 * @defgroup CTB_HASH_DIGEST CTB_HASH_DIGEST 501 * @brief This register holds the calculated hash value. This register is affected by the 502 * endian swap bits. 503 * @{ 504 */ 505 #define MXC_F_CTB_HASH_DIGEST_HASH_POS 0 /**< HASH_DIGEST_HASH Position */ 506 #define MXC_F_CTB_HASH_DIGEST_HASH ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_HASH_DIGEST_HASH_POS)) /**< HASH_DIGEST_HASH Mask */ 507 508 /**@} end of group CTB_HASH_DIGEST_Register */ 509 510 /** 511 * @ingroup ctb_registers 512 * @defgroup CTB_HASH_MSG_SZ CTB_HASH_MSG_SZ 513 * @brief Message Size. This register holds the lowest 32-bit of message size in bytes. 514 * @{ 515 */ 516 #define MXC_F_CTB_HASH_MSG_SZ_MSGSZ_POS 0 /**< HASH_MSG_SZ_MSGSZ Position */ 517 #define MXC_F_CTB_HASH_MSG_SZ_MSGSZ ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_HASH_MSG_SZ_MSGSZ_POS)) /**< HASH_MSG_SZ_MSGSZ Mask */ 518 519 /**@} end of group CTB_HASH_MSG_SZ_Register */ 520 521 /** 522 * @ingroup ctb_registers 523 * @defgroup CTB_AAD_LENGTH CTB_AAD_LENGTH 524 * @brief AAD Length Registers. 525 * @{ 526 */ 527 #define MXC_F_CTB_AAD_LENGTH_LENGTH_POS 0 /**< AAD_LENGTH_LENGTH Position */ 528 #define MXC_F_CTB_AAD_LENGTH_LENGTH ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_AAD_LENGTH_LENGTH_POS)) /**< AAD_LENGTH_LENGTH Mask */ 529 530 /**@} end of group CTB_AAD_LENGTH_Register */ 531 532 /** 533 * @ingroup ctb_registers 534 * @defgroup CTB_PLD_LENGTH CTB_PLD_LENGTH 535 * @brief PLD Length Registers. 536 * @{ 537 */ 538 #define MXC_F_CTB_PLD_LENGTH_LENGTH_POS 0 /**< PLD_LENGTH_LENGTH Position */ 539 #define MXC_F_CTB_PLD_LENGTH_LENGTH ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_PLD_LENGTH_LENGTH_POS)) /**< PLD_LENGTH_LENGTH Mask */ 540 541 /**@} end of group CTB_PLD_LENGTH_Register */ 542 543 /** 544 * @ingroup ctb_registers 545 * @defgroup CTB_TAGMIC CTB_TAGMIC 546 * @brief TAG/MIC Registers. 547 * @{ 548 */ 549 #define MXC_F_CTB_TAGMIC_LENGTH_POS 0 /**< TAGMIC_LENGTH Position */ 550 #define MXC_F_CTB_TAGMIC_LENGTH ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_TAGMIC_LENGTH_POS)) /**< TAGMIC_LENGTH Mask */ 551 552 /**@} end of group CTB_TAGMIC_Register */ 553 554 /** 555 * @ingroup ctb_registers 556 * @defgroup CTB_MAA_MAWS CTB_MAA_MAWS 557 * @brief MAA Word Size Register. 558 * @{ 559 */ 560 #define MXC_F_CTB_MAA_MAWS_SIZE_POS 0 /**< MAA_MAWS_SIZE Position */ 561 #define MXC_F_CTB_MAA_MAWS_SIZE ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_MAA_MAWS_SIZE_POS)) /**< MAA_MAWS_SIZE Mask */ 562 563 /**@} end of group CTB_MAA_MAWS_Register */ 564 565 /** 566 * @ingroup ctb_registers 567 * @defgroup CTB_SCA_CTRL0 CTB_SCA_CTRL0 568 * @brief SCA Control 0 Register. 569 * @{ 570 */ 571 #define MXC_F_CTB_SCA_CTRL0_STC_POS 0 /**< SCA_CTRL0_STC Position */ 572 #define MXC_F_CTB_SCA_CTRL0_STC ((uint32_t)(0x1UL << MXC_F_CTB_SCA_CTRL0_STC_POS)) /**< SCA_CTRL0_STC Mask */ 573 574 #define MXC_F_CTB_SCA_CTRL0_SCAIE_POS 1 /**< SCA_CTRL0_SCAIE Position */ 575 #define MXC_F_CTB_SCA_CTRL0_SCAIE ((uint32_t)(0x1UL << MXC_F_CTB_SCA_CTRL0_SCAIE_POS)) /**< SCA_CTRL0_SCAIE Mask */ 576 577 #define MXC_F_CTB_SCA_CTRL0_ABORT_POS 2 /**< SCA_CTRL0_ABORT Position */ 578 #define MXC_F_CTB_SCA_CTRL0_ABORT ((uint32_t)(0x1UL << MXC_F_CTB_SCA_CTRL0_ABORT_POS)) /**< SCA_CTRL0_ABORT Mask */ 579 580 #define MXC_F_CTB_SCA_CTRL0_AFFJAC_POS 3 /**< SCA_CTRL0_AFFJAC Position */ 581 #define MXC_F_CTB_SCA_CTRL0_AFFJAC ((uint32_t)(0x1UL << MXC_F_CTB_SCA_CTRL0_AFFJAC_POS)) /**< SCA_CTRL0_AFFJAC Mask */ 582 583 #define MXC_F_CTB_SCA_CTRL0_ERMEM_POS 4 /**< SCA_CTRL0_ERMEM Position */ 584 #define MXC_F_CTB_SCA_CTRL0_ERMEM ((uint32_t)(0x1UL << MXC_F_CTB_SCA_CTRL0_ERMEM_POS)) /**< SCA_CTRL0_ERMEM Mask */ 585 586 #define MXC_F_CTB_SCA_CTRL0_MANPARAM_POS 5 /**< SCA_CTRL0_MANPARAM Position */ 587 #define MXC_F_CTB_SCA_CTRL0_MANPARAM ((uint32_t)(0x1UL << MXC_F_CTB_SCA_CTRL0_MANPARAM_POS)) /**< SCA_CTRL0_MANPARAM Mask */ 588 589 #define MXC_F_CTB_SCA_CTRL0_HWKEY_POS 6 /**< SCA_CTRL0_HWKEY Position */ 590 #define MXC_F_CTB_SCA_CTRL0_HWKEY ((uint32_t)(0x1UL << MXC_F_CTB_SCA_CTRL0_HWKEY_POS)) /**< SCA_CTRL0_HWKEY Mask */ 591 592 #define MXC_F_CTB_SCA_CTRL0_OPCODE_POS 8 /**< SCA_CTRL0_OPCODE Position */ 593 #define MXC_F_CTB_SCA_CTRL0_OPCODE ((uint32_t)(0x1FUL << MXC_F_CTB_SCA_CTRL0_OPCODE_POS)) /**< SCA_CTRL0_OPCODE Mask */ 594 595 #define MXC_F_CTB_SCA_CTRL0_MODADDR_POS 16 /**< SCA_CTRL0_MODADDR Position */ 596 #define MXC_F_CTB_SCA_CTRL0_MODADDR ((uint32_t)(0x1FUL << MXC_F_CTB_SCA_CTRL0_MODADDR_POS)) /**< SCA_CTRL0_MODADDR Mask */ 597 598 #define MXC_F_CTB_SCA_CTRL0_ECCSIZE_POS 24 /**< SCA_CTRL0_ECCSIZE Position */ 599 #define MXC_F_CTB_SCA_CTRL0_ECCSIZE ((uint32_t)(0x3UL << MXC_F_CTB_SCA_CTRL0_ECCSIZE_POS)) /**< SCA_CTRL0_ECCSIZE Mask */ 600 601 /**@} end of group CTB_SCA_CTRL0_Register */ 602 603 /** 604 * @ingroup ctb_registers 605 * @defgroup CTB_SCA_CTRL1 CTB_SCA_CTRL1 606 * @brief SCA Advanced Control Register. 607 * @{ 608 */ 609 #define MXC_F_CTB_SCA_CTRL1_MAN_POS 0 /**< SCA_CTRL1_MAN Position */ 610 #define MXC_F_CTB_SCA_CTRL1_MAN ((uint32_t)(0x1UL << MXC_F_CTB_SCA_CTRL1_MAN_POS)) /**< SCA_CTRL1_MAN Mask */ 611 612 #define MXC_F_CTB_SCA_CTRL1_AUTOCARRY_POS 1 /**< SCA_CTRL1_AUTOCARRY Position */ 613 #define MXC_F_CTB_SCA_CTRL1_AUTOCARRY ((uint32_t)(0x1UL << MXC_F_CTB_SCA_CTRL1_AUTOCARRY_POS)) /**< SCA_CTRL1_AUTOCARRY Mask */ 614 615 #define MXC_F_CTB_SCA_CTRL1_PLUSONE_POS 2 /**< SCA_CTRL1_PLUSONE Position */ 616 #define MXC_F_CTB_SCA_CTRL1_PLUSONE ((uint32_t)(0x1UL << MXC_F_CTB_SCA_CTRL1_PLUSONE_POS)) /**< SCA_CTRL1_PLUSONE Mask */ 617 618 #define MXC_F_CTB_SCA_CTRL1_RESSELECT_POS 3 /**< SCA_CTRL1_RESSELECT Position */ 619 #define MXC_F_CTB_SCA_CTRL1_RESSELECT ((uint32_t)(0x3UL << MXC_F_CTB_SCA_CTRL1_RESSELECT_POS)) /**< SCA_CTRL1_RESSELECT Mask */ 620 621 #define MXC_F_CTB_SCA_CTRL1_NRNG_POS 5 /**< SCA_CTRL1_NRNG Position */ 622 #define MXC_F_CTB_SCA_CTRL1_NRNG ((uint32_t)(0x1UL << MXC_F_CTB_SCA_CTRL1_NRNG_POS)) /**< SCA_CTRL1_NRNG Mask */ 623 624 #define MXC_F_CTB_SCA_CTRL1_CARRYPOS_POS 8 /**< SCA_CTRL1_CARRYPOS Position */ 625 #define MXC_F_CTB_SCA_CTRL1_CARRYPOS ((uint32_t)(0x3FFUL << MXC_F_CTB_SCA_CTRL1_CARRYPOS_POS)) /**< SCA_CTRL1_CARRYPOS Mask */ 626 627 #define MXC_F_CTB_SCA_CTRL1_CM_EN_POS 20 /**< SCA_CTRL1_CM_EN Position */ 628 #define MXC_F_CTB_SCA_CTRL1_CM_EN ((uint32_t)(0xFFFUL << MXC_F_CTB_SCA_CTRL1_CM_EN_POS)) /**< SCA_CTRL1_CM_EN Mask */ 629 630 /**@} end of group CTB_SCA_CTRL1_Register */ 631 632 /** 633 * @ingroup ctb_registers 634 * @defgroup CTB_SCA_STAT CTB_SCA_STAT 635 * @brief SCA Status Register. 636 * @{ 637 */ 638 #define MXC_F_CTB_SCA_STAT_BUSY_POS 0 /**< SCA_STAT_BUSY Position */ 639 #define MXC_F_CTB_SCA_STAT_BUSY ((uint32_t)(0x1UL << MXC_F_CTB_SCA_STAT_BUSY_POS)) /**< SCA_STAT_BUSY Mask */ 640 641 #define MXC_F_CTB_SCA_STAT_SCAIF_POS 1 /**< SCA_STAT_SCAIF Position */ 642 #define MXC_F_CTB_SCA_STAT_SCAIF ((uint32_t)(0x1UL << MXC_F_CTB_SCA_STAT_SCAIF_POS)) /**< SCA_STAT_SCAIF Mask */ 643 644 #define MXC_F_CTB_SCA_STAT_PVF1_POS 2 /**< SCA_STAT_PVF1 Position */ 645 #define MXC_F_CTB_SCA_STAT_PVF1 ((uint32_t)(0x1UL << MXC_F_CTB_SCA_STAT_PVF1_POS)) /**< SCA_STAT_PVF1 Mask */ 646 647 #define MXC_F_CTB_SCA_STAT_PVF2_POS 3 /**< SCA_STAT_PVF2 Position */ 648 #define MXC_F_CTB_SCA_STAT_PVF2 ((uint32_t)(0x1UL << MXC_F_CTB_SCA_STAT_PVF2_POS)) /**< SCA_STAT_PVF2 Mask */ 649 650 #define MXC_F_CTB_SCA_STAT_FSMERR_POS 4 /**< SCA_STAT_FSMERR Position */ 651 #define MXC_F_CTB_SCA_STAT_FSMERR ((uint32_t)(0x1UL << MXC_F_CTB_SCA_STAT_FSMERR_POS)) /**< SCA_STAT_FSMERR Mask */ 652 653 #define MXC_F_CTB_SCA_STAT_COMPERR_POS 5 /**< SCA_STAT_COMPERR Position */ 654 #define MXC_F_CTB_SCA_STAT_COMPERR ((uint32_t)(0x1UL << MXC_F_CTB_SCA_STAT_COMPERR_POS)) /**< SCA_STAT_COMPERR Mask */ 655 656 #define MXC_F_CTB_SCA_STAT_MEMERR_POS 6 /**< SCA_STAT_MEMERR Position */ 657 #define MXC_F_CTB_SCA_STAT_MEMERR ((uint32_t)(0x1UL << MXC_F_CTB_SCA_STAT_MEMERR_POS)) /**< SCA_STAT_MEMERR Mask */ 658 659 #define MXC_F_CTB_SCA_STAT_CARRY_POS 8 /**< SCA_STAT_CARRY Position */ 660 #define MXC_F_CTB_SCA_STAT_CARRY ((uint32_t)(0x1UL << MXC_F_CTB_SCA_STAT_CARRY_POS)) /**< SCA_STAT_CARRY Mask */ 661 662 #define MXC_F_CTB_SCA_STAT_GTE2I2_POS 9 /**< SCA_STAT_GTE2I2 Position */ 663 #define MXC_F_CTB_SCA_STAT_GTE2I2 ((uint32_t)(0x1UL << MXC_F_CTB_SCA_STAT_GTE2I2_POS)) /**< SCA_STAT_GTE2I2 Mask */ 664 665 #define MXC_F_CTB_SCA_STAT_ALUNEG1_POS 10 /**< SCA_STAT_ALUNEG1 Position */ 666 #define MXC_F_CTB_SCA_STAT_ALUNEG1 ((uint32_t)(0x1UL << MXC_F_CTB_SCA_STAT_ALUNEG1_POS)) /**< SCA_STAT_ALUNEG1 Mask */ 667 668 #define MXC_F_CTB_SCA_STAT_ALUNEG2_POS 11 /**< SCA_STAT_ALUNEG2 Position */ 669 #define MXC_F_CTB_SCA_STAT_ALUNEG2 ((uint32_t)(0x1UL << MXC_F_CTB_SCA_STAT_ALUNEG2_POS)) /**< SCA_STAT_ALUNEG2 Mask */ 670 671 /**@} end of group CTB_SCA_STAT_Register */ 672 673 /** 674 * @ingroup ctb_registers 675 * @defgroup CTB_SCA_PPX_ADDR CTB_SCA_PPX_ADDR 676 * @brief PPX Coordinate Data Pointer Register. 677 * @{ 678 */ 679 #define MXC_F_CTB_SCA_PPX_ADDR_ADDR_POS 0 /**< SCA_PPX_ADDR_ADDR Position */ 680 #define MXC_F_CTB_SCA_PPX_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_SCA_PPX_ADDR_ADDR_POS)) /**< SCA_PPX_ADDR_ADDR Mask */ 681 682 /**@} end of group CTB_SCA_PPX_ADDR_Register */ 683 684 /** 685 * @ingroup ctb_registers 686 * @defgroup CTB_SCA_PPY_ADDR CTB_SCA_PPY_ADDR 687 * @brief PPY Coordinate Data Pointer Register. 688 * @{ 689 */ 690 #define MXC_F_CTB_SCA_PPY_ADDR_ADDR_POS 0 /**< SCA_PPY_ADDR_ADDR Position */ 691 #define MXC_F_CTB_SCA_PPY_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_SCA_PPY_ADDR_ADDR_POS)) /**< SCA_PPY_ADDR_ADDR Mask */ 692 693 /**@} end of group CTB_SCA_PPY_ADDR_Register */ 694 695 /** 696 * @ingroup ctb_registers 697 * @defgroup CTB_SCA_PPZ_ADDR CTB_SCA_PPZ_ADDR 698 * @brief PPZ Coordinate Data Pointer Register. 699 * @{ 700 */ 701 #define MXC_F_CTB_SCA_PPZ_ADDR_ADDR_POS 0 /**< SCA_PPZ_ADDR_ADDR Position */ 702 #define MXC_F_CTB_SCA_PPZ_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_SCA_PPZ_ADDR_ADDR_POS)) /**< SCA_PPZ_ADDR_ADDR Mask */ 703 704 /**@} end of group CTB_SCA_PPZ_ADDR_Register */ 705 706 /** 707 * @ingroup ctb_registers 708 * @defgroup CTB_SCA_PQX_ADDR CTB_SCA_PQX_ADDR 709 * @brief PQX Coordinate Data Pointer Register. 710 * @{ 711 */ 712 #define MXC_F_CTB_SCA_PQX_ADDR_ADDR_POS 0 /**< SCA_PQX_ADDR_ADDR Position */ 713 #define MXC_F_CTB_SCA_PQX_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_SCA_PQX_ADDR_ADDR_POS)) /**< SCA_PQX_ADDR_ADDR Mask */ 714 715 /**@} end of group CTB_SCA_PQX_ADDR_Register */ 716 717 /** 718 * @ingroup ctb_registers 719 * @defgroup CTB_SCA_PQY_ADDR CTB_SCA_PQY_ADDR 720 * @brief PQY Coordinate Data Pointer Register. 721 * @{ 722 */ 723 #define MXC_F_CTB_SCA_PQY_ADDR_ADDR_POS 0 /**< SCA_PQY_ADDR_ADDR Position */ 724 #define MXC_F_CTB_SCA_PQY_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_SCA_PQY_ADDR_ADDR_POS)) /**< SCA_PQY_ADDR_ADDR Mask */ 725 726 /**@} end of group CTB_SCA_PQY_ADDR_Register */ 727 728 /** 729 * @ingroup ctb_registers 730 * @defgroup CTB_SCA_PQZ_ADDR CTB_SCA_PQZ_ADDR 731 * @brief PQZ Coordinate Data Pointer Register. 732 * @{ 733 */ 734 #define MXC_F_CTB_SCA_PQZ_ADDR_ADDR_POS 0 /**< SCA_PQZ_ADDR_ADDR Position */ 735 #define MXC_F_CTB_SCA_PQZ_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_SCA_PQZ_ADDR_ADDR_POS)) /**< SCA_PQZ_ADDR_ADDR Mask */ 736 737 /**@} end of group CTB_SCA_PQZ_ADDR_Register */ 738 739 /** 740 * @ingroup ctb_registers 741 * @defgroup CTB_SCA_RDSA_ADDR CTB_SCA_RDSA_ADDR 742 * @brief SCA RDSA Address Register. 743 * @{ 744 */ 745 #define MXC_F_CTB_SCA_RDSA_ADDR_ADDR_POS 0 /**< SCA_RDSA_ADDR_ADDR Position */ 746 #define MXC_F_CTB_SCA_RDSA_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_SCA_RDSA_ADDR_ADDR_POS)) /**< SCA_RDSA_ADDR_ADDR Mask */ 747 748 /**@} end of group CTB_SCA_RDSA_ADDR_Register */ 749 750 /** 751 * @ingroup ctb_registers 752 * @defgroup CTB_SCA_RES_ADDR CTB_SCA_RES_ADDR 753 * @brief SCA Result Address Register. 754 * @{ 755 */ 756 #define MXC_F_CTB_SCA_RES_ADDR_ADDR_POS 0 /**< SCA_RES_ADDR_ADDR Position */ 757 #define MXC_F_CTB_SCA_RES_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_SCA_RES_ADDR_ADDR_POS)) /**< SCA_RES_ADDR_ADDR Mask */ 758 759 /**@} end of group CTB_SCA_RES_ADDR_Register */ 760 761 /** 762 * @ingroup ctb_registers 763 * @defgroup CTB_SCA_OP_BUFF_ADDR CTB_SCA_OP_BUFF_ADDR 764 * @brief SCA Operation Buffer Address Register. 765 * @{ 766 */ 767 #define MXC_F_CTB_SCA_OP_BUFF_ADDR_ADDR_POS 0 /**< SCA_OP_BUFF_ADDR_ADDR Position */ 768 #define MXC_F_CTB_SCA_OP_BUFF_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_SCA_OP_BUFF_ADDR_ADDR_POS)) /**< SCA_OP_BUFF_ADDR_ADDR Mask */ 769 770 /**@} end of group CTB_SCA_OP_BUFF_ADDR_Register */ 771 772 /** 773 * @ingroup ctb_registers 774 * @defgroup CTB_SCA_MODDATA CTB_SCA_MODDATA 775 * @brief SCA Modulo Data Input Register. 776 * @{ 777 */ 778 #define MXC_F_CTB_SCA_MODDATA_DATA_POS 0 /**< SCA_MODDATA_DATA Position */ 779 #define MXC_F_CTB_SCA_MODDATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_SCA_MODDATA_DATA_POS)) /**< SCA_MODDATA_DATA Mask */ 780 781 /**@} end of group CTB_SCA_MODDATA_Register */ 782 783 /** 784 * @ingroup ctb_registers 785 * @defgroup CTB_SCA_NRNG CTB_SCA_NRNG 786 * @brief SCA NIST RNG Address Register. 787 * @{ 788 */ 789 #define MXC_F_CTB_SCA_NRNG_ADDR_POS 0 /**< SCA_NRNG_ADDR Position */ 790 #define MXC_F_CTB_SCA_NRNG_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_SCA_NRNG_ADDR_POS)) /**< SCA_NRNG_ADDR Mask */ 791 792 /**@} end of group CTB_SCA_NRNG_Register */ 793 794 /** 795 * @ingroup ctb_registers 796 * @defgroup CTB_SCA_WASH CTB_SCA_WASH 797 * @brief SCA Wash Register. 798 * @{ 799 */ 800 #define MXC_F_CTB_SCA_WASH_ADDR_POS 0 /**< SCA_WASH_ADDR Position */ 801 #define MXC_F_CTB_SCA_WASH_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_SCA_WASH_ADDR_POS)) /**< SCA_WASH_ADDR Mask */ 802 803 /**@} end of group CTB_SCA_WASH_Register */ 804 805 #ifdef __cplusplus 806 } 807 #endif 808 809 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32572_INCLUDE_CTB_REGS_H_ 810
