1 /** 2 * @file tpu_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the TPU Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup tpu_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_TPU_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_TPU_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup tpu 67 * @defgroup tpu_registers TPU_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the TPU Peripheral Module. 69 * @details The Trust Protection Unit used to assist the computationally intensive operations of several common cryptographic algorithms. 70 */ 71 72 /** 73 * @ingroup tpu_registers 74 * Structure type to access the TPU Registers. 75 */ 76 typedef struct { 77 __IO uint32_t crypto_ctrl; /**< <tt>\b 0x00:</tt> TPU CRYPTO_CTRL Register */ 78 __IO uint32_t cipher_ctrl; /**< <tt>\b 0x04:</tt> TPU CIPHER_CTRL Register */ 79 __IO uint32_t hash_ctrl; /**< <tt>\b 0x08:</tt> TPU HASH_CTRL Register */ 80 __IO uint32_t crc_ctrl; /**< <tt>\b 0x0C:</tt> TPU CRC_CTRL Register */ 81 __IO uint32_t dma_src; /**< <tt>\b 0x10:</tt> TPU DMA_SRC Register */ 82 __IO uint32_t dma_dest; /**< <tt>\b 0x14:</tt> TPU DMA_DEST Register */ 83 __IO uint32_t dma_cnt; /**< <tt>\b 0x18:</tt> TPU DMA_CNT Register */ 84 __IO uint32_t maa_ctrl; /**< <tt>\b 0x1C:</tt> TPU MAA_CTRL Register */ 85 __O uint32_t crypto_din[4]; /**< <tt>\b 0x20:</tt> TPU CRYPTO_DIN Register */ 86 __I uint32_t crypto_dout[4]; /**< <tt>\b 0x30:</tt> TPU CRYPTO_DOUT Register */ 87 __IO uint32_t crc_poly; /**< <tt>\b 0x40:</tt> TPU CRC_POLY Register */ 88 __IO uint32_t crc_val; /**< <tt>\b 0x44:</tt> TPU CRC_VAL Register */ 89 __I uint32_t crc_prng; /**< <tt>\b 0x48:</tt> TPU CRC_PRNG Register */ 90 __IO uint32_t ham_ecc; /**< <tt>\b 0x4C:</tt> TPU HAM_ECC Register */ 91 __IO uint32_t cipher_init[4]; /**< <tt>\b 0x50:</tt> TPU CIPHER_INIT Register */ 92 __O uint32_t cipher_key[8]; /**< <tt>\b 0x60:</tt> TPU CIPHER_KEY Register */ 93 __IO uint32_t hash_digest[16]; /**< <tt>\b 0x80:</tt> TPU HASH_DIGEST Register */ 94 __IO uint32_t hash_msg_sz[4]; /**< <tt>\b 0xC0:</tt> TPU HASH_MSG_SZ Register */ 95 __IO uint32_t maa_maws; /**< <tt>\b 0xD0:</tt> TPU MAA_MAWS Register */ 96 } mxc_tpu_regs_t; 97 98 /* Register offsets for module TPU */ 99 /** 100 * @ingroup tpu_registers 101 * @defgroup TPU_Register_Offsets Register Offsets 102 * @brief TPU Peripheral Register Offsets from the TPU Base Peripheral Address. 103 * @{ 104 */ 105 #define MXC_R_TPU_CRYPTO_CTRL ((uint32_t)0x00000000UL) /**< Offset from TPU Base Address: <tt> 0x0000</tt> */ 106 #define MXC_R_TPU_CIPHER_CTRL ((uint32_t)0x00000004UL) /**< Offset from TPU Base Address: <tt> 0x0004</tt> */ 107 #define MXC_R_TPU_HASH_CTRL ((uint32_t)0x00000008UL) /**< Offset from TPU Base Address: <tt> 0x0008</tt> */ 108 #define MXC_R_TPU_CRC_CTRL ((uint32_t)0x0000000CUL) /**< Offset from TPU Base Address: <tt> 0x000C</tt> */ 109 #define MXC_R_TPU_DMA_SRC ((uint32_t)0x00000010UL) /**< Offset from TPU Base Address: <tt> 0x0010</tt> */ 110 #define MXC_R_TPU_DMA_DEST ((uint32_t)0x00000014UL) /**< Offset from TPU Base Address: <tt> 0x0014</tt> */ 111 #define MXC_R_TPU_DMA_CNT ((uint32_t)0x00000018UL) /**< Offset from TPU Base Address: <tt> 0x0018</tt> */ 112 #define MXC_R_TPU_MAA_CTRL ((uint32_t)0x0000001CUL) /**< Offset from TPU Base Address: <tt> 0x001C</tt> */ 113 #define MXC_R_TPU_CRYPTO_DIN ((uint32_t)0x00000020UL) /**< Offset from TPU Base Address: <tt> 0x0020</tt> */ 114 #define MXC_R_TPU_CRYPTO_DOUT ((uint32_t)0x00000030UL) /**< Offset from TPU Base Address: <tt> 0x0030</tt> */ 115 #define MXC_R_TPU_CRC_POLY ((uint32_t)0x00000040UL) /**< Offset from TPU Base Address: <tt> 0x0040</tt> */ 116 #define MXC_R_TPU_CRC_VAL ((uint32_t)0x00000044UL) /**< Offset from TPU Base Address: <tt> 0x0044</tt> */ 117 #define MXC_R_TPU_CRC_PRNG ((uint32_t)0x00000048UL) /**< Offset from TPU Base Address: <tt> 0x0048</tt> */ 118 #define MXC_R_TPU_HAM_ECC ((uint32_t)0x0000004CUL) /**< Offset from TPU Base Address: <tt> 0x004C</tt> */ 119 #define MXC_R_TPU_CIPHER_INIT ((uint32_t)0x00000050UL) /**< Offset from TPU Base Address: <tt> 0x0050</tt> */ 120 #define MXC_R_TPU_CIPHER_KEY ((uint32_t)0x00000060UL) /**< Offset from TPU Base Address: <tt> 0x0060</tt> */ 121 #define MXC_R_TPU_HASH_DIGEST ((uint32_t)0x00000080UL) /**< Offset from TPU Base Address: <tt> 0x0080</tt> */ 122 #define MXC_R_TPU_HASH_MSG_SZ ((uint32_t)0x000000C0UL) /**< Offset from TPU Base Address: <tt> 0x00C0</tt> */ 123 #define MXC_R_TPU_MAA_MAWS ((uint32_t)0x000000D0UL) /**< Offset from TPU Base Address: <tt> 0x00D0</tt> */ 124 /**@} end of group tpu_registers */ 125 126 /** 127 * @ingroup tpu_registers 128 * @defgroup TPU_CRYPTO_CTRL TPU_CRYPTO_CTRL 129 * @brief Crypto Control Register. 130 * @{ 131 */ 132 #define MXC_F_TPU_CRYPTO_CTRL_RST_POS 0 /**< CRYPTO_CTRL_RST Position */ 133 #define MXC_F_TPU_CRYPTO_CTRL_RST ((uint32_t)(0x1UL << MXC_F_TPU_CRYPTO_CTRL_RST_POS)) /**< CRYPTO_CTRL_RST Mask */ 134 #define MXC_V_TPU_CRYPTO_CTRL_RST_RESET ((uint32_t)0x1UL) /**< CRYPTO_CTRL_RST_RESET Value */ 135 #define MXC_S_TPU_CRYPTO_CTRL_RST_RESET (MXC_V_TPU_CRYPTO_CTRL_RST_RESET << MXC_F_TPU_CRYPTO_CTRL_RST_POS) /**< CRYPTO_CTRL_RST_RESET Setting */ 136 #define MXC_V_TPU_CRYPTO_CTRL_RST_RESET_DONE ((uint32_t)0x0UL) /**< CRYPTO_CTRL_RST_RESET_DONE Value */ 137 #define MXC_S_TPU_CRYPTO_CTRL_RST_RESET_DONE (MXC_V_TPU_CRYPTO_CTRL_RST_RESET_DONE << MXC_F_TPU_CRYPTO_CTRL_RST_POS) /**< CRYPTO_CTRL_RST_RESET_DONE Setting */ 138 #define MXC_V_TPU_CRYPTO_CTRL_RST_BUSY ((uint32_t)0x1UL) /**< CRYPTO_CTRL_RST_BUSY Value */ 139 #define MXC_S_TPU_CRYPTO_CTRL_RST_BUSY (MXC_V_TPU_CRYPTO_CTRL_RST_BUSY << MXC_F_TPU_CRYPTO_CTRL_RST_POS) /**< CRYPTO_CTRL_RST_BUSY Setting */ 140 141 #define MXC_F_TPU_CRYPTO_CTRL_INT_POS 1 /**< CRYPTO_CTRL_INT Position */ 142 #define MXC_F_TPU_CRYPTO_CTRL_INT ((uint32_t)(0x1UL << MXC_F_TPU_CRYPTO_CTRL_INT_POS)) /**< CRYPTO_CTRL_INT Mask */ 143 #define MXC_V_TPU_CRYPTO_CTRL_INT_DIS ((uint32_t)0x0UL) /**< CRYPTO_CTRL_INT_DIS Value */ 144 #define MXC_S_TPU_CRYPTO_CTRL_INT_DIS (MXC_V_TPU_CRYPTO_CTRL_INT_DIS << MXC_F_TPU_CRYPTO_CTRL_INT_POS) /**< CRYPTO_CTRL_INT_DIS Setting */ 145 #define MXC_V_TPU_CRYPTO_CTRL_INT_EN ((uint32_t)0x1UL) /**< CRYPTO_CTRL_INT_EN Value */ 146 #define MXC_S_TPU_CRYPTO_CTRL_INT_EN (MXC_V_TPU_CRYPTO_CTRL_INT_EN << MXC_F_TPU_CRYPTO_CTRL_INT_POS) /**< CRYPTO_CTRL_INT_EN Setting */ 147 148 #define MXC_F_TPU_CRYPTO_CTRL_SRC_POS 2 /**< CRYPTO_CTRL_SRC Position */ 149 #define MXC_F_TPU_CRYPTO_CTRL_SRC ((uint32_t)(0x1UL << MXC_F_TPU_CRYPTO_CTRL_SRC_POS)) /**< CRYPTO_CTRL_SRC Mask */ 150 #define MXC_V_TPU_CRYPTO_CTRL_SRC_INPUTFIFO ((uint32_t)0x0UL) /**< CRYPTO_CTRL_SRC_INPUTFIFO Value */ 151 #define MXC_S_TPU_CRYPTO_CTRL_SRC_INPUTFIFO (MXC_V_TPU_CRYPTO_CTRL_SRC_INPUTFIFO << MXC_F_TPU_CRYPTO_CTRL_SRC_POS) /**< CRYPTO_CTRL_SRC_INPUTFIFO Setting */ 152 #define MXC_V_TPU_CRYPTO_CTRL_SRC_OUTPUTFIFO ((uint32_t)0x1UL) /**< CRYPTO_CTRL_SRC_OUTPUTFIFO Value */ 153 #define MXC_S_TPU_CRYPTO_CTRL_SRC_OUTPUTFIFO (MXC_V_TPU_CRYPTO_CTRL_SRC_OUTPUTFIFO << MXC_F_TPU_CRYPTO_CTRL_SRC_POS) /**< CRYPTO_CTRL_SRC_OUTPUTFIFO Setting */ 154 155 #define MXC_F_TPU_CRYPTO_CTRL_BSO_POS 4 /**< CRYPTO_CTRL_BSO Position */ 156 #define MXC_F_TPU_CRYPTO_CTRL_BSO ((uint32_t)(0x1UL << MXC_F_TPU_CRYPTO_CTRL_BSO_POS)) /**< CRYPTO_CTRL_BSO Mask */ 157 #define MXC_V_TPU_CRYPTO_CTRL_BSO_DIS ((uint32_t)0x0UL) /**< CRYPTO_CTRL_BSO_DIS Value */ 158 #define MXC_S_TPU_CRYPTO_CTRL_BSO_DIS (MXC_V_TPU_CRYPTO_CTRL_BSO_DIS << MXC_F_TPU_CRYPTO_CTRL_BSO_POS) /**< CRYPTO_CTRL_BSO_DIS Setting */ 159 #define MXC_V_TPU_CRYPTO_CTRL_BSO_EN ((uint32_t)0x1UL) /**< CRYPTO_CTRL_BSO_EN Value */ 160 #define MXC_S_TPU_CRYPTO_CTRL_BSO_EN (MXC_V_TPU_CRYPTO_CTRL_BSO_EN << MXC_F_TPU_CRYPTO_CTRL_BSO_POS) /**< CRYPTO_CTRL_BSO_EN Setting */ 161 162 #define MXC_F_TPU_CRYPTO_CTRL_BSI_POS 5 /**< CRYPTO_CTRL_BSI Position */ 163 #define MXC_F_TPU_CRYPTO_CTRL_BSI ((uint32_t)(0x1UL << MXC_F_TPU_CRYPTO_CTRL_BSI_POS)) /**< CRYPTO_CTRL_BSI Mask */ 164 #define MXC_V_TPU_CRYPTO_CTRL_BSI_DIS ((uint32_t)0x0UL) /**< CRYPTO_CTRL_BSI_DIS Value */ 165 #define MXC_S_TPU_CRYPTO_CTRL_BSI_DIS (MXC_V_TPU_CRYPTO_CTRL_BSI_DIS << MXC_F_TPU_CRYPTO_CTRL_BSI_POS) /**< CRYPTO_CTRL_BSI_DIS Setting */ 166 #define MXC_V_TPU_CRYPTO_CTRL_BSI_EN ((uint32_t)0x1UL) /**< CRYPTO_CTRL_BSI_EN Value */ 167 #define MXC_S_TPU_CRYPTO_CTRL_BSI_EN (MXC_V_TPU_CRYPTO_CTRL_BSI_EN << MXC_F_TPU_CRYPTO_CTRL_BSI_POS) /**< CRYPTO_CTRL_BSI_EN Setting */ 168 169 #define MXC_F_TPU_CRYPTO_CTRL_WAIT_EN_POS 6 /**< CRYPTO_CTRL_WAIT_EN Position */ 170 #define MXC_F_TPU_CRYPTO_CTRL_WAIT_EN ((uint32_t)(0x1UL << MXC_F_TPU_CRYPTO_CTRL_WAIT_EN_POS)) /**< CRYPTO_CTRL_WAIT_EN Mask */ 171 #define MXC_V_TPU_CRYPTO_CTRL_WAIT_EN_DIS ((uint32_t)0x0UL) /**< CRYPTO_CTRL_WAIT_EN_DIS Value */ 172 #define MXC_S_TPU_CRYPTO_CTRL_WAIT_EN_DIS (MXC_V_TPU_CRYPTO_CTRL_WAIT_EN_DIS << MXC_F_TPU_CRYPTO_CTRL_WAIT_EN_POS) /**< CRYPTO_CTRL_WAIT_EN_DIS Setting */ 173 #define MXC_V_TPU_CRYPTO_CTRL_WAIT_EN_EN ((uint32_t)0x1UL) /**< CRYPTO_CTRL_WAIT_EN_EN Value */ 174 #define MXC_S_TPU_CRYPTO_CTRL_WAIT_EN_EN (MXC_V_TPU_CRYPTO_CTRL_WAIT_EN_EN << MXC_F_TPU_CRYPTO_CTRL_WAIT_EN_POS) /**< CRYPTO_CTRL_WAIT_EN_EN Setting */ 175 176 #define MXC_F_TPU_CRYPTO_CTRL_WAIT_POL_POS 7 /**< CRYPTO_CTRL_WAIT_POL Position */ 177 #define MXC_F_TPU_CRYPTO_CTRL_WAIT_POL ((uint32_t)(0x1UL << MXC_F_TPU_CRYPTO_CTRL_WAIT_POL_POS)) /**< CRYPTO_CTRL_WAIT_POL Mask */ 178 #define MXC_V_TPU_CRYPTO_CTRL_WAIT_POL_ACTIVELO ((uint32_t)0x0UL) /**< CRYPTO_CTRL_WAIT_POL_ACTIVELO Value */ 179 #define MXC_S_TPU_CRYPTO_CTRL_WAIT_POL_ACTIVELO (MXC_V_TPU_CRYPTO_CTRL_WAIT_POL_ACTIVELO << MXC_F_TPU_CRYPTO_CTRL_WAIT_POL_POS) /**< CRYPTO_CTRL_WAIT_POL_ACTIVELO Setting */ 180 #define MXC_V_TPU_CRYPTO_CTRL_WAIT_POL_ACTIVEHI ((uint32_t)0x1UL) /**< CRYPTO_CTRL_WAIT_POL_ACTIVEHI Value */ 181 #define MXC_S_TPU_CRYPTO_CTRL_WAIT_POL_ACTIVEHI (MXC_V_TPU_CRYPTO_CTRL_WAIT_POL_ACTIVEHI << MXC_F_TPU_CRYPTO_CTRL_WAIT_POL_POS) /**< CRYPTO_CTRL_WAIT_POL_ACTIVEHI Setting */ 182 183 #define MXC_F_TPU_CRYPTO_CTRL_WRSRC_POS 8 /**< CRYPTO_CTRL_WRSRC Position */ 184 #define MXC_F_TPU_CRYPTO_CTRL_WRSRC ((uint32_t)(0x3UL << MXC_F_TPU_CRYPTO_CTRL_WRSRC_POS)) /**< CRYPTO_CTRL_WRSRC Mask */ 185 #define MXC_V_TPU_CRYPTO_CTRL_WRSRC_NONE ((uint32_t)0x0UL) /**< CRYPTO_CTRL_WRSRC_NONE Value */ 186 #define MXC_S_TPU_CRYPTO_CTRL_WRSRC_NONE (MXC_V_TPU_CRYPTO_CTRL_WRSRC_NONE << MXC_F_TPU_CRYPTO_CTRL_WRSRC_POS) /**< CRYPTO_CTRL_WRSRC_NONE Setting */ 187 #define MXC_V_TPU_CRYPTO_CTRL_WRSRC_CIPHEROUTPUT ((uint32_t)0x1UL) /**< CRYPTO_CTRL_WRSRC_CIPHEROUTPUT Value */ 188 #define MXC_S_TPU_CRYPTO_CTRL_WRSRC_CIPHEROUTPUT (MXC_V_TPU_CRYPTO_CTRL_WRSRC_CIPHEROUTPUT << MXC_F_TPU_CRYPTO_CTRL_WRSRC_POS) /**< CRYPTO_CTRL_WRSRC_CIPHEROUTPUT Setting */ 189 #define MXC_V_TPU_CRYPTO_CTRL_WRSRC_READFIFO ((uint32_t)0x2UL) /**< CRYPTO_CTRL_WRSRC_READFIFO Value */ 190 #define MXC_S_TPU_CRYPTO_CTRL_WRSRC_READFIFO (MXC_V_TPU_CRYPTO_CTRL_WRSRC_READFIFO << MXC_F_TPU_CRYPTO_CTRL_WRSRC_POS) /**< CRYPTO_CTRL_WRSRC_READFIFO Setting */ 191 192 #define MXC_F_TPU_CRYPTO_CTRL_RDSRC_POS 10 /**< CRYPTO_CTRL_RDSRC Position */ 193 #define MXC_F_TPU_CRYPTO_CTRL_RDSRC ((uint32_t)(0x3UL << MXC_F_TPU_CRYPTO_CTRL_RDSRC_POS)) /**< CRYPTO_CTRL_RDSRC Mask */ 194 #define MXC_V_TPU_CRYPTO_CTRL_RDSRC_DMADISABLED ((uint32_t)0x0UL) /**< CRYPTO_CTRL_RDSRC_DMADISABLED Value */ 195 #define MXC_S_TPU_CRYPTO_CTRL_RDSRC_DMADISABLED (MXC_V_TPU_CRYPTO_CTRL_RDSRC_DMADISABLED << MXC_F_TPU_CRYPTO_CTRL_RDSRC_POS) /**< CRYPTO_CTRL_RDSRC_DMADISABLED Setting */ 196 #define MXC_V_TPU_CRYPTO_CTRL_RDSRC_DMAORAPB ((uint32_t)0x1UL) /**< CRYPTO_CTRL_RDSRC_DMAORAPB Value */ 197 #define MXC_S_TPU_CRYPTO_CTRL_RDSRC_DMAORAPB (MXC_V_TPU_CRYPTO_CTRL_RDSRC_DMAORAPB << MXC_F_TPU_CRYPTO_CTRL_RDSRC_POS) /**< CRYPTO_CTRL_RDSRC_DMAORAPB Setting */ 198 #define MXC_V_TPU_CRYPTO_CTRL_RDSRC_RNG ((uint32_t)0x2UL) /**< CRYPTO_CTRL_RDSRC_RNG Value */ 199 #define MXC_S_TPU_CRYPTO_CTRL_RDSRC_RNG (MXC_V_TPU_CRYPTO_CTRL_RDSRC_RNG << MXC_F_TPU_CRYPTO_CTRL_RDSRC_POS) /**< CRYPTO_CTRL_RDSRC_RNG Setting */ 200 201 #define MXC_F_TPU_CRYPTO_CTRL_FLAG_MODE_POS 14 /**< CRYPTO_CTRL_FLAG_MODE Position */ 202 #define MXC_F_TPU_CRYPTO_CTRL_FLAG_MODE ((uint32_t)(0x1UL << MXC_F_TPU_CRYPTO_CTRL_FLAG_MODE_POS)) /**< CRYPTO_CTRL_FLAG_MODE Mask */ 203 #define MXC_V_TPU_CRYPTO_CTRL_FLAG_MODE_UNRES_WR ((uint32_t)0x0UL) /**< CRYPTO_CTRL_FLAG_MODE_UNRES_WR Value */ 204 #define MXC_S_TPU_CRYPTO_CTRL_FLAG_MODE_UNRES_WR (MXC_V_TPU_CRYPTO_CTRL_FLAG_MODE_UNRES_WR << MXC_F_TPU_CRYPTO_CTRL_FLAG_MODE_POS) /**< CRYPTO_CTRL_FLAG_MODE_UNRES_WR Setting */ 205 #define MXC_V_TPU_CRYPTO_CTRL_FLAG_MODE_RES_WR ((uint32_t)0x1UL) /**< CRYPTO_CTRL_FLAG_MODE_RES_WR Value */ 206 #define MXC_S_TPU_CRYPTO_CTRL_FLAG_MODE_RES_WR (MXC_V_TPU_CRYPTO_CTRL_FLAG_MODE_RES_WR << MXC_F_TPU_CRYPTO_CTRL_FLAG_MODE_POS) /**< CRYPTO_CTRL_FLAG_MODE_RES_WR Setting */ 207 208 #define MXC_F_TPU_CRYPTO_CTRL_DMADNEMSK_POS 15 /**< CRYPTO_CTRL_DMADNEMSK Position */ 209 #define MXC_F_TPU_CRYPTO_CTRL_DMADNEMSK ((uint32_t)(0x1UL << MXC_F_TPU_CRYPTO_CTRL_DMADNEMSK_POS)) /**< CRYPTO_CTRL_DMADNEMSK Mask */ 210 #define MXC_V_TPU_CRYPTO_CTRL_DMADNEMSK_NOT_USED ((uint32_t)0x0UL) /**< CRYPTO_CTRL_DMADNEMSK_NOT_USED Value */ 211 #define MXC_S_TPU_CRYPTO_CTRL_DMADNEMSK_NOT_USED (MXC_V_TPU_CRYPTO_CTRL_DMADNEMSK_NOT_USED << MXC_F_TPU_CRYPTO_CTRL_DMADNEMSK_POS) /**< CRYPTO_CTRL_DMADNEMSK_NOT_USED Setting */ 212 #define MXC_V_TPU_CRYPTO_CTRL_DMADNEMSK_USED ((uint32_t)0x1UL) /**< CRYPTO_CTRL_DMADNEMSK_USED Value */ 213 #define MXC_S_TPU_CRYPTO_CTRL_DMADNEMSK_USED (MXC_V_TPU_CRYPTO_CTRL_DMADNEMSK_USED << MXC_F_TPU_CRYPTO_CTRL_DMADNEMSK_POS) /**< CRYPTO_CTRL_DMADNEMSK_USED Setting */ 214 215 #define MXC_F_TPU_CRYPTO_CTRL_DMA_DONE_POS 24 /**< CRYPTO_CTRL_DMA_DONE Position */ 216 #define MXC_F_TPU_CRYPTO_CTRL_DMA_DONE ((uint32_t)(0x1UL << MXC_F_TPU_CRYPTO_CTRL_DMA_DONE_POS)) /**< CRYPTO_CTRL_DMA_DONE Mask */ 217 #define MXC_V_TPU_CRYPTO_CTRL_DMA_DONE_NOTDONE ((uint32_t)0x0UL) /**< CRYPTO_CTRL_DMA_DONE_NOTDONE Value */ 218 #define MXC_S_TPU_CRYPTO_CTRL_DMA_DONE_NOTDONE (MXC_V_TPU_CRYPTO_CTRL_DMA_DONE_NOTDONE << MXC_F_TPU_CRYPTO_CTRL_DMA_DONE_POS) /**< CRYPTO_CTRL_DMA_DONE_NOTDONE Setting */ 219 #define MXC_V_TPU_CRYPTO_CTRL_DMA_DONE_DONE ((uint32_t)0x1UL) /**< CRYPTO_CTRL_DMA_DONE_DONE Value */ 220 #define MXC_S_TPU_CRYPTO_CTRL_DMA_DONE_DONE (MXC_V_TPU_CRYPTO_CTRL_DMA_DONE_DONE << MXC_F_TPU_CRYPTO_CTRL_DMA_DONE_POS) /**< CRYPTO_CTRL_DMA_DONE_DONE Setting */ 221 222 #define MXC_F_TPU_CRYPTO_CTRL_GLS_DONE_POS 25 /**< CRYPTO_CTRL_GLS_DONE Position */ 223 #define MXC_F_TPU_CRYPTO_CTRL_GLS_DONE ((uint32_t)(0x1UL << MXC_F_TPU_CRYPTO_CTRL_GLS_DONE_POS)) /**< CRYPTO_CTRL_GLS_DONE Mask */ 224 #define MXC_V_TPU_CRYPTO_CTRL_GLS_DONE_NOTDONE ((uint32_t)0x0UL) /**< CRYPTO_CTRL_GLS_DONE_NOTDONE Value */ 225 #define MXC_S_TPU_CRYPTO_CTRL_GLS_DONE_NOTDONE (MXC_V_TPU_CRYPTO_CTRL_GLS_DONE_NOTDONE << MXC_F_TPU_CRYPTO_CTRL_GLS_DONE_POS) /**< CRYPTO_CTRL_GLS_DONE_NOTDONE Setting */ 226 #define MXC_V_TPU_CRYPTO_CTRL_GLS_DONE_DONE ((uint32_t)0x1UL) /**< CRYPTO_CTRL_GLS_DONE_DONE Value */ 227 #define MXC_S_TPU_CRYPTO_CTRL_GLS_DONE_DONE (MXC_V_TPU_CRYPTO_CTRL_GLS_DONE_DONE << MXC_F_TPU_CRYPTO_CTRL_GLS_DONE_POS) /**< CRYPTO_CTRL_GLS_DONE_DONE Setting */ 228 229 #define MXC_F_TPU_CRYPTO_CTRL_HSH_DONE_POS 26 /**< CRYPTO_CTRL_HSH_DONE Position */ 230 #define MXC_F_TPU_CRYPTO_CTRL_HSH_DONE ((uint32_t)(0x1UL << MXC_F_TPU_CRYPTO_CTRL_HSH_DONE_POS)) /**< CRYPTO_CTRL_HSH_DONE Mask */ 231 #define MXC_V_TPU_CRYPTO_CTRL_HSH_DONE_NOTDONE ((uint32_t)0x0UL) /**< CRYPTO_CTRL_HSH_DONE_NOTDONE Value */ 232 #define MXC_S_TPU_CRYPTO_CTRL_HSH_DONE_NOTDONE (MXC_V_TPU_CRYPTO_CTRL_HSH_DONE_NOTDONE << MXC_F_TPU_CRYPTO_CTRL_HSH_DONE_POS) /**< CRYPTO_CTRL_HSH_DONE_NOTDONE Setting */ 233 #define MXC_V_TPU_CRYPTO_CTRL_HSH_DONE_DONE ((uint32_t)0x1UL) /**< CRYPTO_CTRL_HSH_DONE_DONE Value */ 234 #define MXC_S_TPU_CRYPTO_CTRL_HSH_DONE_DONE (MXC_V_TPU_CRYPTO_CTRL_HSH_DONE_DONE << MXC_F_TPU_CRYPTO_CTRL_HSH_DONE_POS) /**< CRYPTO_CTRL_HSH_DONE_DONE Setting */ 235 236 #define MXC_F_TPU_CRYPTO_CTRL_CPH_DONE_POS 27 /**< CRYPTO_CTRL_CPH_DONE Position */ 237 #define MXC_F_TPU_CRYPTO_CTRL_CPH_DONE ((uint32_t)(0x1UL << MXC_F_TPU_CRYPTO_CTRL_CPH_DONE_POS)) /**< CRYPTO_CTRL_CPH_DONE Mask */ 238 #define MXC_V_TPU_CRYPTO_CTRL_CPH_DONE_NOTDONE ((uint32_t)0x0UL) /**< CRYPTO_CTRL_CPH_DONE_NOTDONE Value */ 239 #define MXC_S_TPU_CRYPTO_CTRL_CPH_DONE_NOTDONE (MXC_V_TPU_CRYPTO_CTRL_CPH_DONE_NOTDONE << MXC_F_TPU_CRYPTO_CTRL_CPH_DONE_POS) /**< CRYPTO_CTRL_CPH_DONE_NOTDONE Setting */ 240 #define MXC_V_TPU_CRYPTO_CTRL_CPH_DONE_DONE ((uint32_t)0x1UL) /**< CRYPTO_CTRL_CPH_DONE_DONE Value */ 241 #define MXC_S_TPU_CRYPTO_CTRL_CPH_DONE_DONE (MXC_V_TPU_CRYPTO_CTRL_CPH_DONE_DONE << MXC_F_TPU_CRYPTO_CTRL_CPH_DONE_POS) /**< CRYPTO_CTRL_CPH_DONE_DONE Setting */ 242 243 #define MXC_F_TPU_CRYPTO_CTRL_MAA_DONE_POS 28 /**< CRYPTO_CTRL_MAA_DONE Position */ 244 #define MXC_F_TPU_CRYPTO_CTRL_MAA_DONE ((uint32_t)(0x1UL << MXC_F_TPU_CRYPTO_CTRL_MAA_DONE_POS)) /**< CRYPTO_CTRL_MAA_DONE Mask */ 245 #define MXC_V_TPU_CRYPTO_CTRL_MAA_DONE_NOTDONE ((uint32_t)0x0UL) /**< CRYPTO_CTRL_MAA_DONE_NOTDONE Value */ 246 #define MXC_S_TPU_CRYPTO_CTRL_MAA_DONE_NOTDONE (MXC_V_TPU_CRYPTO_CTRL_MAA_DONE_NOTDONE << MXC_F_TPU_CRYPTO_CTRL_MAA_DONE_POS) /**< CRYPTO_CTRL_MAA_DONE_NOTDONE Setting */ 247 #define MXC_V_TPU_CRYPTO_CTRL_MAA_DONE_DONE ((uint32_t)0x1UL) /**< CRYPTO_CTRL_MAA_DONE_DONE Value */ 248 #define MXC_S_TPU_CRYPTO_CTRL_MAA_DONE_DONE (MXC_V_TPU_CRYPTO_CTRL_MAA_DONE_DONE << MXC_F_TPU_CRYPTO_CTRL_MAA_DONE_POS) /**< CRYPTO_CTRL_MAA_DONE_DONE Setting */ 249 250 #define MXC_F_TPU_CRYPTO_CTRL_ERR_POS 29 /**< CRYPTO_CTRL_ERR Position */ 251 #define MXC_F_TPU_CRYPTO_CTRL_ERR ((uint32_t)(0x1UL << MXC_F_TPU_CRYPTO_CTRL_ERR_POS)) /**< CRYPTO_CTRL_ERR Mask */ 252 #define MXC_V_TPU_CRYPTO_CTRL_ERR_NOERROR ((uint32_t)0x0UL) /**< CRYPTO_CTRL_ERR_NOERROR Value */ 253 #define MXC_S_TPU_CRYPTO_CTRL_ERR_NOERROR (MXC_V_TPU_CRYPTO_CTRL_ERR_NOERROR << MXC_F_TPU_CRYPTO_CTRL_ERR_POS) /**< CRYPTO_CTRL_ERR_NOERROR Setting */ 254 #define MXC_V_TPU_CRYPTO_CTRL_ERR_ERROR ((uint32_t)0x1UL) /**< CRYPTO_CTRL_ERR_ERROR Value */ 255 #define MXC_S_TPU_CRYPTO_CTRL_ERR_ERROR (MXC_V_TPU_CRYPTO_CTRL_ERR_ERROR << MXC_F_TPU_CRYPTO_CTRL_ERR_POS) /**< CRYPTO_CTRL_ERR_ERROR Setting */ 256 257 #define MXC_F_TPU_CRYPTO_CTRL_RDY_POS 30 /**< CRYPTO_CTRL_RDY Position */ 258 #define MXC_F_TPU_CRYPTO_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_TPU_CRYPTO_CTRL_RDY_POS)) /**< CRYPTO_CTRL_RDY Mask */ 259 #define MXC_V_TPU_CRYPTO_CTRL_RDY_BUSY ((uint32_t)0x0UL) /**< CRYPTO_CTRL_RDY_BUSY Value */ 260 #define MXC_S_TPU_CRYPTO_CTRL_RDY_BUSY (MXC_V_TPU_CRYPTO_CTRL_RDY_BUSY << MXC_F_TPU_CRYPTO_CTRL_RDY_POS) /**< CRYPTO_CTRL_RDY_BUSY Setting */ 261 #define MXC_V_TPU_CRYPTO_CTRL_RDY_READY ((uint32_t)0x1UL) /**< CRYPTO_CTRL_RDY_READY Value */ 262 #define MXC_S_TPU_CRYPTO_CTRL_RDY_READY (MXC_V_TPU_CRYPTO_CTRL_RDY_READY << MXC_F_TPU_CRYPTO_CTRL_RDY_POS) /**< CRYPTO_CTRL_RDY_READY Setting */ 263 264 #define MXC_F_TPU_CRYPTO_CTRL_DONE_POS 31 /**< CRYPTO_CTRL_DONE Position */ 265 #define MXC_F_TPU_CRYPTO_CTRL_DONE ((uint32_t)(0x1UL << MXC_F_TPU_CRYPTO_CTRL_DONE_POS)) /**< CRYPTO_CTRL_DONE Mask */ 266 #define MXC_V_TPU_CRYPTO_CTRL_DONE_NOTDONE ((uint32_t)0x0UL) /**< CRYPTO_CTRL_DONE_NOTDONE Value */ 267 #define MXC_S_TPU_CRYPTO_CTRL_DONE_NOTDONE (MXC_V_TPU_CRYPTO_CTRL_DONE_NOTDONE << MXC_F_TPU_CRYPTO_CTRL_DONE_POS) /**< CRYPTO_CTRL_DONE_NOTDONE Setting */ 268 #define MXC_V_TPU_CRYPTO_CTRL_DONE_DONE ((uint32_t)0x1UL) /**< CRYPTO_CTRL_DONE_DONE Value */ 269 #define MXC_S_TPU_CRYPTO_CTRL_DONE_DONE (MXC_V_TPU_CRYPTO_CTRL_DONE_DONE << MXC_F_TPU_CRYPTO_CTRL_DONE_POS) /**< CRYPTO_CTRL_DONE_DONE Setting */ 270 271 /**@} end of group TPU_CRYPTO_CTRL_Register */ 272 273 /** 274 * @ingroup tpu_registers 275 * @defgroup TPU_CIPHER_CTRL TPU_CIPHER_CTRL 276 * @brief Cipher Control Register. 277 * @{ 278 */ 279 #define MXC_F_TPU_CIPHER_CTRL_ENC_POS 0 /**< CIPHER_CTRL_ENC Position */ 280 #define MXC_F_TPU_CIPHER_CTRL_ENC ((uint32_t)(0x1UL << MXC_F_TPU_CIPHER_CTRL_ENC_POS)) /**< CIPHER_CTRL_ENC Mask */ 281 #define MXC_V_TPU_CIPHER_CTRL_ENC_ENCRYPT ((uint32_t)0x0UL) /**< CIPHER_CTRL_ENC_ENCRYPT Value */ 282 #define MXC_S_TPU_CIPHER_CTRL_ENC_ENCRYPT (MXC_V_TPU_CIPHER_CTRL_ENC_ENCRYPT << MXC_F_TPU_CIPHER_CTRL_ENC_POS) /**< CIPHER_CTRL_ENC_ENCRYPT Setting */ 283 #define MXC_V_TPU_CIPHER_CTRL_ENC_DECRYPT ((uint32_t)0x1UL) /**< CIPHER_CTRL_ENC_DECRYPT Value */ 284 #define MXC_S_TPU_CIPHER_CTRL_ENC_DECRYPT (MXC_V_TPU_CIPHER_CTRL_ENC_DECRYPT << MXC_F_TPU_CIPHER_CTRL_ENC_POS) /**< CIPHER_CTRL_ENC_DECRYPT Setting */ 285 286 #define MXC_F_TPU_CIPHER_CTRL_KEY_POS 1 /**< CIPHER_CTRL_KEY Position */ 287 #define MXC_F_TPU_CIPHER_CTRL_KEY ((uint32_t)(0x1UL << MXC_F_TPU_CIPHER_CTRL_KEY_POS)) /**< CIPHER_CTRL_KEY Mask */ 288 #define MXC_V_TPU_CIPHER_CTRL_KEY_COMPLETE ((uint32_t)0x0UL) /**< CIPHER_CTRL_KEY_COMPLETE Value */ 289 #define MXC_S_TPU_CIPHER_CTRL_KEY_COMPLETE (MXC_V_TPU_CIPHER_CTRL_KEY_COMPLETE << MXC_F_TPU_CIPHER_CTRL_KEY_POS) /**< CIPHER_CTRL_KEY_COMPLETE Setting */ 290 #define MXC_V_TPU_CIPHER_CTRL_KEY_START ((uint32_t)0x1UL) /**< CIPHER_CTRL_KEY_START Value */ 291 #define MXC_S_TPU_CIPHER_CTRL_KEY_START (MXC_V_TPU_CIPHER_CTRL_KEY_START << MXC_F_TPU_CIPHER_CTRL_KEY_POS) /**< CIPHER_CTRL_KEY_START Setting */ 292 293 #define MXC_F_TPU_CIPHER_CTRL_SRC_POS 2 /**< CIPHER_CTRL_SRC Position */ 294 #define MXC_F_TPU_CIPHER_CTRL_SRC ((uint32_t)(0x3UL << MXC_F_TPU_CIPHER_CTRL_SRC_POS)) /**< CIPHER_CTRL_SRC Mask */ 295 #define MXC_V_TPU_CIPHER_CTRL_SRC_CIPHERKEY ((uint32_t)0x0UL) /**< CIPHER_CTRL_SRC_CIPHERKEY Value */ 296 #define MXC_S_TPU_CIPHER_CTRL_SRC_CIPHERKEY (MXC_V_TPU_CIPHER_CTRL_SRC_CIPHERKEY << MXC_F_TPU_CIPHER_CTRL_SRC_POS) /**< CIPHER_CTRL_SRC_CIPHERKEY Setting */ 297 #define MXC_V_TPU_CIPHER_CTRL_SRC_REGFILE ((uint32_t)0x2UL) /**< CIPHER_CTRL_SRC_REGFILE Value */ 298 #define MXC_S_TPU_CIPHER_CTRL_SRC_REGFILE (MXC_V_TPU_CIPHER_CTRL_SRC_REGFILE << MXC_F_TPU_CIPHER_CTRL_SRC_POS) /**< CIPHER_CTRL_SRC_REGFILE Setting */ 299 #define MXC_V_TPU_CIPHER_CTRL_SRC_QSPIKEY_REGFILE ((uint32_t)0x3UL) /**< CIPHER_CTRL_SRC_QSPIKEY_REGFILE Value */ 300 #define MXC_S_TPU_CIPHER_CTRL_SRC_QSPIKEY_REGFILE (MXC_V_TPU_CIPHER_CTRL_SRC_QSPIKEY_REGFILE << MXC_F_TPU_CIPHER_CTRL_SRC_POS) /**< CIPHER_CTRL_SRC_QSPIKEY_REGFILE Setting */ 301 302 #define MXC_F_TPU_CIPHER_CTRL_CIPHER_POS 4 /**< CIPHER_CTRL_CIPHER Position */ 303 #define MXC_F_TPU_CIPHER_CTRL_CIPHER ((uint32_t)(0x7UL << MXC_F_TPU_CIPHER_CTRL_CIPHER_POS)) /**< CIPHER_CTRL_CIPHER Mask */ 304 #define MXC_V_TPU_CIPHER_CTRL_CIPHER_DIS ((uint32_t)0x0UL) /**< CIPHER_CTRL_CIPHER_DIS Value */ 305 #define MXC_S_TPU_CIPHER_CTRL_CIPHER_DIS (MXC_V_TPU_CIPHER_CTRL_CIPHER_DIS << MXC_F_TPU_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_DIS Setting */ 306 #define MXC_V_TPU_CIPHER_CTRL_CIPHER_AES128 ((uint32_t)0x1UL) /**< CIPHER_CTRL_CIPHER_AES128 Value */ 307 #define MXC_S_TPU_CIPHER_CTRL_CIPHER_AES128 (MXC_V_TPU_CIPHER_CTRL_CIPHER_AES128 << MXC_F_TPU_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_AES128 Setting */ 308 #define MXC_V_TPU_CIPHER_CTRL_CIPHER_AES192 ((uint32_t)0x2UL) /**< CIPHER_CTRL_CIPHER_AES192 Value */ 309 #define MXC_S_TPU_CIPHER_CTRL_CIPHER_AES192 (MXC_V_TPU_CIPHER_CTRL_CIPHER_AES192 << MXC_F_TPU_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_AES192 Setting */ 310 #define MXC_V_TPU_CIPHER_CTRL_CIPHER_AES256 ((uint32_t)0x3UL) /**< CIPHER_CTRL_CIPHER_AES256 Value */ 311 #define MXC_S_TPU_CIPHER_CTRL_CIPHER_AES256 (MXC_V_TPU_CIPHER_CTRL_CIPHER_AES256 << MXC_F_TPU_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_AES256 Setting */ 312 #define MXC_V_TPU_CIPHER_CTRL_CIPHER_DES ((uint32_t)0x4UL) /**< CIPHER_CTRL_CIPHER_DES Value */ 313 #define MXC_S_TPU_CIPHER_CTRL_CIPHER_DES (MXC_V_TPU_CIPHER_CTRL_CIPHER_DES << MXC_F_TPU_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_DES Setting */ 314 #define MXC_V_TPU_CIPHER_CTRL_CIPHER_TDEA ((uint32_t)0x5UL) /**< CIPHER_CTRL_CIPHER_TDEA Value */ 315 #define MXC_S_TPU_CIPHER_CTRL_CIPHER_TDEA (MXC_V_TPU_CIPHER_CTRL_CIPHER_TDEA << MXC_F_TPU_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_TDEA Setting */ 316 317 #define MXC_F_TPU_CIPHER_CTRL_MODE_POS 8 /**< CIPHER_CTRL_MODE Position */ 318 #define MXC_F_TPU_CIPHER_CTRL_MODE ((uint32_t)(0x7UL << MXC_F_TPU_CIPHER_CTRL_MODE_POS)) /**< CIPHER_CTRL_MODE Mask */ 319 #define MXC_V_TPU_CIPHER_CTRL_MODE_ECB ((uint32_t)0x0UL) /**< CIPHER_CTRL_MODE_ECB Value */ 320 #define MXC_S_TPU_CIPHER_CTRL_MODE_ECB (MXC_V_TPU_CIPHER_CTRL_MODE_ECB << MXC_F_TPU_CIPHER_CTRL_MODE_POS) /**< CIPHER_CTRL_MODE_ECB Setting */ 321 #define MXC_V_TPU_CIPHER_CTRL_MODE_CBC ((uint32_t)0x1UL) /**< CIPHER_CTRL_MODE_CBC Value */ 322 #define MXC_S_TPU_CIPHER_CTRL_MODE_CBC (MXC_V_TPU_CIPHER_CTRL_MODE_CBC << MXC_F_TPU_CIPHER_CTRL_MODE_POS) /**< CIPHER_CTRL_MODE_CBC Setting */ 323 #define MXC_V_TPU_CIPHER_CTRL_MODE_CFB ((uint32_t)0x2UL) /**< CIPHER_CTRL_MODE_CFB Value */ 324 #define MXC_S_TPU_CIPHER_CTRL_MODE_CFB (MXC_V_TPU_CIPHER_CTRL_MODE_CFB << MXC_F_TPU_CIPHER_CTRL_MODE_POS) /**< CIPHER_CTRL_MODE_CFB Setting */ 325 #define MXC_V_TPU_CIPHER_CTRL_MODE_OFB ((uint32_t)0x3UL) /**< CIPHER_CTRL_MODE_OFB Value */ 326 #define MXC_S_TPU_CIPHER_CTRL_MODE_OFB (MXC_V_TPU_CIPHER_CTRL_MODE_OFB << MXC_F_TPU_CIPHER_CTRL_MODE_POS) /**< CIPHER_CTRL_MODE_OFB Setting */ 327 #define MXC_V_TPU_CIPHER_CTRL_MODE_CTR ((uint32_t)0x4UL) /**< CIPHER_CTRL_MODE_CTR Value */ 328 #define MXC_S_TPU_CIPHER_CTRL_MODE_CTR (MXC_V_TPU_CIPHER_CTRL_MODE_CTR << MXC_F_TPU_CIPHER_CTRL_MODE_POS) /**< CIPHER_CTRL_MODE_CTR Setting */ 329 330 /**@} end of group TPU_CIPHER_CTRL_Register */ 331 332 /** 333 * @ingroup tpu_registers 334 * @defgroup TPU_HASH_CTRL TPU_HASH_CTRL 335 * @brief HASH Control Register. 336 * @{ 337 */ 338 #define MXC_F_TPU_HASH_CTRL_INIT_POS 0 /**< HASH_CTRL_INIT Position */ 339 #define MXC_F_TPU_HASH_CTRL_INIT ((uint32_t)(0x1UL << MXC_F_TPU_HASH_CTRL_INIT_POS)) /**< HASH_CTRL_INIT Mask */ 340 #define MXC_V_TPU_HASH_CTRL_INIT_NOP ((uint32_t)0x0UL) /**< HASH_CTRL_INIT_NOP Value */ 341 #define MXC_S_TPU_HASH_CTRL_INIT_NOP (MXC_V_TPU_HASH_CTRL_INIT_NOP << MXC_F_TPU_HASH_CTRL_INIT_POS) /**< HASH_CTRL_INIT_NOP Setting */ 342 #define MXC_V_TPU_HASH_CTRL_INIT_START ((uint32_t)0x1UL) /**< HASH_CTRL_INIT_START Value */ 343 #define MXC_S_TPU_HASH_CTRL_INIT_START (MXC_V_TPU_HASH_CTRL_INIT_START << MXC_F_TPU_HASH_CTRL_INIT_POS) /**< HASH_CTRL_INIT_START Setting */ 344 345 #define MXC_F_TPU_HASH_CTRL_XOR_POS 1 /**< HASH_CTRL_XOR Position */ 346 #define MXC_F_TPU_HASH_CTRL_XOR ((uint32_t)(0x1UL << MXC_F_TPU_HASH_CTRL_XOR_POS)) /**< HASH_CTRL_XOR Mask */ 347 #define MXC_V_TPU_HASH_CTRL_XOR_DIS ((uint32_t)0x0UL) /**< HASH_CTRL_XOR_DIS Value */ 348 #define MXC_S_TPU_HASH_CTRL_XOR_DIS (MXC_V_TPU_HASH_CTRL_XOR_DIS << MXC_F_TPU_HASH_CTRL_XOR_POS) /**< HASH_CTRL_XOR_DIS Setting */ 349 #define MXC_V_TPU_HASH_CTRL_XOR_EN ((uint32_t)0x1UL) /**< HASH_CTRL_XOR_EN Value */ 350 #define MXC_S_TPU_HASH_CTRL_XOR_EN (MXC_V_TPU_HASH_CTRL_XOR_EN << MXC_F_TPU_HASH_CTRL_XOR_POS) /**< HASH_CTRL_XOR_EN Setting */ 351 352 #define MXC_F_TPU_HASH_CTRL_HASH_POS 2 /**< HASH_CTRL_HASH Position */ 353 #define MXC_F_TPU_HASH_CTRL_HASH ((uint32_t)(0x7UL << MXC_F_TPU_HASH_CTRL_HASH_POS)) /**< HASH_CTRL_HASH Mask */ 354 #define MXC_V_TPU_HASH_CTRL_HASH_DIS ((uint32_t)0x0UL) /**< HASH_CTRL_HASH_DIS Value */ 355 #define MXC_S_TPU_HASH_CTRL_HASH_DIS (MXC_V_TPU_HASH_CTRL_HASH_DIS << MXC_F_TPU_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_DIS Setting */ 356 #define MXC_V_TPU_HASH_CTRL_HASH_SHA1 ((uint32_t)0x1UL) /**< HASH_CTRL_HASH_SHA1 Value */ 357 #define MXC_S_TPU_HASH_CTRL_HASH_SHA1 (MXC_V_TPU_HASH_CTRL_HASH_SHA1 << MXC_F_TPU_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_SHA1 Setting */ 358 #define MXC_V_TPU_HASH_CTRL_HASH_SHA224 ((uint32_t)0x2UL) /**< HASH_CTRL_HASH_SHA224 Value */ 359 #define MXC_S_TPU_HASH_CTRL_HASH_SHA224 (MXC_V_TPU_HASH_CTRL_HASH_SHA224 << MXC_F_TPU_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_SHA224 Setting */ 360 #define MXC_V_TPU_HASH_CTRL_HASH_SHA256 ((uint32_t)0x3UL) /**< HASH_CTRL_HASH_SHA256 Value */ 361 #define MXC_S_TPU_HASH_CTRL_HASH_SHA256 (MXC_V_TPU_HASH_CTRL_HASH_SHA256 << MXC_F_TPU_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_SHA256 Setting */ 362 #define MXC_V_TPU_HASH_CTRL_HASH_SHA384 ((uint32_t)0x4UL) /**< HASH_CTRL_HASH_SHA384 Value */ 363 #define MXC_S_TPU_HASH_CTRL_HASH_SHA384 (MXC_V_TPU_HASH_CTRL_HASH_SHA384 << MXC_F_TPU_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_SHA384 Setting */ 364 #define MXC_V_TPU_HASH_CTRL_HASH_SHA512 ((uint32_t)0x5UL) /**< HASH_CTRL_HASH_SHA512 Value */ 365 #define MXC_S_TPU_HASH_CTRL_HASH_SHA512 (MXC_V_TPU_HASH_CTRL_HASH_SHA512 << MXC_F_TPU_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_SHA512 Setting */ 366 367 #define MXC_F_TPU_HASH_CTRL_LAST_POS 5 /**< HASH_CTRL_LAST Position */ 368 #define MXC_F_TPU_HASH_CTRL_LAST ((uint32_t)(0x1UL << MXC_F_TPU_HASH_CTRL_LAST_POS)) /**< HASH_CTRL_LAST Mask */ 369 #define MXC_V_TPU_HASH_CTRL_LAST_NOEFFECT ((uint32_t)0x0UL) /**< HASH_CTRL_LAST_NOEFFECT Value */ 370 #define MXC_S_TPU_HASH_CTRL_LAST_NOEFFECT (MXC_V_TPU_HASH_CTRL_LAST_NOEFFECT << MXC_F_TPU_HASH_CTRL_LAST_POS) /**< HASH_CTRL_LAST_NOEFFECT Setting */ 371 #define MXC_V_TPU_HASH_CTRL_LAST_LASTMSGDATA ((uint32_t)0x1UL) /**< HASH_CTRL_LAST_LASTMSGDATA Value */ 372 #define MXC_S_TPU_HASH_CTRL_LAST_LASTMSGDATA (MXC_V_TPU_HASH_CTRL_LAST_LASTMSGDATA << MXC_F_TPU_HASH_CTRL_LAST_POS) /**< HASH_CTRL_LAST_LASTMSGDATA Setting */ 373 374 /**@} end of group TPU_HASH_CTRL_Register */ 375 376 /** 377 * @ingroup tpu_registers 378 * @defgroup TPU_CRC_CTRL TPU_CRC_CTRL 379 * @brief CRC Control Register. 380 * @{ 381 */ 382 #define MXC_F_TPU_CRC_CTRL_CRC_EN_POS 0 /**< CRC_CTRL_CRC_EN Position */ 383 #define MXC_F_TPU_CRC_CTRL_CRC_EN ((uint32_t)(0x1UL << MXC_F_TPU_CRC_CTRL_CRC_EN_POS)) /**< CRC_CTRL_CRC_EN Mask */ 384 #define MXC_V_TPU_CRC_CTRL_CRC_EN_DIS ((uint32_t)0x0UL) /**< CRC_CTRL_CRC_EN_DIS Value */ 385 #define MXC_S_TPU_CRC_CTRL_CRC_EN_DIS (MXC_V_TPU_CRC_CTRL_CRC_EN_DIS << MXC_F_TPU_CRC_CTRL_CRC_EN_POS) /**< CRC_CTRL_CRC_EN_DIS Setting */ 386 #define MXC_V_TPU_CRC_CTRL_CRC_EN_EN ((uint32_t)0x1UL) /**< CRC_CTRL_CRC_EN_EN Value */ 387 #define MXC_S_TPU_CRC_CTRL_CRC_EN_EN (MXC_V_TPU_CRC_CTRL_CRC_EN_EN << MXC_F_TPU_CRC_CTRL_CRC_EN_POS) /**< CRC_CTRL_CRC_EN_EN Setting */ 388 389 #define MXC_F_TPU_CRC_CTRL_MSB_POS 1 /**< CRC_CTRL_MSB Position */ 390 #define MXC_F_TPU_CRC_CTRL_MSB ((uint32_t)(0x1UL << MXC_F_TPU_CRC_CTRL_MSB_POS)) /**< CRC_CTRL_MSB Mask */ 391 #define MXC_V_TPU_CRC_CTRL_MSB_LSBFIRST ((uint32_t)0x0UL) /**< CRC_CTRL_MSB_LSBFIRST Value */ 392 #define MXC_S_TPU_CRC_CTRL_MSB_LSBFIRST (MXC_V_TPU_CRC_CTRL_MSB_LSBFIRST << MXC_F_TPU_CRC_CTRL_MSB_POS) /**< CRC_CTRL_MSB_LSBFIRST Setting */ 393 #define MXC_V_TPU_CRC_CTRL_MSB_MSBFIRST ((uint32_t)0x1UL) /**< CRC_CTRL_MSB_MSBFIRST Value */ 394 #define MXC_S_TPU_CRC_CTRL_MSB_MSBFIRST (MXC_V_TPU_CRC_CTRL_MSB_MSBFIRST << MXC_F_TPU_CRC_CTRL_MSB_POS) /**< CRC_CTRL_MSB_MSBFIRST Setting */ 395 396 #define MXC_F_TPU_CRC_CTRL_PRNG_POS 2 /**< CRC_CTRL_PRNG Position */ 397 #define MXC_F_TPU_CRC_CTRL_PRNG ((uint32_t)(0x1UL << MXC_F_TPU_CRC_CTRL_PRNG_POS)) /**< CRC_CTRL_PRNG Mask */ 398 #define MXC_V_TPU_CRC_CTRL_PRNG_DIS ((uint32_t)0x0UL) /**< CRC_CTRL_PRNG_DIS Value */ 399 #define MXC_S_TPU_CRC_CTRL_PRNG_DIS (MXC_V_TPU_CRC_CTRL_PRNG_DIS << MXC_F_TPU_CRC_CTRL_PRNG_POS) /**< CRC_CTRL_PRNG_DIS Setting */ 400 #define MXC_V_TPU_CRC_CTRL_PRNG_EN ((uint32_t)0x1UL) /**< CRC_CTRL_PRNG_EN Value */ 401 #define MXC_S_TPU_CRC_CTRL_PRNG_EN (MXC_V_TPU_CRC_CTRL_PRNG_EN << MXC_F_TPU_CRC_CTRL_PRNG_POS) /**< CRC_CTRL_PRNG_EN Setting */ 402 403 #define MXC_F_TPU_CRC_CTRL_ENT_POS 3 /**< CRC_CTRL_ENT Position */ 404 #define MXC_F_TPU_CRC_CTRL_ENT ((uint32_t)(0x1UL << MXC_F_TPU_CRC_CTRL_ENT_POS)) /**< CRC_CTRL_ENT Mask */ 405 #define MXC_V_TPU_CRC_CTRL_ENT_DIS ((uint32_t)0x0UL) /**< CRC_CTRL_ENT_DIS Value */ 406 #define MXC_S_TPU_CRC_CTRL_ENT_DIS (MXC_V_TPU_CRC_CTRL_ENT_DIS << MXC_F_TPU_CRC_CTRL_ENT_POS) /**< CRC_CTRL_ENT_DIS Setting */ 407 #define MXC_V_TPU_CRC_CTRL_ENT_EN ((uint32_t)0x1UL) /**< CRC_CTRL_ENT_EN Value */ 408 #define MXC_S_TPU_CRC_CTRL_ENT_EN (MXC_V_TPU_CRC_CTRL_ENT_EN << MXC_F_TPU_CRC_CTRL_ENT_POS) /**< CRC_CTRL_ENT_EN Setting */ 409 410 #define MXC_F_TPU_CRC_CTRL_HAM_POS 4 /**< CRC_CTRL_HAM Position */ 411 #define MXC_F_TPU_CRC_CTRL_HAM ((uint32_t)(0x1UL << MXC_F_TPU_CRC_CTRL_HAM_POS)) /**< CRC_CTRL_HAM Mask */ 412 #define MXC_V_TPU_CRC_CTRL_HAM_DIS ((uint32_t)0x0UL) /**< CRC_CTRL_HAM_DIS Value */ 413 #define MXC_S_TPU_CRC_CTRL_HAM_DIS (MXC_V_TPU_CRC_CTRL_HAM_DIS << MXC_F_TPU_CRC_CTRL_HAM_POS) /**< CRC_CTRL_HAM_DIS Setting */ 414 #define MXC_V_TPU_CRC_CTRL_HAM_EN ((uint32_t)0x1UL) /**< CRC_CTRL_HAM_EN Value */ 415 #define MXC_S_TPU_CRC_CTRL_HAM_EN (MXC_V_TPU_CRC_CTRL_HAM_EN << MXC_F_TPU_CRC_CTRL_HAM_POS) /**< CRC_CTRL_HAM_EN Setting */ 416 417 #define MXC_F_TPU_CRC_CTRL_HRST_POS 5 /**< CRC_CTRL_HRST Position */ 418 #define MXC_F_TPU_CRC_CTRL_HRST ((uint32_t)(0x1UL << MXC_F_TPU_CRC_CTRL_HRST_POS)) /**< CRC_CTRL_HRST Mask */ 419 #define MXC_V_TPU_CRC_CTRL_HRST_RESET ((uint32_t)0x1UL) /**< CRC_CTRL_HRST_RESET Value */ 420 #define MXC_S_TPU_CRC_CTRL_HRST_RESET (MXC_V_TPU_CRC_CTRL_HRST_RESET << MXC_F_TPU_CRC_CTRL_HRST_POS) /**< CRC_CTRL_HRST_RESET Setting */ 421 422 /**@} end of group TPU_CRC_CTRL_Register */ 423 424 /** 425 * @ingroup tpu_registers 426 * @defgroup TPU_DMA_SRC TPU_DMA_SRC 427 * @brief Crypto DMA Source Address. 428 * @{ 429 */ 430 #define MXC_F_TPU_DMA_SRC_ADDR_POS 0 /**< DMA_SRC_ADDR Position */ 431 #define MXC_F_TPU_DMA_SRC_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_DMA_SRC_ADDR_POS)) /**< DMA_SRC_ADDR Mask */ 432 433 /**@} end of group TPU_DMA_SRC_Register */ 434 435 /** 436 * @ingroup tpu_registers 437 * @defgroup TPU_DMA_DEST TPU_DMA_DEST 438 * @brief Crypto DMA Destination Address. 439 * @{ 440 */ 441 #define MXC_F_TPU_DMA_DEST_ADDR_POS 0 /**< DMA_DEST_ADDR Position */ 442 #define MXC_F_TPU_DMA_DEST_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_DMA_DEST_ADDR_POS)) /**< DMA_DEST_ADDR Mask */ 443 444 /**@} end of group TPU_DMA_DEST_Register */ 445 446 /** 447 * @ingroup tpu_registers 448 * @defgroup TPU_DMA_CNT TPU_DMA_CNT 449 * @brief Crypto DMA Byte Count. 450 * @{ 451 */ 452 #define MXC_F_TPU_DMA_CNT_COUNT_POS 0 /**< DMA_CNT_COUNT Position */ 453 #define MXC_F_TPU_DMA_CNT_COUNT ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_DMA_CNT_COUNT_POS)) /**< DMA_CNT_COUNT Mask */ 454 455 /**@} end of group TPU_DMA_CNT_Register */ 456 457 /** 458 * @ingroup tpu_registers 459 * @defgroup TPU_MAA_CTRL TPU_MAA_CTRL 460 * @brief MAA Control Register. 461 * @{ 462 */ 463 #define MXC_F_TPU_MAA_CTRL_STC_POS 0 /**< MAA_CTRL_STC Position */ 464 #define MXC_F_TPU_MAA_CTRL_STC ((uint32_t)(0x1UL << MXC_F_TPU_MAA_CTRL_STC_POS)) /**< MAA_CTRL_STC Mask */ 465 #define MXC_V_TPU_MAA_CTRL_STC_NOP ((uint32_t)0x0UL) /**< MAA_CTRL_STC_NOP Value */ 466 #define MXC_S_TPU_MAA_CTRL_STC_NOP (MXC_V_TPU_MAA_CTRL_STC_NOP << MXC_F_TPU_MAA_CTRL_STC_POS) /**< MAA_CTRL_STC_NOP Setting */ 467 #define MXC_V_TPU_MAA_CTRL_STC_START ((uint32_t)0x1UL) /**< MAA_CTRL_STC_START Value */ 468 #define MXC_S_TPU_MAA_CTRL_STC_START (MXC_V_TPU_MAA_CTRL_STC_START << MXC_F_TPU_MAA_CTRL_STC_POS) /**< MAA_CTRL_STC_START Setting */ 469 470 #define MXC_F_TPU_MAA_CTRL_CLC_POS 1 /**< MAA_CTRL_CLC Position */ 471 #define MXC_F_TPU_MAA_CTRL_CLC ((uint32_t)(0x7UL << MXC_F_TPU_MAA_CTRL_CLC_POS)) /**< MAA_CTRL_CLC Mask */ 472 #define MXC_V_TPU_MAA_CTRL_CLC_EXP ((uint32_t)0x0UL) /**< MAA_CTRL_CLC_EXP Value */ 473 #define MXC_S_TPU_MAA_CTRL_CLC_EXP (MXC_V_TPU_MAA_CTRL_CLC_EXP << MXC_F_TPU_MAA_CTRL_CLC_POS) /**< MAA_CTRL_CLC_EXP Setting */ 474 #define MXC_V_TPU_MAA_CTRL_CLC_SQ ((uint32_t)0x1UL) /**< MAA_CTRL_CLC_SQ Value */ 475 #define MXC_S_TPU_MAA_CTRL_CLC_SQ (MXC_V_TPU_MAA_CTRL_CLC_SQ << MXC_F_TPU_MAA_CTRL_CLC_POS) /**< MAA_CTRL_CLC_SQ Setting */ 476 #define MXC_V_TPU_MAA_CTRL_CLC_MULT ((uint32_t)0x2UL) /**< MAA_CTRL_CLC_MULT Value */ 477 #define MXC_S_TPU_MAA_CTRL_CLC_MULT (MXC_V_TPU_MAA_CTRL_CLC_MULT << MXC_F_TPU_MAA_CTRL_CLC_POS) /**< MAA_CTRL_CLC_MULT Setting */ 478 #define MXC_V_TPU_MAA_CTRL_CLC_SQ_MULT ((uint32_t)0x3UL) /**< MAA_CTRL_CLC_SQ_MULT Value */ 479 #define MXC_S_TPU_MAA_CTRL_CLC_SQ_MULT (MXC_V_TPU_MAA_CTRL_CLC_SQ_MULT << MXC_F_TPU_MAA_CTRL_CLC_POS) /**< MAA_CTRL_CLC_SQ_MULT Setting */ 480 #define MXC_V_TPU_MAA_CTRL_CLC_ADD ((uint32_t)0x4UL) /**< MAA_CTRL_CLC_ADD Value */ 481 #define MXC_S_TPU_MAA_CTRL_CLC_ADD (MXC_V_TPU_MAA_CTRL_CLC_ADD << MXC_F_TPU_MAA_CTRL_CLC_POS) /**< MAA_CTRL_CLC_ADD Setting */ 482 #define MXC_V_TPU_MAA_CTRL_CLC_SUB ((uint32_t)0x5UL) /**< MAA_CTRL_CLC_SUB Value */ 483 #define MXC_S_TPU_MAA_CTRL_CLC_SUB (MXC_V_TPU_MAA_CTRL_CLC_SUB << MXC_F_TPU_MAA_CTRL_CLC_POS) /**< MAA_CTRL_CLC_SUB Setting */ 484 485 #define MXC_F_TPU_MAA_CTRL_OCALC_POS 4 /**< MAA_CTRL_OCALC Position */ 486 #define MXC_F_TPU_MAA_CTRL_OCALC ((uint32_t)(0x1UL << MXC_F_TPU_MAA_CTRL_OCALC_POS)) /**< MAA_CTRL_OCALC Mask */ 487 #define MXC_V_TPU_MAA_CTRL_OCALC_NONE ((uint32_t)0x0UL) /**< MAA_CTRL_OCALC_NONE Value */ 488 #define MXC_S_TPU_MAA_CTRL_OCALC_NONE (MXC_V_TPU_MAA_CTRL_OCALC_NONE << MXC_F_TPU_MAA_CTRL_OCALC_POS) /**< MAA_CTRL_OCALC_NONE Setting */ 489 #define MXC_V_TPU_MAA_CTRL_OCALC_OPTIMIZE ((uint32_t)0x1UL) /**< MAA_CTRL_OCALC_OPTIMIZE Value */ 490 #define MXC_S_TPU_MAA_CTRL_OCALC_OPTIMIZE (MXC_V_TPU_MAA_CTRL_OCALC_OPTIMIZE << MXC_F_TPU_MAA_CTRL_OCALC_POS) /**< MAA_CTRL_OCALC_OPTIMIZE Setting */ 491 492 #define MXC_F_TPU_MAA_CTRL_MAAER_POS 7 /**< MAA_CTRL_MAAER Position */ 493 #define MXC_F_TPU_MAA_CTRL_MAAER ((uint32_t)(0x1UL << MXC_F_TPU_MAA_CTRL_MAAER_POS)) /**< MAA_CTRL_MAAER Mask */ 494 #define MXC_V_TPU_MAA_CTRL_MAAER_NOERROR ((uint32_t)0x0UL) /**< MAA_CTRL_MAAER_NOERROR Value */ 495 #define MXC_S_TPU_MAA_CTRL_MAAER_NOERROR (MXC_V_TPU_MAA_CTRL_MAAER_NOERROR << MXC_F_TPU_MAA_CTRL_MAAER_POS) /**< MAA_CTRL_MAAER_NOERROR Setting */ 496 #define MXC_V_TPU_MAA_CTRL_MAAER_ERROR ((uint32_t)0x1UL) /**< MAA_CTRL_MAAER_ERROR Value */ 497 #define MXC_S_TPU_MAA_CTRL_MAAER_ERROR (MXC_V_TPU_MAA_CTRL_MAAER_ERROR << MXC_F_TPU_MAA_CTRL_MAAER_POS) /**< MAA_CTRL_MAAER_ERROR Setting */ 498 499 #define MXC_F_TPU_MAA_CTRL_AMS_POS 8 /**< MAA_CTRL_AMS Position */ 500 #define MXC_F_TPU_MAA_CTRL_AMS ((uint32_t)(0x3UL << MXC_F_TPU_MAA_CTRL_AMS_POS)) /**< MAA_CTRL_AMS Mask */ 501 502 #define MXC_F_TPU_MAA_CTRL_BMS_POS 10 /**< MAA_CTRL_BMS Position */ 503 #define MXC_F_TPU_MAA_CTRL_BMS ((uint32_t)(0x3UL << MXC_F_TPU_MAA_CTRL_BMS_POS)) /**< MAA_CTRL_BMS Mask */ 504 505 #define MXC_F_TPU_MAA_CTRL_EMS_POS 12 /**< MAA_CTRL_EMS Position */ 506 #define MXC_F_TPU_MAA_CTRL_EMS ((uint32_t)(0x3UL << MXC_F_TPU_MAA_CTRL_EMS_POS)) /**< MAA_CTRL_EMS Mask */ 507 508 #define MXC_F_TPU_MAA_CTRL_MMS_POS 14 /**< MAA_CTRL_MMS Position */ 509 #define MXC_F_TPU_MAA_CTRL_MMS ((uint32_t)(0x3UL << MXC_F_TPU_MAA_CTRL_MMS_POS)) /**< MAA_CTRL_MMS Mask */ 510 511 #define MXC_F_TPU_MAA_CTRL_AMA_POS 16 /**< MAA_CTRL_AMA Position */ 512 #define MXC_F_TPU_MAA_CTRL_AMA ((uint32_t)(0xFUL << MXC_F_TPU_MAA_CTRL_AMA_POS)) /**< MAA_CTRL_AMA Mask */ 513 514 #define MXC_F_TPU_MAA_CTRL_BMA_POS 20 /**< MAA_CTRL_BMA Position */ 515 #define MXC_F_TPU_MAA_CTRL_BMA ((uint32_t)(0xFUL << MXC_F_TPU_MAA_CTRL_BMA_POS)) /**< MAA_CTRL_BMA Mask */ 516 517 #define MXC_F_TPU_MAA_CTRL_RMA_POS 24 /**< MAA_CTRL_RMA Position */ 518 #define MXC_F_TPU_MAA_CTRL_RMA ((uint32_t)(0xFUL << MXC_F_TPU_MAA_CTRL_RMA_POS)) /**< MAA_CTRL_RMA Mask */ 519 520 #define MXC_F_TPU_MAA_CTRL_TMA_POS 28 /**< MAA_CTRL_TMA Position */ 521 #define MXC_F_TPU_MAA_CTRL_TMA ((uint32_t)(0xFUL << MXC_F_TPU_MAA_CTRL_TMA_POS)) /**< MAA_CTRL_TMA Mask */ 522 523 /**@} end of group TPU_MAA_CTRL_Register */ 524 525 /** 526 * @ingroup tpu_registers 527 * @defgroup TPU_CRYPTO_DIN TPU_CRYPTO_DIN 528 * @brief Crypto Data Input. Data input can be written to this register instead of using 529 * the DMA. This register writes to the FIFO. This register occupies four 530 * successive words to allow the use of multi-store instructions. Words can be 531 * written to any location, they will be placed in the FIFO in the order they are 532 * written. The endian swap input control bit affects this register. 533 * @{ 534 */ 535 #define MXC_F_TPU_CRYPTO_DIN_DATA_POS 0 /**< CRYPTO_DIN_DATA Position */ 536 #define MXC_F_TPU_CRYPTO_DIN_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_CRYPTO_DIN_DATA_POS)) /**< CRYPTO_DIN_DATA Mask */ 537 538 /**@} end of group TPU_CRYPTO_DIN_Register */ 539 540 /** 541 * @ingroup tpu_registers 542 * @defgroup TPU_CRYPTO_DOUT TPU_CRYPTO_DOUT 543 * @brief Crypto Data Output. Resulting data from cipher calculation. Data is placed in 544 * the lower words of these four registers depending on the algorithm. For block 545 * cipher modes, this register holds the result of most recent encryption or 546 * decryption operation. These registers are affected by the endian swap bits. 547 * @{ 548 */ 549 #define MXC_F_TPU_CRYPTO_DOUT_DATA_POS 0 /**< CRYPTO_DOUT_DATA Position */ 550 #define MXC_F_TPU_CRYPTO_DOUT_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_CRYPTO_DOUT_DATA_POS)) /**< CRYPTO_DOUT_DATA Mask */ 551 552 /**@} end of group TPU_CRYPTO_DOUT_Register */ 553 554 /** 555 * @ingroup tpu_registers 556 * @defgroup TPU_CRC_POLY TPU_CRC_POLY 557 * @brief CRC Polynomial. The polynomial to be used for Galois Field calculations (CRC or 558 * LFSR) should be written to this register. This register is affected by the MSB 559 * control bit. 560 * @{ 561 */ 562 #define MXC_F_TPU_CRC_POLY_POLY_POS 0 /**< CRC_POLY_POLY Position */ 563 #define MXC_F_TPU_CRC_POLY_POLY ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_CRC_POLY_POLY_POS)) /**< CRC_POLY_POLY Mask */ 564 565 /**@} end of group TPU_CRC_POLY_Register */ 566 567 /** 568 * @ingroup tpu_registers 569 * @defgroup TPU_CRC_VAL TPU_CRC_VAL 570 * @brief CRC Value. This is the state for the Galois Field. This register holds the 571 * result of a CRC calculation or the current state of the LFSR. This register is 572 * affected by the MSB control bit. 573 * @{ 574 */ 575 #define MXC_F_TPU_CRC_VAL_VAL_POS 0 /**< CRC_VAL_VAL Position */ 576 #define MXC_F_TPU_CRC_VAL_VAL ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_CRC_VAL_VAL_POS)) /**< CRC_VAL_VAL Mask */ 577 578 /**@} end of group TPU_CRC_VAL_Register */ 579 580 /** 581 * @ingroup tpu_registers 582 * @defgroup TPU_CRC_PRNG TPU_CRC_PRNG 583 * @brief Pseudo Random Value. Output of the Galois Field shift register. This holds the 584 * resulting pseudo-random number if entropy is disabled or true random number if 585 * entropy is enabled. 586 * @{ 587 */ 588 #define MXC_F_TPU_CRC_PRNG_PRNG_POS 0 /**< CRC_PRNG_PRNG Position */ 589 #define MXC_F_TPU_CRC_PRNG_PRNG ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_CRC_PRNG_PRNG_POS)) /**< CRC_PRNG_PRNG Mask */ 590 591 /**@} end of group TPU_CRC_PRNG_Register */ 592 593 /** 594 * @ingroup tpu_registers 595 * @defgroup TPU_HAM_ECC TPU_HAM_ECC 596 * @brief Hamming ECC Register. 597 * @{ 598 */ 599 #define MXC_F_TPU_HAM_ECC_ECC_POS 0 /**< HAM_ECC_ECC Position */ 600 #define MXC_F_TPU_HAM_ECC_ECC ((uint32_t)(0xFFFFUL << MXC_F_TPU_HAM_ECC_ECC_POS)) /**< HAM_ECC_ECC Mask */ 601 602 #define MXC_F_TPU_HAM_ECC_PAR_POS 16 /**< HAM_ECC_PAR Position */ 603 #define MXC_F_TPU_HAM_ECC_PAR ((uint32_t)(0x1UL << MXC_F_TPU_HAM_ECC_PAR_POS)) /**< HAM_ECC_PAR Mask */ 604 #define MXC_V_TPU_HAM_ECC_PAR_EVEN ((uint32_t)0x0UL) /**< HAM_ECC_PAR_EVEN Value */ 605 #define MXC_S_TPU_HAM_ECC_PAR_EVEN (MXC_V_TPU_HAM_ECC_PAR_EVEN << MXC_F_TPU_HAM_ECC_PAR_POS) /**< HAM_ECC_PAR_EVEN Setting */ 606 #define MXC_V_TPU_HAM_ECC_PAR_ODD ((uint32_t)0x1UL) /**< HAM_ECC_PAR_ODD Value */ 607 #define MXC_S_TPU_HAM_ECC_PAR_ODD (MXC_V_TPU_HAM_ECC_PAR_ODD << MXC_F_TPU_HAM_ECC_PAR_POS) /**< HAM_ECC_PAR_ODD Setting */ 608 609 /**@} end of group TPU_HAM_ECC_Register */ 610 611 /** 612 * @ingroup tpu_registers 613 * @defgroup TPU_CIPHER_INIT TPU_CIPHER_INIT 614 * @brief Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR 615 * modes, this register holds the initial value. This register is updated with each 616 * encryption or decryption operation. This register is affected by the endian swap 617 * bits. 618 * @{ 619 */ 620 #define MXC_F_TPU_CIPHER_INIT_IVEC_POS 0 /**< CIPHER_INIT_IVEC Position */ 621 #define MXC_F_TPU_CIPHER_INIT_IVEC ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_CIPHER_INIT_IVEC_POS)) /**< CIPHER_INIT_IVEC Mask */ 622 623 /**@} end of group TPU_CIPHER_INIT_Register */ 624 625 /** 626 * @ingroup tpu_registers 627 * @defgroup TPU_CIPHER_KEY TPU_CIPHER_KEY 628 * @brief Cipher Key. This register holds the key used for block cipher operations. The 629 * lower words are used for block ciphers that use shorter key lengths. This 630 * register is affected by the endian swap input control bits. 631 * @{ 632 */ 633 #define MXC_F_TPU_CIPHER_KEY_KEY_POS 0 /**< CIPHER_KEY_KEY Position */ 634 #define MXC_F_TPU_CIPHER_KEY_KEY ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_CIPHER_KEY_KEY_POS)) /**< CIPHER_KEY_KEY Mask */ 635 636 /**@} end of group TPU_CIPHER_KEY_Register */ 637 638 /** 639 * @ingroup tpu_registers 640 * @defgroup TPU_HASH_DIGEST TPU_HASH_DIGEST 641 * @brief This register holds the calculated hash value. This register is affected by the 642 * endian swap bits. 643 * @{ 644 */ 645 #define MXC_F_TPU_HASH_DIGEST_HASH_POS 0 /**< HASH_DIGEST_HASH Position */ 646 #define MXC_F_TPU_HASH_DIGEST_HASH ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_HASH_DIGEST_HASH_POS)) /**< HASH_DIGEST_HASH Mask */ 647 648 /**@} end of group TPU_HASH_DIGEST_Register */ 649 650 /** 651 * @ingroup tpu_registers 652 * @defgroup TPU_HASH_MSG_SZ TPU_HASH_MSG_SZ 653 * @brief Message Size. This register holds the lowest 32-bit of message size in bytes. 654 * @{ 655 */ 656 #define MXC_F_TPU_HASH_MSG_SZ_MSGSZ_POS 0 /**< HASH_MSG_SZ_MSGSZ Position */ 657 #define MXC_F_TPU_HASH_MSG_SZ_MSGSZ ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_HASH_MSG_SZ_MSGSZ_POS)) /**< HASH_MSG_SZ_MSGSZ Mask */ 658 659 /**@} end of group TPU_HASH_MSG_SZ_Register */ 660 661 /** 662 * @ingroup tpu_registers 663 * @defgroup TPU_MAA_MAWS TPU_MAA_MAWS 664 * @brief MAA Word Size. This register defines the number of bits for a modular operation. 665 * This register must be set to a valid value prior to the MAA operation start. 666 * Valid values are from 1 to 2048. Invalid values are ignored and will not 667 * initiate a MAA operation. 668 * @{ 669 */ 670 #define MXC_F_TPU_MAA_MAWS_MSGSZ_POS 0 /**< MAA_MAWS_MSGSZ Position */ 671 #define MXC_F_TPU_MAA_MAWS_MSGSZ ((uint32_t)(0xFFFUL << MXC_F_TPU_MAA_MAWS_MSGSZ_POS)) /**< MAA_MAWS_MSGSZ Mask */ 672 673 /**@} end of group TPU_MAA_MAWS_Register */ 674 675 #ifdef __cplusplus 676 } 677 #endif 678 679 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_TPU_REGS_H_ 680
