1 /** 2 * @file ctb_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the CTB Peripheral Module. 4 * @note This file is @generated. 5 */ 6 7 /****************************************************************************** 8 * 9 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 10 * Analog Devices, Inc.), 11 * Copyright (C) 2023-2024 Analog Devices, Inc. 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the License at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 ******************************************************************************/ 26 27 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_CTB_REGS_H_ 28 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_CTB_REGS_H_ 29 30 /* **** Includes **** */ 31 #include <stdint.h> 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 #if defined (__ICCARM__) 38 #pragma system_include 39 #endif 40 41 #if defined (__CC_ARM) 42 #pragma anon_unions 43 #endif 44 /// @cond 45 /* 46 If types are not defined elsewhere (CMSIS) define them here 47 */ 48 #ifndef __IO 49 #define __IO volatile 50 #endif 51 #ifndef __I 52 #define __I volatile const 53 #endif 54 #ifndef __O 55 #define __O volatile 56 #endif 57 #ifndef __R 58 #define __R volatile const 59 #endif 60 /// @endcond 61 62 /* **** Definitions **** */ 63 64 /** 65 * @ingroup ctb 66 * @defgroup ctb_registers CTB_Registers 67 * @brief Registers, Bit Masks and Bit Positions for the CTB Peripheral Module. 68 * @details The Cryptographic Toolbox is a combination of cryptographic engines and a secure cryptographic accelerator (SCA) used to provide advanced cryptographic security. 69 */ 70 71 /** 72 * @ingroup ctb_registers 73 * Structure type to access the CTB Registers. 74 */ 75 typedef struct { 76 __IO uint32_t crypto_ctrl; /**< <tt>\b 0x00:</tt> CTB CRYPTO_CTRL Register */ 77 __IO uint32_t cipher_ctrl; /**< <tt>\b 0x04:</tt> CTB CIPHER_CTRL Register */ 78 __IO uint32_t hash_ctrl; /**< <tt>\b 0x08:</tt> CTB HASH_CTRL Register */ 79 __IO uint32_t crc_ctrl; /**< <tt>\b 0x0C:</tt> CTB CRC_CTRL Register */ 80 __IO uint32_t dma_src; /**< <tt>\b 0x10:</tt> CTB DMA_SRC Register */ 81 __IO uint32_t dma_dest; /**< <tt>\b 0x14:</tt> CTB DMA_DEST Register */ 82 __IO uint32_t dma_cnt; /**< <tt>\b 0x18:</tt> CTB DMA_CNT Register */ 83 __R uint32_t rsv_0x1c; 84 __O uint32_t crypto_din[4]; /**< <tt>\b 0x20:</tt> CTB CRYPTO_DIN Register */ 85 __I uint32_t crypto_dout[4]; /**< <tt>\b 0x30:</tt> CTB CRYPTO_DOUT Register */ 86 __IO uint32_t crc_poly; /**< <tt>\b 0x40:</tt> CTB CRC_POLY Register */ 87 __IO uint32_t crc_val; /**< <tt>\b 0x44:</tt> CTB CRC_VAL Register */ 88 __R uint32_t rsv_0x48; 89 __IO uint32_t ham_ecc; /**< <tt>\b 0x4C:</tt> CTB HAM_ECC Register */ 90 __IO uint32_t cipher_init[4]; /**< <tt>\b 0x50:</tt> CTB CIPHER_INIT Register */ 91 __O uint32_t cipher_key[8]; /**< <tt>\b 0x60:</tt> CTB CIPHER_KEY Register */ 92 __IO uint32_t hash_digest[16]; /**< <tt>\b 0x80:</tt> CTB HASH_DIGEST Register */ 93 __IO uint32_t hash_msg_sz[4]; /**< <tt>\b 0xC0:</tt> CTB HASH_MSG_SZ Register */ 94 __IO uint32_t aad_length_0; /**< <tt>\b 0xD0:</tt> CTB AAD_LENGTH_0 Register */ 95 __IO uint32_t aad_length_1; /**< <tt>\b 0xD4:</tt> CTB AAD_LENGTH_1 Register */ 96 __IO uint32_t pld_length_0; /**< <tt>\b 0xD8:</tt> CTB PLD_LENGTH_0 Register */ 97 __IO uint32_t pld_length_1; /**< <tt>\b 0xDC:</tt> CTB PLD_LENGTH_1 Register */ 98 __IO uint32_t tagmic[4]; /**< <tt>\b 0xE0:</tt> CTB TAGMIC Register */ 99 __R uint32_t rsv_0xf0_0xff[4]; 100 __IO uint32_t sca_ctrl0; /**< <tt>\b 0x100:</tt> CTB SCA_CTRL0 Register */ 101 __IO uint32_t sca_ctrl1; /**< <tt>\b 0x104:</tt> CTB SCA_CTRL1 Register */ 102 __IO uint32_t sca_stat; /**< <tt>\b 0x108:</tt> CTB SCA_STAT Register */ 103 __IO uint32_t sca_ppx_addr; /**< <tt>\b 0x10C:</tt> CTB SCA_PPX_ADDR Register */ 104 __IO uint32_t sca_ppy_addr; /**< <tt>\b 0x110:</tt> CTB SCA_PPY_ADDR Register */ 105 __IO uint32_t sca_ppz_addr; /**< <tt>\b 0x114:</tt> CTB SCA_PPZ_ADDR Register */ 106 __IO uint32_t sca_pqx_addr; /**< <tt>\b 0x118:</tt> CTB SCA_PQX_ADDR Register */ 107 __IO uint32_t sca_pqy_addr; /**< <tt>\b 0x11C:</tt> CTB SCA_PQY_ADDR Register */ 108 __IO uint32_t sca_pqz_addr; /**< <tt>\b 0x120:</tt> CTB SCA_PQZ_ADDR Register */ 109 __IO uint32_t sca_rdsa_addr; /**< <tt>\b 0x124:</tt> CTB SCA_RDSA_ADDR Register */ 110 __IO uint32_t sca_res_addr; /**< <tt>\b 0x128:</tt> CTB SCA_RES_ADDR Register */ 111 __IO uint32_t sca_op_buff_addr; /**< <tt>\b 0x12C:</tt> CTB SCA_OP_BUFF_ADDR Register */ 112 __IO uint32_t sca_moddata; /**< <tt>\b 0x130:</tt> CTB SCA_MODDATA Register */ 113 } mxc_ctb_regs_t; 114 115 /* Register offsets for module CTB */ 116 /** 117 * @ingroup ctb_registers 118 * @defgroup CTB_Register_Offsets Register Offsets 119 * @brief CTB Peripheral Register Offsets from the CTB Base Peripheral Address. 120 * @{ 121 */ 122 #define MXC_R_CTB_CRYPTO_CTRL ((uint32_t)0x00000000UL) /**< Offset from CTB Base Address: <tt> 0x0000</tt> */ 123 #define MXC_R_CTB_CIPHER_CTRL ((uint32_t)0x00000004UL) /**< Offset from CTB Base Address: <tt> 0x0004</tt> */ 124 #define MXC_R_CTB_HASH_CTRL ((uint32_t)0x00000008UL) /**< Offset from CTB Base Address: <tt> 0x0008</tt> */ 125 #define MXC_R_CTB_CRC_CTRL ((uint32_t)0x0000000CUL) /**< Offset from CTB Base Address: <tt> 0x000C</tt> */ 126 #define MXC_R_CTB_DMA_SRC ((uint32_t)0x00000010UL) /**< Offset from CTB Base Address: <tt> 0x0010</tt> */ 127 #define MXC_R_CTB_DMA_DEST ((uint32_t)0x00000014UL) /**< Offset from CTB Base Address: <tt> 0x0014</tt> */ 128 #define MXC_R_CTB_DMA_CNT ((uint32_t)0x00000018UL) /**< Offset from CTB Base Address: <tt> 0x0018</tt> */ 129 #define MXC_R_CTB_CRYPTO_DIN ((uint32_t)0x00000020UL) /**< Offset from CTB Base Address: <tt> 0x0020</tt> */ 130 #define MXC_R_CTB_CRYPTO_DOUT ((uint32_t)0x00000030UL) /**< Offset from CTB Base Address: <tt> 0x0030</tt> */ 131 #define MXC_R_CTB_CRC_POLY ((uint32_t)0x00000040UL) /**< Offset from CTB Base Address: <tt> 0x0040</tt> */ 132 #define MXC_R_CTB_CRC_VAL ((uint32_t)0x00000044UL) /**< Offset from CTB Base Address: <tt> 0x0044</tt> */ 133 #define MXC_R_CTB_HAM_ECC ((uint32_t)0x0000004CUL) /**< Offset from CTB Base Address: <tt> 0x004C</tt> */ 134 #define MXC_R_CTB_CIPHER_INIT ((uint32_t)0x00000050UL) /**< Offset from CTB Base Address: <tt> 0x0050</tt> */ 135 #define MXC_R_CTB_CIPHER_KEY ((uint32_t)0x00000060UL) /**< Offset from CTB Base Address: <tt> 0x0060</tt> */ 136 #define MXC_R_CTB_HASH_DIGEST ((uint32_t)0x00000080UL) /**< Offset from CTB Base Address: <tt> 0x0080</tt> */ 137 #define MXC_R_CTB_HASH_MSG_SZ ((uint32_t)0x000000C0UL) /**< Offset from CTB Base Address: <tt> 0x00C0</tt> */ 138 #define MXC_R_CTB_AAD_LENGTH_0 ((uint32_t)0x000000D0UL) /**< Offset from CTB Base Address: <tt> 0x00D0</tt> */ 139 #define MXC_R_CTB_AAD_LENGTH_1 ((uint32_t)0x000000D4UL) /**< Offset from CTB Base Address: <tt> 0x00D4</tt> */ 140 #define MXC_R_CTB_PLD_LENGTH_0 ((uint32_t)0x000000D8UL) /**< Offset from CTB Base Address: <tt> 0x00D8</tt> */ 141 #define MXC_R_CTB_PLD_LENGTH_1 ((uint32_t)0x000000DCUL) /**< Offset from CTB Base Address: <tt> 0x00DC</tt> */ 142 #define MXC_R_CTB_TAGMIC ((uint32_t)0x000000E0UL) /**< Offset from CTB Base Address: <tt> 0x00E0</tt> */ 143 #define MXC_R_CTB_SCA_CTRL0 ((uint32_t)0x00000100UL) /**< Offset from CTB Base Address: <tt> 0x0100</tt> */ 144 #define MXC_R_CTB_SCA_CTRL1 ((uint32_t)0x00000104UL) /**< Offset from CTB Base Address: <tt> 0x0104</tt> */ 145 #define MXC_R_CTB_SCA_STAT ((uint32_t)0x00000108UL) /**< Offset from CTB Base Address: <tt> 0x0108</tt> */ 146 #define MXC_R_CTB_SCA_PPX_ADDR ((uint32_t)0x0000010CUL) /**< Offset from CTB Base Address: <tt> 0x010C</tt> */ 147 #define MXC_R_CTB_SCA_PPY_ADDR ((uint32_t)0x00000110UL) /**< Offset from CTB Base Address: <tt> 0x0110</tt> */ 148 #define MXC_R_CTB_SCA_PPZ_ADDR ((uint32_t)0x00000114UL) /**< Offset from CTB Base Address: <tt> 0x0114</tt> */ 149 #define MXC_R_CTB_SCA_PQX_ADDR ((uint32_t)0x00000118UL) /**< Offset from CTB Base Address: <tt> 0x0118</tt> */ 150 #define MXC_R_CTB_SCA_PQY_ADDR ((uint32_t)0x0000011CUL) /**< Offset from CTB Base Address: <tt> 0x011C</tt> */ 151 #define MXC_R_CTB_SCA_PQZ_ADDR ((uint32_t)0x00000120UL) /**< Offset from CTB Base Address: <tt> 0x0120</tt> */ 152 #define MXC_R_CTB_SCA_RDSA_ADDR ((uint32_t)0x00000124UL) /**< Offset from CTB Base Address: <tt> 0x0124</tt> */ 153 #define MXC_R_CTB_SCA_RES_ADDR ((uint32_t)0x00000128UL) /**< Offset from CTB Base Address: <tt> 0x0128</tt> */ 154 #define MXC_R_CTB_SCA_OP_BUFF_ADDR ((uint32_t)0x0000012CUL) /**< Offset from CTB Base Address: <tt> 0x012C</tt> */ 155 #define MXC_R_CTB_SCA_MODDATA ((uint32_t)0x00000130UL) /**< Offset from CTB Base Address: <tt> 0x0130</tt> */ 156 /**@} end of group ctb_registers */ 157 158 /** 159 * @ingroup ctb_registers 160 * @defgroup CTB_CRYPTO_CTRL CTB_CRYPTO_CTRL 161 * @brief Crypto Control Register. 162 * @{ 163 */ 164 #define MXC_F_CTB_CRYPTO_CTRL_RST_POS 0 /**< CRYPTO_CTRL_RST Position */ 165 #define MXC_F_CTB_CRYPTO_CTRL_RST ((uint32_t)(0x1UL << MXC_F_CTB_CRYPTO_CTRL_RST_POS)) /**< CRYPTO_CTRL_RST Mask */ 166 167 #define MXC_F_CTB_CRYPTO_CTRL_INTR_POS 1 /**< CRYPTO_CTRL_INTR Position */ 168 #define MXC_F_CTB_CRYPTO_CTRL_INTR ((uint32_t)(0x1UL << MXC_F_CTB_CRYPTO_CTRL_INTR_POS)) /**< CRYPTO_CTRL_INTR Mask */ 169 170 #define MXC_F_CTB_CRYPTO_CTRL_SRC_POS 2 /**< CRYPTO_CTRL_SRC Position */ 171 #define MXC_F_CTB_CRYPTO_CTRL_SRC ((uint32_t)(0x1UL << MXC_F_CTB_CRYPTO_CTRL_SRC_POS)) /**< CRYPTO_CTRL_SRC Mask */ 172 173 #define MXC_F_CTB_CRYPTO_CTRL_BSO_POS 4 /**< CRYPTO_CTRL_BSO Position */ 174 #define MXC_F_CTB_CRYPTO_CTRL_BSO ((uint32_t)(0x1UL << MXC_F_CTB_CRYPTO_CTRL_BSO_POS)) /**< CRYPTO_CTRL_BSO Mask */ 175 176 #define MXC_F_CTB_CRYPTO_CTRL_BSI_POS 5 /**< CRYPTO_CTRL_BSI Position */ 177 #define MXC_F_CTB_CRYPTO_CTRL_BSI ((uint32_t)(0x1UL << MXC_F_CTB_CRYPTO_CTRL_BSI_POS)) /**< CRYPTO_CTRL_BSI Mask */ 178 179 #define MXC_F_CTB_CRYPTO_CTRL_WAIT_EN_POS 6 /**< CRYPTO_CTRL_WAIT_EN Position */ 180 #define MXC_F_CTB_CRYPTO_CTRL_WAIT_EN ((uint32_t)(0x1UL << MXC_F_CTB_CRYPTO_CTRL_WAIT_EN_POS)) /**< CRYPTO_CTRL_WAIT_EN Mask */ 181 182 #define MXC_F_CTB_CRYPTO_CTRL_WAIT_POL_POS 7 /**< CRYPTO_CTRL_WAIT_POL Position */ 183 #define MXC_F_CTB_CRYPTO_CTRL_WAIT_POL ((uint32_t)(0x1UL << MXC_F_CTB_CRYPTO_CTRL_WAIT_POL_POS)) /**< CRYPTO_CTRL_WAIT_POL Mask */ 184 185 #define MXC_F_CTB_CRYPTO_CTRL_WRSRC_POS 8 /**< CRYPTO_CTRL_WRSRC Position */ 186 #define MXC_F_CTB_CRYPTO_CTRL_WRSRC ((uint32_t)(0x3UL << MXC_F_CTB_CRYPTO_CTRL_WRSRC_POS)) /**< CRYPTO_CTRL_WRSRC Mask */ 187 #define MXC_V_CTB_CRYPTO_CTRL_WRSRC_NONE ((uint32_t)0x0UL) /**< CRYPTO_CTRL_WRSRC_NONE Value */ 188 #define MXC_S_CTB_CRYPTO_CTRL_WRSRC_NONE (MXC_V_CTB_CRYPTO_CTRL_WRSRC_NONE << MXC_F_CTB_CRYPTO_CTRL_WRSRC_POS) /**< CRYPTO_CTRL_WRSRC_NONE Setting */ 189 #define MXC_V_CTB_CRYPTO_CTRL_WRSRC_CIPHEROUTPUT ((uint32_t)0x1UL) /**< CRYPTO_CTRL_WRSRC_CIPHEROUTPUT Value */ 190 #define MXC_S_CTB_CRYPTO_CTRL_WRSRC_CIPHEROUTPUT (MXC_V_CTB_CRYPTO_CTRL_WRSRC_CIPHEROUTPUT << MXC_F_CTB_CRYPTO_CTRL_WRSRC_POS) /**< CRYPTO_CTRL_WRSRC_CIPHEROUTPUT Setting */ 191 #define MXC_V_CTB_CRYPTO_CTRL_WRSRC_READFIFO ((uint32_t)0x2UL) /**< CRYPTO_CTRL_WRSRC_READFIFO Value */ 192 #define MXC_S_CTB_CRYPTO_CTRL_WRSRC_READFIFO (MXC_V_CTB_CRYPTO_CTRL_WRSRC_READFIFO << MXC_F_CTB_CRYPTO_CTRL_WRSRC_POS) /**< CRYPTO_CTRL_WRSRC_READFIFO Setting */ 193 194 #define MXC_F_CTB_CRYPTO_CTRL_RDSRC_POS 10 /**< CRYPTO_CTRL_RDSRC Position */ 195 #define MXC_F_CTB_CRYPTO_CTRL_RDSRC ((uint32_t)(0x3UL << MXC_F_CTB_CRYPTO_CTRL_RDSRC_POS)) /**< CRYPTO_CTRL_RDSRC Mask */ 196 #define MXC_V_CTB_CRYPTO_CTRL_RDSRC_DMADISABLED ((uint32_t)0x0UL) /**< CRYPTO_CTRL_RDSRC_DMADISABLED Value */ 197 #define MXC_S_CTB_CRYPTO_CTRL_RDSRC_DMADISABLED (MXC_V_CTB_CRYPTO_CTRL_RDSRC_DMADISABLED << MXC_F_CTB_CRYPTO_CTRL_RDSRC_POS) /**< CRYPTO_CTRL_RDSRC_DMADISABLED Setting */ 198 #define MXC_V_CTB_CRYPTO_CTRL_RDSRC_DMAORAPB ((uint32_t)0x1UL) /**< CRYPTO_CTRL_RDSRC_DMAORAPB Value */ 199 #define MXC_S_CTB_CRYPTO_CTRL_RDSRC_DMAORAPB (MXC_V_CTB_CRYPTO_CTRL_RDSRC_DMAORAPB << MXC_F_CTB_CRYPTO_CTRL_RDSRC_POS) /**< CRYPTO_CTRL_RDSRC_DMAORAPB Setting */ 200 #define MXC_V_CTB_CRYPTO_CTRL_RDSRC_RNG ((uint32_t)0x2UL) /**< CRYPTO_CTRL_RDSRC_RNG Value */ 201 #define MXC_S_CTB_CRYPTO_CTRL_RDSRC_RNG (MXC_V_CTB_CRYPTO_CTRL_RDSRC_RNG << MXC_F_CTB_CRYPTO_CTRL_RDSRC_POS) /**< CRYPTO_CTRL_RDSRC_RNG Setting */ 202 203 #define MXC_F_CTB_CRYPTO_CTRL_FLAG_MODE_POS 14 /**< CRYPTO_CTRL_FLAG_MODE Position */ 204 #define MXC_F_CTB_CRYPTO_CTRL_FLAG_MODE ((uint32_t)(0x1UL << MXC_F_CTB_CRYPTO_CTRL_FLAG_MODE_POS)) /**< CRYPTO_CTRL_FLAG_MODE Mask */ 205 206 #define MXC_F_CTB_CRYPTO_CTRL_DMADNEMSK_POS 15 /**< CRYPTO_CTRL_DMADNEMSK Position */ 207 #define MXC_F_CTB_CRYPTO_CTRL_DMADNEMSK ((uint32_t)(0x1UL << MXC_F_CTB_CRYPTO_CTRL_DMADNEMSK_POS)) /**< CRYPTO_CTRL_DMADNEMSK Mask */ 208 209 #define MXC_F_CTB_CRYPTO_CTRL_DMA_DONE_POS 24 /**< CRYPTO_CTRL_DMA_DONE Position */ 210 #define MXC_F_CTB_CRYPTO_CTRL_DMA_DONE ((uint32_t)(0x1UL << MXC_F_CTB_CRYPTO_CTRL_DMA_DONE_POS)) /**< CRYPTO_CTRL_DMA_DONE Mask */ 211 212 #define MXC_F_CTB_CRYPTO_CTRL_GLS_DONE_POS 25 /**< CRYPTO_CTRL_GLS_DONE Position */ 213 #define MXC_F_CTB_CRYPTO_CTRL_GLS_DONE ((uint32_t)(0x1UL << MXC_F_CTB_CRYPTO_CTRL_GLS_DONE_POS)) /**< CRYPTO_CTRL_GLS_DONE Mask */ 214 215 #define MXC_F_CTB_CRYPTO_CTRL_HSH_DONE_POS 26 /**< CRYPTO_CTRL_HSH_DONE Position */ 216 #define MXC_F_CTB_CRYPTO_CTRL_HSH_DONE ((uint32_t)(0x1UL << MXC_F_CTB_CRYPTO_CTRL_HSH_DONE_POS)) /**< CRYPTO_CTRL_HSH_DONE Mask */ 217 218 #define MXC_F_CTB_CRYPTO_CTRL_CPH_DONE_POS 27 /**< CRYPTO_CTRL_CPH_DONE Position */ 219 #define MXC_F_CTB_CRYPTO_CTRL_CPH_DONE ((uint32_t)(0x1UL << MXC_F_CTB_CRYPTO_CTRL_CPH_DONE_POS)) /**< CRYPTO_CTRL_CPH_DONE Mask */ 220 221 #define MXC_F_CTB_CRYPTO_CTRL_ERR_POS 29 /**< CRYPTO_CTRL_ERR Position */ 222 #define MXC_F_CTB_CRYPTO_CTRL_ERR ((uint32_t)(0x1UL << MXC_F_CTB_CRYPTO_CTRL_ERR_POS)) /**< CRYPTO_CTRL_ERR Mask */ 223 224 #define MXC_F_CTB_CRYPTO_CTRL_RDY_POS 30 /**< CRYPTO_CTRL_RDY Position */ 225 #define MXC_F_CTB_CRYPTO_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_CTB_CRYPTO_CTRL_RDY_POS)) /**< CRYPTO_CTRL_RDY Mask */ 226 227 #define MXC_F_CTB_CRYPTO_CTRL_DONE_POS 31 /**< CRYPTO_CTRL_DONE Position */ 228 #define MXC_F_CTB_CRYPTO_CTRL_DONE ((uint32_t)(0x1UL << MXC_F_CTB_CRYPTO_CTRL_DONE_POS)) /**< CRYPTO_CTRL_DONE Mask */ 229 230 /**@} end of group CTB_CRYPTO_CTRL_Register */ 231 232 /** 233 * @ingroup ctb_registers 234 * @defgroup CTB_CIPHER_CTRL CTB_CIPHER_CTRL 235 * @brief Cipher Control Register. 236 * @{ 237 */ 238 #define MXC_F_CTB_CIPHER_CTRL_ENC_POS 0 /**< CIPHER_CTRL_ENC Position */ 239 #define MXC_F_CTB_CIPHER_CTRL_ENC ((uint32_t)(0x1UL << MXC_F_CTB_CIPHER_CTRL_ENC_POS)) /**< CIPHER_CTRL_ENC Mask */ 240 241 #define MXC_F_CTB_CIPHER_CTRL_KEY_POS 1 /**< CIPHER_CTRL_KEY Position */ 242 #define MXC_F_CTB_CIPHER_CTRL_KEY ((uint32_t)(0x1UL << MXC_F_CTB_CIPHER_CTRL_KEY_POS)) /**< CIPHER_CTRL_KEY Mask */ 243 244 #define MXC_F_CTB_CIPHER_CTRL_SRC_POS 2 /**< CIPHER_CTRL_SRC Position */ 245 #define MXC_F_CTB_CIPHER_CTRL_SRC ((uint32_t)(0x3UL << MXC_F_CTB_CIPHER_CTRL_SRC_POS)) /**< CIPHER_CTRL_SRC Mask */ 246 #define MXC_V_CTB_CIPHER_CTRL_SRC_CIPHERKEY ((uint32_t)0x0UL) /**< CIPHER_CTRL_SRC_CIPHERKEY Value */ 247 #define MXC_S_CTB_CIPHER_CTRL_SRC_CIPHERKEY (MXC_V_CTB_CIPHER_CTRL_SRC_CIPHERKEY << MXC_F_CTB_CIPHER_CTRL_SRC_POS) /**< CIPHER_CTRL_SRC_CIPHERKEY Setting */ 248 #define MXC_V_CTB_CIPHER_CTRL_SRC_REGFILE ((uint32_t)0x2UL) /**< CIPHER_CTRL_SRC_REGFILE Value */ 249 #define MXC_S_CTB_CIPHER_CTRL_SRC_REGFILE (MXC_V_CTB_CIPHER_CTRL_SRC_REGFILE << MXC_F_CTB_CIPHER_CTRL_SRC_POS) /**< CIPHER_CTRL_SRC_REGFILE Setting */ 250 #define MXC_V_CTB_CIPHER_CTRL_SRC_QSPIKEY_REGFILE ((uint32_t)0x3UL) /**< CIPHER_CTRL_SRC_QSPIKEY_REGFILE Value */ 251 #define MXC_S_CTB_CIPHER_CTRL_SRC_QSPIKEY_REGFILE (MXC_V_CTB_CIPHER_CTRL_SRC_QSPIKEY_REGFILE << MXC_F_CTB_CIPHER_CTRL_SRC_POS) /**< CIPHER_CTRL_SRC_QSPIKEY_REGFILE Setting */ 252 253 #define MXC_F_CTB_CIPHER_CTRL_CIPHER_POS 4 /**< CIPHER_CTRL_CIPHER Position */ 254 #define MXC_F_CTB_CIPHER_CTRL_CIPHER ((uint32_t)(0x7UL << MXC_F_CTB_CIPHER_CTRL_CIPHER_POS)) /**< CIPHER_CTRL_CIPHER Mask */ 255 #define MXC_V_CTB_CIPHER_CTRL_CIPHER_DIS ((uint32_t)0x0UL) /**< CIPHER_CTRL_CIPHER_DIS Value */ 256 #define MXC_S_CTB_CIPHER_CTRL_CIPHER_DIS (MXC_V_CTB_CIPHER_CTRL_CIPHER_DIS << MXC_F_CTB_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_DIS Setting */ 257 #define MXC_V_CTB_CIPHER_CTRL_CIPHER_AES128 ((uint32_t)0x1UL) /**< CIPHER_CTRL_CIPHER_AES128 Value */ 258 #define MXC_S_CTB_CIPHER_CTRL_CIPHER_AES128 (MXC_V_CTB_CIPHER_CTRL_CIPHER_AES128 << MXC_F_CTB_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_AES128 Setting */ 259 #define MXC_V_CTB_CIPHER_CTRL_CIPHER_AES192 ((uint32_t)0x2UL) /**< CIPHER_CTRL_CIPHER_AES192 Value */ 260 #define MXC_S_CTB_CIPHER_CTRL_CIPHER_AES192 (MXC_V_CTB_CIPHER_CTRL_CIPHER_AES192 << MXC_F_CTB_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_AES192 Setting */ 261 #define MXC_V_CTB_CIPHER_CTRL_CIPHER_AES256 ((uint32_t)0x3UL) /**< CIPHER_CTRL_CIPHER_AES256 Value */ 262 #define MXC_S_CTB_CIPHER_CTRL_CIPHER_AES256 (MXC_V_CTB_CIPHER_CTRL_CIPHER_AES256 << MXC_F_CTB_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_AES256 Setting */ 263 #define MXC_V_CTB_CIPHER_CTRL_CIPHER_DES ((uint32_t)0x4UL) /**< CIPHER_CTRL_CIPHER_DES Value */ 264 #define MXC_S_CTB_CIPHER_CTRL_CIPHER_DES (MXC_V_CTB_CIPHER_CTRL_CIPHER_DES << MXC_F_CTB_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_DES Setting */ 265 #define MXC_V_CTB_CIPHER_CTRL_CIPHER_TDES ((uint32_t)0x5UL) /**< CIPHER_CTRL_CIPHER_TDES Value */ 266 #define MXC_S_CTB_CIPHER_CTRL_CIPHER_TDES (MXC_V_CTB_CIPHER_CTRL_CIPHER_TDES << MXC_F_CTB_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_TDES Setting */ 267 268 #define MXC_F_CTB_CIPHER_CTRL_MODE_POS 8 /**< CIPHER_CTRL_MODE Position */ 269 #define MXC_F_CTB_CIPHER_CTRL_MODE ((uint32_t)(0x7UL << MXC_F_CTB_CIPHER_CTRL_MODE_POS)) /**< CIPHER_CTRL_MODE Mask */ 270 #define MXC_V_CTB_CIPHER_CTRL_MODE_ECB ((uint32_t)0x0UL) /**< CIPHER_CTRL_MODE_ECB Value */ 271 #define MXC_S_CTB_CIPHER_CTRL_MODE_ECB (MXC_V_CTB_CIPHER_CTRL_MODE_ECB << MXC_F_CTB_CIPHER_CTRL_MODE_POS) /**< CIPHER_CTRL_MODE_ECB Setting */ 272 #define MXC_V_CTB_CIPHER_CTRL_MODE_CBC ((uint32_t)0x1UL) /**< CIPHER_CTRL_MODE_CBC Value */ 273 #define MXC_S_CTB_CIPHER_CTRL_MODE_CBC (MXC_V_CTB_CIPHER_CTRL_MODE_CBC << MXC_F_CTB_CIPHER_CTRL_MODE_POS) /**< CIPHER_CTRL_MODE_CBC Setting */ 274 #define MXC_V_CTB_CIPHER_CTRL_MODE_CFB ((uint32_t)0x2UL) /**< CIPHER_CTRL_MODE_CFB Value */ 275 #define MXC_S_CTB_CIPHER_CTRL_MODE_CFB (MXC_V_CTB_CIPHER_CTRL_MODE_CFB << MXC_F_CTB_CIPHER_CTRL_MODE_POS) /**< CIPHER_CTRL_MODE_CFB Setting */ 276 #define MXC_V_CTB_CIPHER_CTRL_MODE_OFB ((uint32_t)0x3UL) /**< CIPHER_CTRL_MODE_OFB Value */ 277 #define MXC_S_CTB_CIPHER_CTRL_MODE_OFB (MXC_V_CTB_CIPHER_CTRL_MODE_OFB << MXC_F_CTB_CIPHER_CTRL_MODE_POS) /**< CIPHER_CTRL_MODE_OFB Setting */ 278 #define MXC_V_CTB_CIPHER_CTRL_MODE_CTR ((uint32_t)0x4UL) /**< CIPHER_CTRL_MODE_CTR Value */ 279 #define MXC_S_CTB_CIPHER_CTRL_MODE_CTR (MXC_V_CTB_CIPHER_CTRL_MODE_CTR << MXC_F_CTB_CIPHER_CTRL_MODE_POS) /**< CIPHER_CTRL_MODE_CTR Setting */ 280 281 #define MXC_F_CTB_CIPHER_CTRL_HVC_POS 11 /**< CIPHER_CTRL_HVC Position */ 282 #define MXC_F_CTB_CIPHER_CTRL_HVC ((uint32_t)(0x1UL << MXC_F_CTB_CIPHER_CTRL_HVC_POS)) /**< CIPHER_CTRL_HVC Mask */ 283 284 #define MXC_F_CTB_CIPHER_CTRL_DTYPE_POS 12 /**< CIPHER_CTRL_DTYPE Position */ 285 #define MXC_F_CTB_CIPHER_CTRL_DTYPE ((uint32_t)(0x1UL << MXC_F_CTB_CIPHER_CTRL_DTYPE_POS)) /**< CIPHER_CTRL_DTYPE Mask */ 286 287 #define MXC_F_CTB_CIPHER_CTRL_CCMM_POS 13 /**< CIPHER_CTRL_CCMM Position */ 288 #define MXC_F_CTB_CIPHER_CTRL_CCMM ((uint32_t)(0x7UL << MXC_F_CTB_CIPHER_CTRL_CCMM_POS)) /**< CIPHER_CTRL_CCMM Mask */ 289 290 #define MXC_F_CTB_CIPHER_CTRL_CCML_POS 16 /**< CIPHER_CTRL_CCML Position */ 291 #define MXC_F_CTB_CIPHER_CTRL_CCML ((uint32_t)(0x7UL << MXC_F_CTB_CIPHER_CTRL_CCML_POS)) /**< CIPHER_CTRL_CCML Mask */ 292 293 /**@} end of group CTB_CIPHER_CTRL_Register */ 294 295 /** 296 * @ingroup ctb_registers 297 * @defgroup CTB_HASH_CTRL CTB_HASH_CTRL 298 * @brief HASH Control Register. 299 * @{ 300 */ 301 #define MXC_F_CTB_HASH_CTRL_INIT_POS 0 /**< HASH_CTRL_INIT Position */ 302 #define MXC_F_CTB_HASH_CTRL_INIT ((uint32_t)(0x1UL << MXC_F_CTB_HASH_CTRL_INIT_POS)) /**< HASH_CTRL_INIT Mask */ 303 304 #define MXC_F_CTB_HASH_CTRL_XOR_POS 1 /**< HASH_CTRL_XOR Position */ 305 #define MXC_F_CTB_HASH_CTRL_XOR ((uint32_t)(0x1UL << MXC_F_CTB_HASH_CTRL_XOR_POS)) /**< HASH_CTRL_XOR Mask */ 306 307 #define MXC_F_CTB_HASH_CTRL_HASH_POS 2 /**< HASH_CTRL_HASH Position */ 308 #define MXC_F_CTB_HASH_CTRL_HASH ((uint32_t)(0x7UL << MXC_F_CTB_HASH_CTRL_HASH_POS)) /**< HASH_CTRL_HASH Mask */ 309 #define MXC_V_CTB_HASH_CTRL_HASH_DIS ((uint32_t)0x0UL) /**< HASH_CTRL_HASH_DIS Value */ 310 #define MXC_S_CTB_HASH_CTRL_HASH_DIS (MXC_V_CTB_HASH_CTRL_HASH_DIS << MXC_F_CTB_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_DIS Setting */ 311 #define MXC_V_CTB_HASH_CTRL_HASH_SHA1 ((uint32_t)0x1UL) /**< HASH_CTRL_HASH_SHA1 Value */ 312 #define MXC_S_CTB_HASH_CTRL_HASH_SHA1 (MXC_V_CTB_HASH_CTRL_HASH_SHA1 << MXC_F_CTB_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_SHA1 Setting */ 313 #define MXC_V_CTB_HASH_CTRL_HASH_SHA224 ((uint32_t)0x2UL) /**< HASH_CTRL_HASH_SHA224 Value */ 314 #define MXC_S_CTB_HASH_CTRL_HASH_SHA224 (MXC_V_CTB_HASH_CTRL_HASH_SHA224 << MXC_F_CTB_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_SHA224 Setting */ 315 #define MXC_V_CTB_HASH_CTRL_HASH_SHA256 ((uint32_t)0x3UL) /**< HASH_CTRL_HASH_SHA256 Value */ 316 #define MXC_S_CTB_HASH_CTRL_HASH_SHA256 (MXC_V_CTB_HASH_CTRL_HASH_SHA256 << MXC_F_CTB_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_SHA256 Setting */ 317 #define MXC_V_CTB_HASH_CTRL_HASH_SHA384 ((uint32_t)0x4UL) /**< HASH_CTRL_HASH_SHA384 Value */ 318 #define MXC_S_CTB_HASH_CTRL_HASH_SHA384 (MXC_V_CTB_HASH_CTRL_HASH_SHA384 << MXC_F_CTB_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_SHA384 Setting */ 319 #define MXC_V_CTB_HASH_CTRL_HASH_SHA512 ((uint32_t)0x5UL) /**< HASH_CTRL_HASH_SHA512 Value */ 320 #define MXC_S_CTB_HASH_CTRL_HASH_SHA512 (MXC_V_CTB_HASH_CTRL_HASH_SHA512 << MXC_F_CTB_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_SHA512 Setting */ 321 322 #define MXC_F_CTB_HASH_CTRL_LAST_POS 5 /**< HASH_CTRL_LAST Position */ 323 #define MXC_F_CTB_HASH_CTRL_LAST ((uint32_t)(0x1UL << MXC_F_CTB_HASH_CTRL_LAST_POS)) /**< HASH_CTRL_LAST Mask */ 324 325 /**@} end of group CTB_HASH_CTRL_Register */ 326 327 /** 328 * @ingroup ctb_registers 329 * @defgroup CTB_CRC_CTRL CTB_CRC_CTRL 330 * @brief CRC Control Register. 331 * @{ 332 */ 333 #define MXC_F_CTB_CRC_CTRL_CRC_POS 0 /**< CRC_CTRL_CRC Position */ 334 #define MXC_F_CTB_CRC_CTRL_CRC ((uint32_t)(0x1UL << MXC_F_CTB_CRC_CTRL_CRC_POS)) /**< CRC_CTRL_CRC Mask */ 335 336 #define MXC_F_CTB_CRC_CTRL_MSB_POS 1 /**< CRC_CTRL_MSB Position */ 337 #define MXC_F_CTB_CRC_CTRL_MSB ((uint32_t)(0x1UL << MXC_F_CTB_CRC_CTRL_MSB_POS)) /**< CRC_CTRL_MSB Mask */ 338 339 #define MXC_F_CTB_CRC_CTRL_PRNG_POS 2 /**< CRC_CTRL_PRNG Position */ 340 #define MXC_F_CTB_CRC_CTRL_PRNG ((uint32_t)(0x1UL << MXC_F_CTB_CRC_CTRL_PRNG_POS)) /**< CRC_CTRL_PRNG Mask */ 341 342 #define MXC_F_CTB_CRC_CTRL_ENT_POS 3 /**< CRC_CTRL_ENT Position */ 343 #define MXC_F_CTB_CRC_CTRL_ENT ((uint32_t)(0x1UL << MXC_F_CTB_CRC_CTRL_ENT_POS)) /**< CRC_CTRL_ENT Mask */ 344 345 #define MXC_F_CTB_CRC_CTRL_HAM_POS 4 /**< CRC_CTRL_HAM Position */ 346 #define MXC_F_CTB_CRC_CTRL_HAM ((uint32_t)(0x1UL << MXC_F_CTB_CRC_CTRL_HAM_POS)) /**< CRC_CTRL_HAM Mask */ 347 348 #define MXC_F_CTB_CRC_CTRL_HRST_POS 5 /**< CRC_CTRL_HRST Position */ 349 #define MXC_F_CTB_CRC_CTRL_HRST ((uint32_t)(0x1UL << MXC_F_CTB_CRC_CTRL_HRST_POS)) /**< CRC_CTRL_HRST Mask */ 350 351 /**@} end of group CTB_CRC_CTRL_Register */ 352 353 /** 354 * @ingroup ctb_registers 355 * @defgroup CTB_DMA_SRC CTB_DMA_SRC 356 * @brief Crypto DMA Source Address. 357 * @{ 358 */ 359 #define MXC_F_CTB_DMA_SRC_ADDR_POS 0 /**< DMA_SRC_ADDR Position */ 360 #define MXC_F_CTB_DMA_SRC_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_DMA_SRC_ADDR_POS)) /**< DMA_SRC_ADDR Mask */ 361 362 /**@} end of group CTB_DMA_SRC_Register */ 363 364 /** 365 * @ingroup ctb_registers 366 * @defgroup CTB_DMA_DEST CTB_DMA_DEST 367 * @brief Crypto DMA Destination Address. 368 * @{ 369 */ 370 #define MXC_F_CTB_DMA_DEST_ADDR_POS 0 /**< DMA_DEST_ADDR Position */ 371 #define MXC_F_CTB_DMA_DEST_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_DMA_DEST_ADDR_POS)) /**< DMA_DEST_ADDR Mask */ 372 373 /**@} end of group CTB_DMA_DEST_Register */ 374 375 /** 376 * @ingroup ctb_registers 377 * @defgroup CTB_DMA_CNT CTB_DMA_CNT 378 * @brief Crypto DMA Byte Count. 379 * @{ 380 */ 381 #define MXC_F_CTB_DMA_CNT_COUNT_POS 0 /**< DMA_CNT_COUNT Position */ 382 #define MXC_F_CTB_DMA_CNT_COUNT ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_DMA_CNT_COUNT_POS)) /**< DMA_CNT_COUNT Mask */ 383 384 /**@} end of group CTB_DMA_CNT_Register */ 385 386 /** 387 * @ingroup ctb_registers 388 * @defgroup CTB_CRYPTO_DIN CTB_CRYPTO_DIN 389 * @brief Crypto Data Input. Data input can be written to this register instead of using 390 * the DMA. This register writes to the FIFO. This register occupies four 391 * successive words to allow the use of multi-store instructions. Words can be 392 * written to any location, they will be placed in the FIFO in the order they are 393 * written. The endian swap input control bit affects this register. 394 * @{ 395 */ 396 #define MXC_F_CTB_CRYPTO_DIN_DATA_POS 0 /**< CRYPTO_DIN_DATA Position */ 397 #define MXC_F_CTB_CRYPTO_DIN_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_CRYPTO_DIN_DATA_POS)) /**< CRYPTO_DIN_DATA Mask */ 398 399 /**@} end of group CTB_CRYPTO_DIN_Register */ 400 401 /** 402 * @ingroup ctb_registers 403 * @defgroup CTB_CRYPTO_DOUT CTB_CRYPTO_DOUT 404 * @brief Crypto Data Output. Resulting data from cipher calculation. Data is placed in 405 * the lower words of these four registers depending on the algorithm. For block 406 * cipher modes, this register holds the result of most recent encryption or 407 * decryption operation. These registers are affected by the endian swap bits. 408 * @{ 409 */ 410 #define MXC_F_CTB_CRYPTO_DOUT_DATA_POS 0 /**< CRYPTO_DOUT_DATA Position */ 411 #define MXC_F_CTB_CRYPTO_DOUT_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_CRYPTO_DOUT_DATA_POS)) /**< CRYPTO_DOUT_DATA Mask */ 412 413 /**@} end of group CTB_CRYPTO_DOUT_Register */ 414 415 /** 416 * @ingroup ctb_registers 417 * @defgroup CTB_CRC_POLY CTB_CRC_POLY 418 * @brief CRC Polynomial. The polynomial to be used for Galois Field calculations (CRC or 419 * LFSR) should be written to this register. This register is affected by the MSB 420 * control bit. 421 * @{ 422 */ 423 #define MXC_F_CTB_CRC_POLY_DATA_POS 0 /**< CRC_POLY_DATA Position */ 424 #define MXC_F_CTB_CRC_POLY_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_CRC_POLY_DATA_POS)) /**< CRC_POLY_DATA Mask */ 425 426 /**@} end of group CTB_CRC_POLY_Register */ 427 428 /** 429 * @ingroup ctb_registers 430 * @defgroup CTB_CRC_VAL CTB_CRC_VAL 431 * @brief CRC Value. This is the state for the Galois Field. This register holds the 432 * result of a CRC calculation or the current state of the LFSR. This register is 433 * affected by the MSB control bit. 434 * @{ 435 */ 436 #define MXC_F_CTB_CRC_VAL_VAL_POS 0 /**< CRC_VAL_VAL Position */ 437 #define MXC_F_CTB_CRC_VAL_VAL ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_CRC_VAL_VAL_POS)) /**< CRC_VAL_VAL Mask */ 438 439 /**@} end of group CTB_CRC_VAL_Register */ 440 441 /** 442 * @ingroup ctb_registers 443 * @defgroup CTB_HAM_ECC CTB_HAM_ECC 444 * @brief Hamming ECC Register. 445 * @{ 446 */ 447 #define MXC_F_CTB_HAM_ECC_ECC_POS 0 /**< HAM_ECC_ECC Position */ 448 #define MXC_F_CTB_HAM_ECC_ECC ((uint32_t)(0xFFFFUL << MXC_F_CTB_HAM_ECC_ECC_POS)) /**< HAM_ECC_ECC Mask */ 449 450 #define MXC_F_CTB_HAM_ECC_PAR_POS 16 /**< HAM_ECC_PAR Position */ 451 #define MXC_F_CTB_HAM_ECC_PAR ((uint32_t)(0x1UL << MXC_F_CTB_HAM_ECC_PAR_POS)) /**< HAM_ECC_PAR Mask */ 452 453 /**@} end of group CTB_HAM_ECC_Register */ 454 455 /** 456 * @ingroup ctb_registers 457 * @defgroup CTB_CIPHER_INIT CTB_CIPHER_INIT 458 * @brief Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR 459 * modes, this register holds the initial value. This register is updated with each 460 * encryption or decryption operation. This register is affected by the endian swap 461 * bits. 462 * @{ 463 */ 464 #define MXC_F_CTB_CIPHER_INIT_IVEC_POS 0 /**< CIPHER_INIT_IVEC Position */ 465 #define MXC_F_CTB_CIPHER_INIT_IVEC ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_CIPHER_INIT_IVEC_POS)) /**< CIPHER_INIT_IVEC Mask */ 466 467 /**@} end of group CTB_CIPHER_INIT_Register */ 468 469 /** 470 * @ingroup ctb_registers 471 * @defgroup CTB_CIPHER_KEY CTB_CIPHER_KEY 472 * @brief Cipher Key. This register holds the key used for block cipher operations. The 473 * lower words are used for block ciphers that use shorter key lengths. This 474 * register is affected by the endian swap input control bits. 475 * @{ 476 */ 477 #define MXC_F_CTB_CIPHER_KEY_KEY_POS 0 /**< CIPHER_KEY_KEY Position */ 478 #define MXC_F_CTB_CIPHER_KEY_KEY ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_CIPHER_KEY_KEY_POS)) /**< CIPHER_KEY_KEY Mask */ 479 480 /**@} end of group CTB_CIPHER_KEY_Register */ 481 482 /** 483 * @ingroup ctb_registers 484 * @defgroup CTB_HASH_DIGEST CTB_HASH_DIGEST 485 * @brief This register holds the calculated hash value. This register is affected by the 486 * endian swap bits. 487 * @{ 488 */ 489 #define MXC_F_CTB_HASH_DIGEST_HASH_POS 0 /**< HASH_DIGEST_HASH Position */ 490 #define MXC_F_CTB_HASH_DIGEST_HASH ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_HASH_DIGEST_HASH_POS)) /**< HASH_DIGEST_HASH Mask */ 491 492 /**@} end of group CTB_HASH_DIGEST_Register */ 493 494 /** 495 * @ingroup ctb_registers 496 * @defgroup CTB_HASH_MSG_SZ CTB_HASH_MSG_SZ 497 * @brief Message Size. This register holds the lowest 32-bit of message size in bytes. 498 * @{ 499 */ 500 #define MXC_F_CTB_HASH_MSG_SZ_MSGSZ_POS 0 /**< HASH_MSG_SZ_MSGSZ Position */ 501 #define MXC_F_CTB_HASH_MSG_SZ_MSGSZ ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_HASH_MSG_SZ_MSGSZ_POS)) /**< HASH_MSG_SZ_MSGSZ Mask */ 502 503 /**@} end of group CTB_HASH_MSG_SZ_Register */ 504 505 /** 506 * @ingroup ctb_registers 507 * @defgroup CTB_AAD_LENGTH_0 CTB_AAD_LENGTH_0 508 * @brief .AAD Length Register 0. 509 * @{ 510 */ 511 #define MXC_F_CTB_AAD_LENGTH_0_LENGTH_POS 0 /**< AAD_LENGTH_0_LENGTH Position */ 512 #define MXC_F_CTB_AAD_LENGTH_0_LENGTH ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_AAD_LENGTH_0_LENGTH_POS)) /**< AAD_LENGTH_0_LENGTH Mask */ 513 514 /**@} end of group CTB_AAD_LENGTH_0_Register */ 515 516 /** 517 * @ingroup ctb_registers 518 * @defgroup CTB_AAD_LENGTH_1 CTB_AAD_LENGTH_1 519 * @brief .AAD Length Register 1. 520 * @{ 521 */ 522 #define MXC_F_CTB_AAD_LENGTH_1_LENGTH_POS 0 /**< AAD_LENGTH_1_LENGTH Position */ 523 #define MXC_F_CTB_AAD_LENGTH_1_LENGTH ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_AAD_LENGTH_1_LENGTH_POS)) /**< AAD_LENGTH_1_LENGTH Mask */ 524 525 /**@} end of group CTB_AAD_LENGTH_1_Register */ 526 527 /** 528 * @ingroup ctb_registers 529 * @defgroup CTB_PLD_LENGTH_0 CTB_PLD_LENGTH_0 530 * @brief .PLD Length Register 0. 531 * @{ 532 */ 533 #define MXC_F_CTB_PLD_LENGTH_0_LENGTH_POS 0 /**< PLD_LENGTH_0_LENGTH Position */ 534 #define MXC_F_CTB_PLD_LENGTH_0_LENGTH ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_PLD_LENGTH_0_LENGTH_POS)) /**< PLD_LENGTH_0_LENGTH Mask */ 535 536 /**@} end of group CTB_PLD_LENGTH_0_Register */ 537 538 /** 539 * @ingroup ctb_registers 540 * @defgroup CTB_PLD_LENGTH_1 CTB_PLD_LENGTH_1 541 * @brief .LENGTH. 542 * @{ 543 */ 544 #define MXC_F_CTB_PLD_LENGTH_1_LENGTH_POS 0 /**< PLD_LENGTH_1_LENGTH Position */ 545 #define MXC_F_CTB_PLD_LENGTH_1_LENGTH ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_PLD_LENGTH_1_LENGTH_POS)) /**< PLD_LENGTH_1_LENGTH Mask */ 546 547 /**@} end of group CTB_PLD_LENGTH_1_Register */ 548 549 /** 550 * @ingroup ctb_registers 551 * @defgroup CTB_TAGMIC CTB_TAGMIC 552 * @brief TAG/MIC Registers. 553 * @{ 554 */ 555 #define MXC_F_CTB_TAGMIC_LENGTH_POS 0 /**< TAGMIC_LENGTH Position */ 556 #define MXC_F_CTB_TAGMIC_LENGTH ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_TAGMIC_LENGTH_POS)) /**< TAGMIC_LENGTH Mask */ 557 558 /**@} end of group CTB_TAGMIC_Register */ 559 560 /** 561 * @ingroup ctb_registers 562 * @defgroup CTB_SCA_CTRL0 CTB_SCA_CTRL0 563 * @brief SCA Control 0 Register. 564 * @{ 565 */ 566 #define MXC_F_CTB_SCA_CTRL0_STC_POS 0 /**< SCA_CTRL0_STC Position */ 567 #define MXC_F_CTB_SCA_CTRL0_STC ((uint32_t)(0x1UL << MXC_F_CTB_SCA_CTRL0_STC_POS)) /**< SCA_CTRL0_STC Mask */ 568 569 #define MXC_F_CTB_SCA_CTRL0_SCAIE_POS 1 /**< SCA_CTRL0_SCAIE Position */ 570 #define MXC_F_CTB_SCA_CTRL0_SCAIE ((uint32_t)(0x1UL << MXC_F_CTB_SCA_CTRL0_SCAIE_POS)) /**< SCA_CTRL0_SCAIE Mask */ 571 572 #define MXC_F_CTB_SCA_CTRL0_ABORT_POS 2 /**< SCA_CTRL0_ABORT Position */ 573 #define MXC_F_CTB_SCA_CTRL0_ABORT ((uint32_t)(0x1UL << MXC_F_CTB_SCA_CTRL0_ABORT_POS)) /**< SCA_CTRL0_ABORT Mask */ 574 575 #define MXC_F_CTB_SCA_CTRL0_ERMEM_POS 4 /**< SCA_CTRL0_ERMEM Position */ 576 #define MXC_F_CTB_SCA_CTRL0_ERMEM ((uint32_t)(0x1UL << MXC_F_CTB_SCA_CTRL0_ERMEM_POS)) /**< SCA_CTRL0_ERMEM Mask */ 577 578 #define MXC_F_CTB_SCA_CTRL0_MANPARAM_POS 5 /**< SCA_CTRL0_MANPARAM Position */ 579 #define MXC_F_CTB_SCA_CTRL0_MANPARAM ((uint32_t)(0x1UL << MXC_F_CTB_SCA_CTRL0_MANPARAM_POS)) /**< SCA_CTRL0_MANPARAM Mask */ 580 581 #define MXC_F_CTB_SCA_CTRL0_HWKEY_POS 6 /**< SCA_CTRL0_HWKEY Position */ 582 #define MXC_F_CTB_SCA_CTRL0_HWKEY ((uint32_t)(0x1UL << MXC_F_CTB_SCA_CTRL0_HWKEY_POS)) /**< SCA_CTRL0_HWKEY Mask */ 583 584 #define MXC_F_CTB_SCA_CTRL0_OPCODE_POS 8 /**< SCA_CTRL0_OPCODE Position */ 585 #define MXC_F_CTB_SCA_CTRL0_OPCODE ((uint32_t)(0x1FUL << MXC_F_CTB_SCA_CTRL0_OPCODE_POS)) /**< SCA_CTRL0_OPCODE Mask */ 586 587 #define MXC_F_CTB_SCA_CTRL0_MODADDR_POS 16 /**< SCA_CTRL0_MODADDR Position */ 588 #define MXC_F_CTB_SCA_CTRL0_MODADDR ((uint32_t)(0x1FUL << MXC_F_CTB_SCA_CTRL0_MODADDR_POS)) /**< SCA_CTRL0_MODADDR Mask */ 589 590 #define MXC_F_CTB_SCA_CTRL0_ECCSIZE_POS 24 /**< SCA_CTRL0_ECCSIZE Position */ 591 #define MXC_F_CTB_SCA_CTRL0_ECCSIZE ((uint32_t)(0x3UL << MXC_F_CTB_SCA_CTRL0_ECCSIZE_POS)) /**< SCA_CTRL0_ECCSIZE Mask */ 592 593 /**@} end of group CTB_SCA_CTRL0_Register */ 594 595 /** 596 * @ingroup ctb_registers 597 * @defgroup CTB_SCA_CTRL1 CTB_SCA_CTRL1 598 * @brief SCA Advanced Control Register. 599 * @{ 600 */ 601 #define MXC_F_CTB_SCA_CTRL1_MAN_POS 0 /**< SCA_CTRL1_MAN Position */ 602 #define MXC_F_CTB_SCA_CTRL1_MAN ((uint32_t)(0x1UL << MXC_F_CTB_SCA_CTRL1_MAN_POS)) /**< SCA_CTRL1_MAN Mask */ 603 604 #define MXC_F_CTB_SCA_CTRL1_AUTOCARRY_POS 1 /**< SCA_CTRL1_AUTOCARRY Position */ 605 #define MXC_F_CTB_SCA_CTRL1_AUTOCARRY ((uint32_t)(0x1UL << MXC_F_CTB_SCA_CTRL1_AUTOCARRY_POS)) /**< SCA_CTRL1_AUTOCARRY Mask */ 606 607 #define MXC_F_CTB_SCA_CTRL1_PLUSONE_POS 2 /**< SCA_CTRL1_PLUSONE Position */ 608 #define MXC_F_CTB_SCA_CTRL1_PLUSONE ((uint32_t)(0x1UL << MXC_F_CTB_SCA_CTRL1_PLUSONE_POS)) /**< SCA_CTRL1_PLUSONE Mask */ 609 610 #define MXC_F_CTB_SCA_CTRL1_RESSELECT_POS 3 /**< SCA_CTRL1_RESSELECT Position */ 611 #define MXC_F_CTB_SCA_CTRL1_RESSELECT ((uint32_t)(0x3UL << MXC_F_CTB_SCA_CTRL1_RESSELECT_POS)) /**< SCA_CTRL1_RESSELECT Mask */ 612 613 #define MXC_F_CTB_SCA_CTRL1_CARRYPOS_POS 8 /**< SCA_CTRL1_CARRYPOS Position */ 614 #define MXC_F_CTB_SCA_CTRL1_CARRYPOS ((uint32_t)(0x3FFUL << MXC_F_CTB_SCA_CTRL1_CARRYPOS_POS)) /**< SCA_CTRL1_CARRYPOS Mask */ 615 616 /**@} end of group CTB_SCA_CTRL1_Register */ 617 618 /** 619 * @ingroup ctb_registers 620 * @defgroup CTB_SCA_STAT CTB_SCA_STAT 621 * @brief SCA Status Register. 622 * @{ 623 */ 624 #define MXC_F_CTB_SCA_STAT_BUSY_POS 0 /**< SCA_STAT_BUSY Position */ 625 #define MXC_F_CTB_SCA_STAT_BUSY ((uint32_t)(0x1UL << MXC_F_CTB_SCA_STAT_BUSY_POS)) /**< SCA_STAT_BUSY Mask */ 626 627 #define MXC_F_CTB_SCA_STAT_SCAIF_POS 1 /**< SCA_STAT_SCAIF Position */ 628 #define MXC_F_CTB_SCA_STAT_SCAIF ((uint32_t)(0x1UL << MXC_F_CTB_SCA_STAT_SCAIF_POS)) /**< SCA_STAT_SCAIF Mask */ 629 630 #define MXC_F_CTB_SCA_STAT_PVF1_POS 2 /**< SCA_STAT_PVF1 Position */ 631 #define MXC_F_CTB_SCA_STAT_PVF1 ((uint32_t)(0x1UL << MXC_F_CTB_SCA_STAT_PVF1_POS)) /**< SCA_STAT_PVF1 Mask */ 632 633 #define MXC_F_CTB_SCA_STAT_PVF2_POS 3 /**< SCA_STAT_PVF2 Position */ 634 #define MXC_F_CTB_SCA_STAT_PVF2 ((uint32_t)(0x1UL << MXC_F_CTB_SCA_STAT_PVF2_POS)) /**< SCA_STAT_PVF2 Mask */ 635 636 #define MXC_F_CTB_SCA_STAT_FSMERR_POS 4 /**< SCA_STAT_FSMERR Position */ 637 #define MXC_F_CTB_SCA_STAT_FSMERR ((uint32_t)(0x1UL << MXC_F_CTB_SCA_STAT_FSMERR_POS)) /**< SCA_STAT_FSMERR Mask */ 638 639 #define MXC_F_CTB_SCA_STAT_COMPERR_POS 5 /**< SCA_STAT_COMPERR Position */ 640 #define MXC_F_CTB_SCA_STAT_COMPERR ((uint32_t)(0x1UL << MXC_F_CTB_SCA_STAT_COMPERR_POS)) /**< SCA_STAT_COMPERR Mask */ 641 642 #define MXC_F_CTB_SCA_STAT_MEMERR_POS 6 /**< SCA_STAT_MEMERR Position */ 643 #define MXC_F_CTB_SCA_STAT_MEMERR ((uint32_t)(0x1UL << MXC_F_CTB_SCA_STAT_MEMERR_POS)) /**< SCA_STAT_MEMERR Mask */ 644 645 #define MXC_F_CTB_SCA_STAT_CARRY_POS 8 /**< SCA_STAT_CARRY Position */ 646 #define MXC_F_CTB_SCA_STAT_CARRY ((uint32_t)(0x1UL << MXC_F_CTB_SCA_STAT_CARRY_POS)) /**< SCA_STAT_CARRY Mask */ 647 648 #define MXC_F_CTB_SCA_STAT_GTE2I2_POS 9 /**< SCA_STAT_GTE2I2 Position */ 649 #define MXC_F_CTB_SCA_STAT_GTE2I2 ((uint32_t)(0x1UL << MXC_F_CTB_SCA_STAT_GTE2I2_POS)) /**< SCA_STAT_GTE2I2 Mask */ 650 651 #define MXC_F_CTB_SCA_STAT_ALUNEG1_POS 10 /**< SCA_STAT_ALUNEG1 Position */ 652 #define MXC_F_CTB_SCA_STAT_ALUNEG1 ((uint32_t)(0x1UL << MXC_F_CTB_SCA_STAT_ALUNEG1_POS)) /**< SCA_STAT_ALUNEG1 Mask */ 653 654 #define MXC_F_CTB_SCA_STAT_ALUNEG2_POS 11 /**< SCA_STAT_ALUNEG2 Position */ 655 #define MXC_F_CTB_SCA_STAT_ALUNEG2 ((uint32_t)(0x1UL << MXC_F_CTB_SCA_STAT_ALUNEG2_POS)) /**< SCA_STAT_ALUNEG2 Mask */ 656 657 /**@} end of group CTB_SCA_STAT_Register */ 658 659 /** 660 * @ingroup ctb_registers 661 * @defgroup CTB_SCA_PPX_ADDR CTB_SCA_PPX_ADDR 662 * @brief PPX Coordinate Data Pointer Register. 663 * @{ 664 */ 665 #define MXC_F_CTB_SCA_PPX_ADDR_ADDR_POS 0 /**< SCA_PPX_ADDR_ADDR Position */ 666 #define MXC_F_CTB_SCA_PPX_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_SCA_PPX_ADDR_ADDR_POS)) /**< SCA_PPX_ADDR_ADDR Mask */ 667 668 /**@} end of group CTB_SCA_PPX_ADDR_Register */ 669 670 /** 671 * @ingroup ctb_registers 672 * @defgroup CTB_SCA_PPY_ADDR CTB_SCA_PPY_ADDR 673 * @brief PPY Coordinate Data Pointer Register. 674 * @{ 675 */ 676 #define MXC_F_CTB_SCA_PPY_ADDR_ADDR_POS 0 /**< SCA_PPY_ADDR_ADDR Position */ 677 #define MXC_F_CTB_SCA_PPY_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_SCA_PPY_ADDR_ADDR_POS)) /**< SCA_PPY_ADDR_ADDR Mask */ 678 679 /**@} end of group CTB_SCA_PPY_ADDR_Register */ 680 681 /** 682 * @ingroup ctb_registers 683 * @defgroup CTB_SCA_PPZ_ADDR CTB_SCA_PPZ_ADDR 684 * @brief PPZ Coordinate Data Pointer Register. 685 * @{ 686 */ 687 #define MXC_F_CTB_SCA_PPZ_ADDR_ADDR_POS 0 /**< SCA_PPZ_ADDR_ADDR Position */ 688 #define MXC_F_CTB_SCA_PPZ_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_SCA_PPZ_ADDR_ADDR_POS)) /**< SCA_PPZ_ADDR_ADDR Mask */ 689 690 /**@} end of group CTB_SCA_PPZ_ADDR_Register */ 691 692 /** 693 * @ingroup ctb_registers 694 * @defgroup CTB_SCA_PQX_ADDR CTB_SCA_PQX_ADDR 695 * @brief PQX Coordinate Data Pointer Register. 696 * @{ 697 */ 698 #define MXC_F_CTB_SCA_PQX_ADDR_ADDR_POS 0 /**< SCA_PQX_ADDR_ADDR Position */ 699 #define MXC_F_CTB_SCA_PQX_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_SCA_PQX_ADDR_ADDR_POS)) /**< SCA_PQX_ADDR_ADDR Mask */ 700 701 /**@} end of group CTB_SCA_PQX_ADDR_Register */ 702 703 /** 704 * @ingroup ctb_registers 705 * @defgroup CTB_SCA_PQY_ADDR CTB_SCA_PQY_ADDR 706 * @brief PQY Coordinate Data Pointer Register. 707 * @{ 708 */ 709 #define MXC_F_CTB_SCA_PQY_ADDR_ADDR_POS 0 /**< SCA_PQY_ADDR_ADDR Position */ 710 #define MXC_F_CTB_SCA_PQY_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_SCA_PQY_ADDR_ADDR_POS)) /**< SCA_PQY_ADDR_ADDR Mask */ 711 712 /**@} end of group CTB_SCA_PQY_ADDR_Register */ 713 714 /** 715 * @ingroup ctb_registers 716 * @defgroup CTB_SCA_PQZ_ADDR CTB_SCA_PQZ_ADDR 717 * @brief PQZ Coordinate Data Pointer Register. 718 * @{ 719 */ 720 #define MXC_F_CTB_SCA_PQZ_ADDR_ADDR_POS 0 /**< SCA_PQZ_ADDR_ADDR Position */ 721 #define MXC_F_CTB_SCA_PQZ_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_SCA_PQZ_ADDR_ADDR_POS)) /**< SCA_PQZ_ADDR_ADDR Mask */ 722 723 /**@} end of group CTB_SCA_PQZ_ADDR_Register */ 724 725 /** 726 * @ingroup ctb_registers 727 * @defgroup CTB_SCA_RDSA_ADDR CTB_SCA_RDSA_ADDR 728 * @brief SCA RDSA Address Register. 729 * @{ 730 */ 731 #define MXC_F_CTB_SCA_RDSA_ADDR_ADDR_POS 0 /**< SCA_RDSA_ADDR_ADDR Position */ 732 #define MXC_F_CTB_SCA_RDSA_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_SCA_RDSA_ADDR_ADDR_POS)) /**< SCA_RDSA_ADDR_ADDR Mask */ 733 734 /**@} end of group CTB_SCA_RDSA_ADDR_Register */ 735 736 /** 737 * @ingroup ctb_registers 738 * @defgroup CTB_SCA_RES_ADDR CTB_SCA_RES_ADDR 739 * @brief SCA Result Address Register. 740 * @{ 741 */ 742 #define MXC_F_CTB_SCA_RES_ADDR_ADDR_POS 0 /**< SCA_RES_ADDR_ADDR Position */ 743 #define MXC_F_CTB_SCA_RES_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_SCA_RES_ADDR_ADDR_POS)) /**< SCA_RES_ADDR_ADDR Mask */ 744 745 /**@} end of group CTB_SCA_RES_ADDR_Register */ 746 747 /** 748 * @ingroup ctb_registers 749 * @defgroup CTB_SCA_OP_BUFF_ADDR CTB_SCA_OP_BUFF_ADDR 750 * @brief SCA Operation Buffer Address Register. 751 * @{ 752 */ 753 #define MXC_F_CTB_SCA_OP_BUFF_ADDR_ADDR_POS 0 /**< SCA_OP_BUFF_ADDR_ADDR Position */ 754 #define MXC_F_CTB_SCA_OP_BUFF_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_SCA_OP_BUFF_ADDR_ADDR_POS)) /**< SCA_OP_BUFF_ADDR_ADDR Mask */ 755 756 /**@} end of group CTB_SCA_OP_BUFF_ADDR_Register */ 757 758 /** 759 * @ingroup ctb_registers 760 * @defgroup CTB_SCA_MODDATA CTB_SCA_MODDATA 761 * @brief SCA Modulo Data Input Register. 762 * @{ 763 */ 764 #define MXC_F_CTB_SCA_MODDATA_DATA_POS 0 /**< SCA_MODDATA_DATA Position */ 765 #define MXC_F_CTB_SCA_MODDATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_SCA_MODDATA_DATA_POS)) /**< SCA_MODDATA_DATA Mask */ 766 767 /**@} end of group CTB_SCA_MODDATA_Register */ 768 769 #ifdef __cplusplus 770 } 771 #endif 772 773 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32570_INCLUDE_CTB_REGS_H_ 774
