1 /** 2 * @file ctb_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the CTB Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup ctb_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32520_INCLUDE_CTB_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32520_INCLUDE_CTB_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup ctb 67 * @defgroup ctb_registers CTB_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the CTB Peripheral Module. 69 * @details The Cryptographic Toolbox is a combination of cryptographic engines and a secure cryptographic accelerator (SCA) used to provide advanced cryptographic security. 70 */ 71 72 /** 73 * @ingroup ctb_registers 74 * Structure type to access the CTB Registers. 75 */ 76 typedef struct { 77 __IO uint32_t crypto_ctrl; /**< <tt>\b 0x00:</tt> CTB CRYPTO_CTRL Register */ 78 __IO uint32_t cipher_ctrl; /**< <tt>\b 0x04:</tt> CTB CIPHER_CTRL Register */ 79 __IO uint32_t hash_ctrl; /**< <tt>\b 0x08:</tt> CTB HASH_CTRL Register */ 80 __IO uint32_t crc_ctrl; /**< <tt>\b 0x0C:</tt> CTB CRC_CTRL Register */ 81 __IO uint32_t dma_src; /**< <tt>\b 0x10:</tt> CTB DMA_SRC Register */ 82 __IO uint32_t dma_dest; /**< <tt>\b 0x14:</tt> CTB DMA_DEST Register */ 83 __IO uint32_t dma_cnt; /**< <tt>\b 0x18:</tt> CTB DMA_CNT Register */ 84 __R uint32_t rsv_0x1c; 85 __O uint32_t crypto_din[4]; /**< <tt>\b 0x20:</tt> CTB CRYPTO_DIN Register */ 86 __I uint32_t crypto_dout[4]; /**< <tt>\b 0x30:</tt> CTB CRYPTO_DOUT Register */ 87 __IO uint32_t crc_poly; /**< <tt>\b 0x40:</tt> CTB CRC_POLY Register */ 88 __IO uint32_t crc_val; /**< <tt>\b 0x44:</tt> CTB CRC_VAL Register */ 89 __IO uint32_t crc_prng; /**< <tt>\b 0x48:</tt> CTB CRC_PRNG Register */ 90 __IO uint32_t ham_ecc; /**< <tt>\b 0x4C:</tt> CTB HAM_ECC Register */ 91 __IO uint32_t cipher_init[4]; /**< <tt>\b 0x50:</tt> CTB CIPHER_INIT Register */ 92 __O uint32_t cipher_key[8]; /**< <tt>\b 0x60:</tt> CTB CIPHER_KEY Register */ 93 __IO uint32_t hash_digest[16]; /**< <tt>\b 0x80:</tt> CTB HASH_DIGEST Register */ 94 __IO uint32_t hash_msg_sz[4]; /**< <tt>\b 0xC0:</tt> CTB HASH_MSG_SZ Register */ 95 __IO uint32_t a_length_0; /**< <tt>\b 0xD0:</tt> CTB A_LENGTH_0 Register */ 96 __IO uint32_t a_length_1; /**< <tt>\b 0xD4:</tt> CTB A_LENGTH_1 Register */ 97 __IO uint32_t pld_length_0; /**< <tt>\b 0xD8:</tt> CTB PLD_LENGTH_0 Register */ 98 __IO uint32_t pld_length_1; /**< <tt>\b 0xDC:</tt> CTB PLD_LENGTH_1 Register */ 99 __IO uint32_t tagmic[4]; /**< <tt>\b 0xE0:</tt> CTB TAGMIC Register */ 100 __R uint32_t rsv_0xf0_0xff[4]; 101 __IO uint32_t sca_cn; /**< <tt>\b 0x100:</tt> CTB SCA_CN Register */ 102 __IO uint32_t sca_acn; /**< <tt>\b 0x104:</tt> CTB SCA_ACN Register */ 103 __IO uint32_t sca_st; /**< <tt>\b 0x108:</tt> CTB SCA_ST Register */ 104 __IO uint32_t sca_ppx_addr; /**< <tt>\b 0x10C:</tt> CTB SCA_PPX_ADDR Register */ 105 __IO uint32_t sca_ppy_addr; /**< <tt>\b 0x110:</tt> CTB SCA_PPY_ADDR Register */ 106 __IO uint32_t sca_ppz_addr; /**< <tt>\b 0x114:</tt> CTB SCA_PPZ_ADDR Register */ 107 __IO uint32_t sca_pqx_addr; /**< <tt>\b 0x118:</tt> CTB SCA_PQX_ADDR Register */ 108 __IO uint32_t sca_pqy_addr; /**< <tt>\b 0x11C:</tt> CTB SCA_PQY_ADDR Register */ 109 __IO uint32_t sca_pqz_addr; /**< <tt>\b 0x120:</tt> CTB SCA_PQZ_ADDR Register */ 110 __IO uint32_t sca_rdsa_addr; /**< <tt>\b 0x124:</tt> CTB SCA_RDSA_ADDR Register */ 111 __IO uint32_t sca_res_addr; /**< <tt>\b 0x128:</tt> CTB SCA_RES_ADDR Register */ 112 __IO uint32_t sca_op_buff_addr; /**< <tt>\b 0x12C:</tt> CTB SCA_OP_BUFF_ADDR Register */ 113 __IO uint32_t sca_moddata; /**< <tt>\b 0x130:</tt> CTB SCA_MODDATA Register */ 114 } mxc_ctb_regs_t; 115 116 /* Register offsets for module CTB */ 117 /** 118 * @ingroup ctb_registers 119 * @defgroup CTB_Register_Offsets Register Offsets 120 * @brief CTB Peripheral Register Offsets from the CTB Base Peripheral Address. 121 * @{ 122 */ 123 #define MXC_R_CTB_CRYPTO_CTRL ((uint32_t)0x00000000UL) /**< Offset from CTB Base Address: <tt> 0x0000</tt> */ 124 #define MXC_R_CTB_CIPHER_CTRL ((uint32_t)0x00000004UL) /**< Offset from CTB Base Address: <tt> 0x0004</tt> */ 125 #define MXC_R_CTB_HASH_CTRL ((uint32_t)0x00000008UL) /**< Offset from CTB Base Address: <tt> 0x0008</tt> */ 126 #define MXC_R_CTB_CRC_CTRL ((uint32_t)0x0000000CUL) /**< Offset from CTB Base Address: <tt> 0x000C</tt> */ 127 #define MXC_R_CTB_DMA_SRC ((uint32_t)0x00000010UL) /**< Offset from CTB Base Address: <tt> 0x0010</tt> */ 128 #define MXC_R_CTB_DMA_DEST ((uint32_t)0x00000014UL) /**< Offset from CTB Base Address: <tt> 0x0014</tt> */ 129 #define MXC_R_CTB_DMA_CNT ((uint32_t)0x00000018UL) /**< Offset from CTB Base Address: <tt> 0x0018</tt> */ 130 #define MXC_R_CTB_CRYPTO_DIN ((uint32_t)0x00000020UL) /**< Offset from CTB Base Address: <tt> 0x0020</tt> */ 131 #define MXC_R_CTB_CRYPTO_DOUT ((uint32_t)0x00000030UL) /**< Offset from CTB Base Address: <tt> 0x0030</tt> */ 132 #define MXC_R_CTB_CRC_POLY ((uint32_t)0x00000040UL) /**< Offset from CTB Base Address: <tt> 0x0040</tt> */ 133 #define MXC_R_CTB_CRC_VAL ((uint32_t)0x00000044UL) /**< Offset from CTB Base Address: <tt> 0x0044</tt> */ 134 #define MXC_R_CTB_CRC_PRNG ((uint32_t)0x00000048UL) /**< Offset from CTB Base Address: <tt> 0x0048</tt> */ 135 #define MXC_R_CTB_HAM_ECC ((uint32_t)0x0000004CUL) /**< Offset from CTB Base Address: <tt> 0x004C</tt> */ 136 #define MXC_R_CTB_CIPHER_INIT ((uint32_t)0x00000050UL) /**< Offset from CTB Base Address: <tt> 0x0050</tt> */ 137 #define MXC_R_CTB_CIPHER_KEY ((uint32_t)0x00000060UL) /**< Offset from CTB Base Address: <tt> 0x0060</tt> */ 138 #define MXC_R_CTB_HASH_DIGEST ((uint32_t)0x00000080UL) /**< Offset from CTB Base Address: <tt> 0x0080</tt> */ 139 #define MXC_R_CTB_HASH_MSG_SZ ((uint32_t)0x000000C0UL) /**< Offset from CTB Base Address: <tt> 0x00C0</tt> */ 140 #define MXC_R_CTB_A_LENGTH_0 ((uint32_t)0x000000D0UL) /**< Offset from CTB Base Address: <tt> 0x00D0</tt> */ 141 #define MXC_R_CTB_A_LENGTH_1 ((uint32_t)0x000000D4UL) /**< Offset from CTB Base Address: <tt> 0x00D4</tt> */ 142 #define MXC_R_CTB_PLD_LENGTH_0 ((uint32_t)0x000000D8UL) /**< Offset from CTB Base Address: <tt> 0x00D8</tt> */ 143 #define MXC_R_CTB_PLD_LENGTH_1 ((uint32_t)0x000000DCUL) /**< Offset from CTB Base Address: <tt> 0x00DC</tt> */ 144 #define MXC_R_CTB_TAGMIC ((uint32_t)0x000000E0UL) /**< Offset from CTB Base Address: <tt> 0x00E0</tt> */ 145 #define MXC_R_CTB_SCA_CN ((uint32_t)0x00000100UL) /**< Offset from CTB Base Address: <tt> 0x0100</tt> */ 146 #define MXC_R_CTB_SCA_ACN ((uint32_t)0x00000104UL) /**< Offset from CTB Base Address: <tt> 0x0104</tt> */ 147 #define MXC_R_CTB_SCA_ST ((uint32_t)0x00000108UL) /**< Offset from CTB Base Address: <tt> 0x0108</tt> */ 148 #define MXC_R_CTB_SCA_PPX_ADDR ((uint32_t)0x0000010CUL) /**< Offset from CTB Base Address: <tt> 0x010C</tt> */ 149 #define MXC_R_CTB_SCA_PPY_ADDR ((uint32_t)0x00000110UL) /**< Offset from CTB Base Address: <tt> 0x0110</tt> */ 150 #define MXC_R_CTB_SCA_PPZ_ADDR ((uint32_t)0x00000114UL) /**< Offset from CTB Base Address: <tt> 0x0114</tt> */ 151 #define MXC_R_CTB_SCA_PQX_ADDR ((uint32_t)0x00000118UL) /**< Offset from CTB Base Address: <tt> 0x0118</tt> */ 152 #define MXC_R_CTB_SCA_PQY_ADDR ((uint32_t)0x0000011CUL) /**< Offset from CTB Base Address: <tt> 0x011C</tt> */ 153 #define MXC_R_CTB_SCA_PQZ_ADDR ((uint32_t)0x00000120UL) /**< Offset from CTB Base Address: <tt> 0x0120</tt> */ 154 #define MXC_R_CTB_SCA_RDSA_ADDR ((uint32_t)0x00000124UL) /**< Offset from CTB Base Address: <tt> 0x0124</tt> */ 155 #define MXC_R_CTB_SCA_RES_ADDR ((uint32_t)0x00000128UL) /**< Offset from CTB Base Address: <tt> 0x0128</tt> */ 156 #define MXC_R_CTB_SCA_OP_BUFF_ADDR ((uint32_t)0x0000012CUL) /**< Offset from CTB Base Address: <tt> 0x012C</tt> */ 157 #define MXC_R_CTB_SCA_MODDATA ((uint32_t)0x00000130UL) /**< Offset from CTB Base Address: <tt> 0x0130</tt> */ 158 /**@} end of group ctb_registers */ 159 160 /** 161 * @ingroup ctb_registers 162 * @defgroup CTB_CRYPTO_CTRL CTB_CRYPTO_CTRL 163 * @brief Crypto Control Register. 164 * @{ 165 */ 166 #define MXC_F_CTB_CRYPTO_CTRL_RST_POS 0 /**< CRYPTO_CTRL_RST Position */ 167 #define MXC_F_CTB_CRYPTO_CTRL_RST ((uint32_t)(0x1UL << MXC_F_CTB_CRYPTO_CTRL_RST_POS)) /**< CRYPTO_CTRL_RST Mask */ 168 169 #define MXC_F_CTB_CRYPTO_CTRL_INT_POS 1 /**< CRYPTO_CTRL_INT Position */ 170 #define MXC_F_CTB_CRYPTO_CTRL_INT ((uint32_t)(0x1UL << MXC_F_CTB_CRYPTO_CTRL_INT_POS)) /**< CRYPTO_CTRL_INT Mask */ 171 172 #define MXC_F_CTB_CRYPTO_CTRL_SRC_POS 2 /**< CRYPTO_CTRL_SRC Position */ 173 #define MXC_F_CTB_CRYPTO_CTRL_SRC ((uint32_t)(0x1UL << MXC_F_CTB_CRYPTO_CTRL_SRC_POS)) /**< CRYPTO_CTRL_SRC Mask */ 174 175 #define MXC_F_CTB_CRYPTO_CTRL_BSO_POS 4 /**< CRYPTO_CTRL_BSO Position */ 176 #define MXC_F_CTB_CRYPTO_CTRL_BSO ((uint32_t)(0x1UL << MXC_F_CTB_CRYPTO_CTRL_BSO_POS)) /**< CRYPTO_CTRL_BSO Mask */ 177 178 #define MXC_F_CTB_CRYPTO_CTRL_BSI_POS 5 /**< CRYPTO_CTRL_BSI Position */ 179 #define MXC_F_CTB_CRYPTO_CTRL_BSI ((uint32_t)(0x1UL << MXC_F_CTB_CRYPTO_CTRL_BSI_POS)) /**< CRYPTO_CTRL_BSI Mask */ 180 181 #define MXC_F_CTB_CRYPTO_CTRL_WAIT_EN_POS 6 /**< CRYPTO_CTRL_WAIT_EN Position */ 182 #define MXC_F_CTB_CRYPTO_CTRL_WAIT_EN ((uint32_t)(0x1UL << MXC_F_CTB_CRYPTO_CTRL_WAIT_EN_POS)) /**< CRYPTO_CTRL_WAIT_EN Mask */ 183 184 #define MXC_F_CTB_CRYPTO_CTRL_WAIT_POL_POS 7 /**< CRYPTO_CTRL_WAIT_POL Position */ 185 #define MXC_F_CTB_CRYPTO_CTRL_WAIT_POL ((uint32_t)(0x1UL << MXC_F_CTB_CRYPTO_CTRL_WAIT_POL_POS)) /**< CRYPTO_CTRL_WAIT_POL Mask */ 186 187 #define MXC_F_CTB_CRYPTO_CTRL_WRSRC_POS 8 /**< CRYPTO_CTRL_WRSRC Position */ 188 #define MXC_F_CTB_CRYPTO_CTRL_WRSRC ((uint32_t)(0x3UL << MXC_F_CTB_CRYPTO_CTRL_WRSRC_POS)) /**< CRYPTO_CTRL_WRSRC Mask */ 189 #define MXC_V_CTB_CRYPTO_CTRL_WRSRC_NONE ((uint32_t)0x0UL) /**< CRYPTO_CTRL_WRSRC_NONE Value */ 190 #define MXC_S_CTB_CRYPTO_CTRL_WRSRC_NONE (MXC_V_CTB_CRYPTO_CTRL_WRSRC_NONE << MXC_F_CTB_CRYPTO_CTRL_WRSRC_POS) /**< CRYPTO_CTRL_WRSRC_NONE Setting */ 191 #define MXC_V_CTB_CRYPTO_CTRL_WRSRC_CIPHEROUTPUT ((uint32_t)0x1UL) /**< CRYPTO_CTRL_WRSRC_CIPHEROUTPUT Value */ 192 #define MXC_S_CTB_CRYPTO_CTRL_WRSRC_CIPHEROUTPUT (MXC_V_CTB_CRYPTO_CTRL_WRSRC_CIPHEROUTPUT << MXC_F_CTB_CRYPTO_CTRL_WRSRC_POS) /**< CRYPTO_CTRL_WRSRC_CIPHEROUTPUT Setting */ 193 #define MXC_V_CTB_CRYPTO_CTRL_WRSRC_READFIFO ((uint32_t)0x2UL) /**< CRYPTO_CTRL_WRSRC_READFIFO Value */ 194 #define MXC_S_CTB_CRYPTO_CTRL_WRSRC_READFIFO (MXC_V_CTB_CRYPTO_CTRL_WRSRC_READFIFO << MXC_F_CTB_CRYPTO_CTRL_WRSRC_POS) /**< CRYPTO_CTRL_WRSRC_READFIFO Setting */ 195 196 #define MXC_F_CTB_CRYPTO_CTRL_RDSRC_POS 10 /**< CRYPTO_CTRL_RDSRC Position */ 197 #define MXC_F_CTB_CRYPTO_CTRL_RDSRC ((uint32_t)(0x3UL << MXC_F_CTB_CRYPTO_CTRL_RDSRC_POS)) /**< CRYPTO_CTRL_RDSRC Mask */ 198 #define MXC_V_CTB_CRYPTO_CTRL_RDSRC_DMADISABLED ((uint32_t)0x0UL) /**< CRYPTO_CTRL_RDSRC_DMADISABLED Value */ 199 #define MXC_S_CTB_CRYPTO_CTRL_RDSRC_DMADISABLED (MXC_V_CTB_CRYPTO_CTRL_RDSRC_DMADISABLED << MXC_F_CTB_CRYPTO_CTRL_RDSRC_POS) /**< CRYPTO_CTRL_RDSRC_DMADISABLED Setting */ 200 #define MXC_V_CTB_CRYPTO_CTRL_RDSRC_DMAORAPB ((uint32_t)0x1UL) /**< CRYPTO_CTRL_RDSRC_DMAORAPB Value */ 201 #define MXC_S_CTB_CRYPTO_CTRL_RDSRC_DMAORAPB (MXC_V_CTB_CRYPTO_CTRL_RDSRC_DMAORAPB << MXC_F_CTB_CRYPTO_CTRL_RDSRC_POS) /**< CRYPTO_CTRL_RDSRC_DMAORAPB Setting */ 202 #define MXC_V_CTB_CRYPTO_CTRL_RDSRC_RNG ((uint32_t)0x2UL) /**< CRYPTO_CTRL_RDSRC_RNG Value */ 203 #define MXC_S_CTB_CRYPTO_CTRL_RDSRC_RNG (MXC_V_CTB_CRYPTO_CTRL_RDSRC_RNG << MXC_F_CTB_CRYPTO_CTRL_RDSRC_POS) /**< CRYPTO_CTRL_RDSRC_RNG Setting */ 204 205 #define MXC_F_CTB_CRYPTO_CTRL_FLAG_MODE_POS 14 /**< CRYPTO_CTRL_FLAG_MODE Position */ 206 #define MXC_F_CTB_CRYPTO_CTRL_FLAG_MODE ((uint32_t)(0x1UL << MXC_F_CTB_CRYPTO_CTRL_FLAG_MODE_POS)) /**< CRYPTO_CTRL_FLAG_MODE Mask */ 207 208 #define MXC_F_CTB_CRYPTO_CTRL_DMADNEMSK_POS 15 /**< CRYPTO_CTRL_DMADNEMSK Position */ 209 #define MXC_F_CTB_CRYPTO_CTRL_DMADNEMSK ((uint32_t)(0x1UL << MXC_F_CTB_CRYPTO_CTRL_DMADNEMSK_POS)) /**< CRYPTO_CTRL_DMADNEMSK Mask */ 210 211 #define MXC_F_CTB_CRYPTO_CTRL_DMA_DONE_POS 24 /**< CRYPTO_CTRL_DMA_DONE Position */ 212 #define MXC_F_CTB_CRYPTO_CTRL_DMA_DONE ((uint32_t)(0x1UL << MXC_F_CTB_CRYPTO_CTRL_DMA_DONE_POS)) /**< CRYPTO_CTRL_DMA_DONE Mask */ 213 214 #define MXC_F_CTB_CRYPTO_CTRL_GLS_DONE_POS 25 /**< CRYPTO_CTRL_GLS_DONE Position */ 215 #define MXC_F_CTB_CRYPTO_CTRL_GLS_DONE ((uint32_t)(0x1UL << MXC_F_CTB_CRYPTO_CTRL_GLS_DONE_POS)) /**< CRYPTO_CTRL_GLS_DONE Mask */ 216 217 #define MXC_F_CTB_CRYPTO_CTRL_HSH_DONE_POS 26 /**< CRYPTO_CTRL_HSH_DONE Position */ 218 #define MXC_F_CTB_CRYPTO_CTRL_HSH_DONE ((uint32_t)(0x1UL << MXC_F_CTB_CRYPTO_CTRL_HSH_DONE_POS)) /**< CRYPTO_CTRL_HSH_DONE Mask */ 219 220 #define MXC_F_CTB_CRYPTO_CTRL_CPH_DONE_POS 27 /**< CRYPTO_CTRL_CPH_DONE Position */ 221 #define MXC_F_CTB_CRYPTO_CTRL_CPH_DONE ((uint32_t)(0x1UL << MXC_F_CTB_CRYPTO_CTRL_CPH_DONE_POS)) /**< CRYPTO_CTRL_CPH_DONE Mask */ 222 223 #define MXC_F_CTB_CRYPTO_CTRL_ERR_POS 29 /**< CRYPTO_CTRL_ERR Position */ 224 #define MXC_F_CTB_CRYPTO_CTRL_ERR ((uint32_t)(0x1UL << MXC_F_CTB_CRYPTO_CTRL_ERR_POS)) /**< CRYPTO_CTRL_ERR Mask */ 225 226 #define MXC_F_CTB_CRYPTO_CTRL_RDY_POS 30 /**< CRYPTO_CTRL_RDY Position */ 227 #define MXC_F_CTB_CRYPTO_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_CTB_CRYPTO_CTRL_RDY_POS)) /**< CRYPTO_CTRL_RDY Mask */ 228 229 #define MXC_F_CTB_CRYPTO_CTRL_DONE_POS 31 /**< CRYPTO_CTRL_DONE Position */ 230 #define MXC_F_CTB_CRYPTO_CTRL_DONE ((uint32_t)(0x1UL << MXC_F_CTB_CRYPTO_CTRL_DONE_POS)) /**< CRYPTO_CTRL_DONE Mask */ 231 232 /**@} end of group CTB_CRYPTO_CTRL_Register */ 233 234 /** 235 * @ingroup ctb_registers 236 * @defgroup CTB_CIPHER_CTRL CTB_CIPHER_CTRL 237 * @brief Cipher Control Register. 238 * @{ 239 */ 240 #define MXC_F_CTB_CIPHER_CTRL_ENC_POS 0 /**< CIPHER_CTRL_ENC Position */ 241 #define MXC_F_CTB_CIPHER_CTRL_ENC ((uint32_t)(0x1UL << MXC_F_CTB_CIPHER_CTRL_ENC_POS)) /**< CIPHER_CTRL_ENC Mask */ 242 243 #define MXC_F_CTB_CIPHER_CTRL_KEY_POS 1 /**< CIPHER_CTRL_KEY Position */ 244 #define MXC_F_CTB_CIPHER_CTRL_KEY ((uint32_t)(0x1UL << MXC_F_CTB_CIPHER_CTRL_KEY_POS)) /**< CIPHER_CTRL_KEY Mask */ 245 246 #define MXC_F_CTB_CIPHER_CTRL_SRC_POS 2 /**< CIPHER_CTRL_SRC Position */ 247 #define MXC_F_CTB_CIPHER_CTRL_SRC ((uint32_t)(0x3UL << MXC_F_CTB_CIPHER_CTRL_SRC_POS)) /**< CIPHER_CTRL_SRC Mask */ 248 #define MXC_V_CTB_CIPHER_CTRL_SRC_CIPHERKEY ((uint32_t)0x0UL) /**< CIPHER_CTRL_SRC_CIPHERKEY Value */ 249 #define MXC_S_CTB_CIPHER_CTRL_SRC_CIPHERKEY (MXC_V_CTB_CIPHER_CTRL_SRC_CIPHERKEY << MXC_F_CTB_CIPHER_CTRL_SRC_POS) /**< CIPHER_CTRL_SRC_CIPHERKEY Setting */ 250 #define MXC_V_CTB_CIPHER_CTRL_SRC_REGFILE ((uint32_t)0x2UL) /**< CIPHER_CTRL_SRC_REGFILE Value */ 251 #define MXC_S_CTB_CIPHER_CTRL_SRC_REGFILE (MXC_V_CTB_CIPHER_CTRL_SRC_REGFILE << MXC_F_CTB_CIPHER_CTRL_SRC_POS) /**< CIPHER_CTRL_SRC_REGFILE Setting */ 252 #define MXC_V_CTB_CIPHER_CTRL_SRC_QSPIKEY_REGFILE ((uint32_t)0x3UL) /**< CIPHER_CTRL_SRC_QSPIKEY_REGFILE Value */ 253 #define MXC_S_CTB_CIPHER_CTRL_SRC_QSPIKEY_REGFILE (MXC_V_CTB_CIPHER_CTRL_SRC_QSPIKEY_REGFILE << MXC_F_CTB_CIPHER_CTRL_SRC_POS) /**< CIPHER_CTRL_SRC_QSPIKEY_REGFILE Setting */ 254 255 #define MXC_F_CTB_CIPHER_CTRL_CIPHER_POS 4 /**< CIPHER_CTRL_CIPHER Position */ 256 #define MXC_F_CTB_CIPHER_CTRL_CIPHER ((uint32_t)(0x7UL << MXC_F_CTB_CIPHER_CTRL_CIPHER_POS)) /**< CIPHER_CTRL_CIPHER Mask */ 257 #define MXC_V_CTB_CIPHER_CTRL_CIPHER_DIS ((uint32_t)0x0UL) /**< CIPHER_CTRL_CIPHER_DIS Value */ 258 #define MXC_S_CTB_CIPHER_CTRL_CIPHER_DIS (MXC_V_CTB_CIPHER_CTRL_CIPHER_DIS << MXC_F_CTB_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_DIS Setting */ 259 #define MXC_V_CTB_CIPHER_CTRL_CIPHER_AES128 ((uint32_t)0x1UL) /**< CIPHER_CTRL_CIPHER_AES128 Value */ 260 #define MXC_S_CTB_CIPHER_CTRL_CIPHER_AES128 (MXC_V_CTB_CIPHER_CTRL_CIPHER_AES128 << MXC_F_CTB_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_AES128 Setting */ 261 #define MXC_V_CTB_CIPHER_CTRL_CIPHER_AES192 ((uint32_t)0x2UL) /**< CIPHER_CTRL_CIPHER_AES192 Value */ 262 #define MXC_S_CTB_CIPHER_CTRL_CIPHER_AES192 (MXC_V_CTB_CIPHER_CTRL_CIPHER_AES192 << MXC_F_CTB_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_AES192 Setting */ 263 #define MXC_V_CTB_CIPHER_CTRL_CIPHER_AES256 ((uint32_t)0x3UL) /**< CIPHER_CTRL_CIPHER_AES256 Value */ 264 #define MXC_S_CTB_CIPHER_CTRL_CIPHER_AES256 (MXC_V_CTB_CIPHER_CTRL_CIPHER_AES256 << MXC_F_CTB_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_AES256 Setting */ 265 #define MXC_V_CTB_CIPHER_CTRL_CIPHER_DES ((uint32_t)0x4UL) /**< CIPHER_CTRL_CIPHER_DES Value */ 266 #define MXC_S_CTB_CIPHER_CTRL_CIPHER_DES (MXC_V_CTB_CIPHER_CTRL_CIPHER_DES << MXC_F_CTB_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_DES Setting */ 267 #define MXC_V_CTB_CIPHER_CTRL_CIPHER_TDES ((uint32_t)0x5UL) /**< CIPHER_CTRL_CIPHER_TDES Value */ 268 #define MXC_S_CTB_CIPHER_CTRL_CIPHER_TDES (MXC_V_CTB_CIPHER_CTRL_CIPHER_TDES << MXC_F_CTB_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_TDES Setting */ 269 270 #define MXC_F_CTB_CIPHER_CTRL_MODE_POS 8 /**< CIPHER_CTRL_MODE Position */ 271 #define MXC_F_CTB_CIPHER_CTRL_MODE ((uint32_t)(0x7UL << MXC_F_CTB_CIPHER_CTRL_MODE_POS)) /**< CIPHER_CTRL_MODE Mask */ 272 #define MXC_V_CTB_CIPHER_CTRL_MODE_ECB ((uint32_t)0x0UL) /**< CIPHER_CTRL_MODE_ECB Value */ 273 #define MXC_S_CTB_CIPHER_CTRL_MODE_ECB (MXC_V_CTB_CIPHER_CTRL_MODE_ECB << MXC_F_CTB_CIPHER_CTRL_MODE_POS) /**< CIPHER_CTRL_MODE_ECB Setting */ 274 #define MXC_V_CTB_CIPHER_CTRL_MODE_CBC ((uint32_t)0x1UL) /**< CIPHER_CTRL_MODE_CBC Value */ 275 #define MXC_S_CTB_CIPHER_CTRL_MODE_CBC (MXC_V_CTB_CIPHER_CTRL_MODE_CBC << MXC_F_CTB_CIPHER_CTRL_MODE_POS) /**< CIPHER_CTRL_MODE_CBC Setting */ 276 #define MXC_V_CTB_CIPHER_CTRL_MODE_CFB ((uint32_t)0x2UL) /**< CIPHER_CTRL_MODE_CFB Value */ 277 #define MXC_S_CTB_CIPHER_CTRL_MODE_CFB (MXC_V_CTB_CIPHER_CTRL_MODE_CFB << MXC_F_CTB_CIPHER_CTRL_MODE_POS) /**< CIPHER_CTRL_MODE_CFB Setting */ 278 #define MXC_V_CTB_CIPHER_CTRL_MODE_OFB ((uint32_t)0x3UL) /**< CIPHER_CTRL_MODE_OFB Value */ 279 #define MXC_S_CTB_CIPHER_CTRL_MODE_OFB (MXC_V_CTB_CIPHER_CTRL_MODE_OFB << MXC_F_CTB_CIPHER_CTRL_MODE_POS) /**< CIPHER_CTRL_MODE_OFB Setting */ 280 #define MXC_V_CTB_CIPHER_CTRL_MODE_CTR ((uint32_t)0x4UL) /**< CIPHER_CTRL_MODE_CTR Value */ 281 #define MXC_S_CTB_CIPHER_CTRL_MODE_CTR (MXC_V_CTB_CIPHER_CTRL_MODE_CTR << MXC_F_CTB_CIPHER_CTRL_MODE_POS) /**< CIPHER_CTRL_MODE_CTR Setting */ 282 283 #define MXC_F_CTB_CIPHER_CTRL_COMPH_POS 11 /**< CIPHER_CTRL_COMPH Position */ 284 #define MXC_F_CTB_CIPHER_CTRL_COMPH ((uint32_t)(0x1UL << MXC_F_CTB_CIPHER_CTRL_COMPH_POS)) /**< CIPHER_CTRL_COMPH Mask */ 285 286 #define MXC_F_CTB_CIPHER_CTRL_DTYPE_POS 12 /**< CIPHER_CTRL_DTYPE Position */ 287 #define MXC_F_CTB_CIPHER_CTRL_DTYPE ((uint32_t)(0x1UL << MXC_F_CTB_CIPHER_CTRL_DTYPE_POS)) /**< CIPHER_CTRL_DTYPE Mask */ 288 289 #define MXC_F_CTB_CIPHER_CTRL_CCMM_POS 13 /**< CIPHER_CTRL_CCMM Position */ 290 #define MXC_F_CTB_CIPHER_CTRL_CCMM ((uint32_t)(0x7UL << MXC_F_CTB_CIPHER_CTRL_CCMM_POS)) /**< CIPHER_CTRL_CCMM Mask */ 291 292 #define MXC_F_CTB_CIPHER_CTRL_CCML_POS 16 /**< CIPHER_CTRL_CCML Position */ 293 #define MXC_F_CTB_CIPHER_CTRL_CCML ((uint32_t)(0x7UL << MXC_F_CTB_CIPHER_CTRL_CCML_POS)) /**< CIPHER_CTRL_CCML Mask */ 294 295 /**@} end of group CTB_CIPHER_CTRL_Register */ 296 297 /** 298 * @ingroup ctb_registers 299 * @defgroup CTB_HASH_CTRL CTB_HASH_CTRL 300 * @brief HASH Control Register. 301 * @{ 302 */ 303 #define MXC_F_CTB_HASH_CTRL_INIT_POS 0 /**< HASH_CTRL_INIT Position */ 304 #define MXC_F_CTB_HASH_CTRL_INIT ((uint32_t)(0x1UL << MXC_F_CTB_HASH_CTRL_INIT_POS)) /**< HASH_CTRL_INIT Mask */ 305 306 #define MXC_F_CTB_HASH_CTRL_XOR_POS 1 /**< HASH_CTRL_XOR Position */ 307 #define MXC_F_CTB_HASH_CTRL_XOR ((uint32_t)(0x1UL << MXC_F_CTB_HASH_CTRL_XOR_POS)) /**< HASH_CTRL_XOR Mask */ 308 309 #define MXC_F_CTB_HASH_CTRL_HASH_POS 2 /**< HASH_CTRL_HASH Position */ 310 #define MXC_F_CTB_HASH_CTRL_HASH ((uint32_t)(0x7UL << MXC_F_CTB_HASH_CTRL_HASH_POS)) /**< HASH_CTRL_HASH Mask */ 311 #define MXC_V_CTB_HASH_CTRL_HASH_DIS ((uint32_t)0x0UL) /**< HASH_CTRL_HASH_DIS Value */ 312 #define MXC_S_CTB_HASH_CTRL_HASH_DIS (MXC_V_CTB_HASH_CTRL_HASH_DIS << MXC_F_CTB_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_DIS Setting */ 313 #define MXC_V_CTB_HASH_CTRL_HASH_SHA1 ((uint32_t)0x1UL) /**< HASH_CTRL_HASH_SHA1 Value */ 314 #define MXC_S_CTB_HASH_CTRL_HASH_SHA1 (MXC_V_CTB_HASH_CTRL_HASH_SHA1 << MXC_F_CTB_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_SHA1 Setting */ 315 #define MXC_V_CTB_HASH_CTRL_HASH_SHA224 ((uint32_t)0x2UL) /**< HASH_CTRL_HASH_SHA224 Value */ 316 #define MXC_S_CTB_HASH_CTRL_HASH_SHA224 (MXC_V_CTB_HASH_CTRL_HASH_SHA224 << MXC_F_CTB_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_SHA224 Setting */ 317 #define MXC_V_CTB_HASH_CTRL_HASH_SHA256 ((uint32_t)0x3UL) /**< HASH_CTRL_HASH_SHA256 Value */ 318 #define MXC_S_CTB_HASH_CTRL_HASH_SHA256 (MXC_V_CTB_HASH_CTRL_HASH_SHA256 << MXC_F_CTB_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_SHA256 Setting */ 319 #define MXC_V_CTB_HASH_CTRL_HASH_SHA384 ((uint32_t)0x4UL) /**< HASH_CTRL_HASH_SHA384 Value */ 320 #define MXC_S_CTB_HASH_CTRL_HASH_SHA384 (MXC_V_CTB_HASH_CTRL_HASH_SHA384 << MXC_F_CTB_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_SHA384 Setting */ 321 #define MXC_V_CTB_HASH_CTRL_HASH_SHA512 ((uint32_t)0x5UL) /**< HASH_CTRL_HASH_SHA512 Value */ 322 #define MXC_S_CTB_HASH_CTRL_HASH_SHA512 (MXC_V_CTB_HASH_CTRL_HASH_SHA512 << MXC_F_CTB_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_SHA512 Setting */ 323 324 #define MXC_F_CTB_HASH_CTRL_LAST_POS 5 /**< HASH_CTRL_LAST Position */ 325 #define MXC_F_CTB_HASH_CTRL_LAST ((uint32_t)(0x1UL << MXC_F_CTB_HASH_CTRL_LAST_POS)) /**< HASH_CTRL_LAST Mask */ 326 327 /**@} end of group CTB_HASH_CTRL_Register */ 328 329 /** 330 * @ingroup ctb_registers 331 * @defgroup CTB_CRC_CTRL CTB_CRC_CTRL 332 * @brief CRC Control Register. 333 * @{ 334 */ 335 #define MXC_F_CTB_CRC_CTRL_CRC_POS 0 /**< CRC_CTRL_CRC Position */ 336 #define MXC_F_CTB_CRC_CTRL_CRC ((uint32_t)(0x1UL << MXC_F_CTB_CRC_CTRL_CRC_POS)) /**< CRC_CTRL_CRC Mask */ 337 338 #define MXC_F_CTB_CRC_CTRL_MSB_POS 1 /**< CRC_CTRL_MSB Position */ 339 #define MXC_F_CTB_CRC_CTRL_MSB ((uint32_t)(0x1UL << MXC_F_CTB_CRC_CTRL_MSB_POS)) /**< CRC_CTRL_MSB Mask */ 340 341 #define MXC_F_CTB_CRC_CTRL_PRNG_POS 2 /**< CRC_CTRL_PRNG Position */ 342 #define MXC_F_CTB_CRC_CTRL_PRNG ((uint32_t)(0x1UL << MXC_F_CTB_CRC_CTRL_PRNG_POS)) /**< CRC_CTRL_PRNG Mask */ 343 344 #define MXC_F_CTB_CRC_CTRL_ENT_POS 3 /**< CRC_CTRL_ENT Position */ 345 #define MXC_F_CTB_CRC_CTRL_ENT ((uint32_t)(0x1UL << MXC_F_CTB_CRC_CTRL_ENT_POS)) /**< CRC_CTRL_ENT Mask */ 346 347 #define MXC_F_CTB_CRC_CTRL_HAM_POS 4 /**< CRC_CTRL_HAM Position */ 348 #define MXC_F_CTB_CRC_CTRL_HAM ((uint32_t)(0x1UL << MXC_F_CTB_CRC_CTRL_HAM_POS)) /**< CRC_CTRL_HAM Mask */ 349 350 #define MXC_F_CTB_CRC_CTRL_HRST_POS 5 /**< CRC_CTRL_HRST Position */ 351 #define MXC_F_CTB_CRC_CTRL_HRST ((uint32_t)(0x1UL << MXC_F_CTB_CRC_CTRL_HRST_POS)) /**< CRC_CTRL_HRST Mask */ 352 353 /**@} end of group CTB_CRC_CTRL_Register */ 354 355 /** 356 * @ingroup ctb_registers 357 * @defgroup CTB_DMA_SRC CTB_DMA_SRC 358 * @brief Crypto DMA Source Address. 359 * @{ 360 */ 361 #define MXC_F_CTB_DMA_SRC_ADDR_POS 0 /**< DMA_SRC_ADDR Position */ 362 #define MXC_F_CTB_DMA_SRC_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_DMA_SRC_ADDR_POS)) /**< DMA_SRC_ADDR Mask */ 363 364 /**@} end of group CTB_DMA_SRC_Register */ 365 366 /** 367 * @ingroup ctb_registers 368 * @defgroup CTB_DMA_DEST CTB_DMA_DEST 369 * @brief Crypto DMA Destination Address. 370 * @{ 371 */ 372 #define MXC_F_CTB_DMA_DEST_ADDR_POS 0 /**< DMA_DEST_ADDR Position */ 373 #define MXC_F_CTB_DMA_DEST_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_DMA_DEST_ADDR_POS)) /**< DMA_DEST_ADDR Mask */ 374 375 /**@} end of group CTB_DMA_DEST_Register */ 376 377 /** 378 * @ingroup ctb_registers 379 * @defgroup CTB_DMA_CNT CTB_DMA_CNT 380 * @brief Crypto DMA Byte Count. 381 * @{ 382 */ 383 #define MXC_F_CTB_DMA_CNT_CNT_POS 0 /**< DMA_CNT_CNT Position */ 384 #define MXC_F_CTB_DMA_CNT_CNT ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_DMA_CNT_CNT_POS)) /**< DMA_CNT_CNT Mask */ 385 386 /**@} end of group CTB_DMA_CNT_Register */ 387 388 /** 389 * @ingroup ctb_registers 390 * @defgroup CTB_CRYPTO_DIN CTB_CRYPTO_DIN 391 * @brief Crypto Data Input. Data input can be written to this register instead of using 392 * the DMA. This register writes to the FIFO. This register occupies four 393 * successive words to allow the use of multi-store instructions. Words can be 394 * written to any location, they will be placed in the FIFO in the order they are 395 * written. The endian swap input control bit affects this register. 396 * @{ 397 */ 398 #define MXC_F_CTB_CRYPTO_DIN_DATA_POS 0 /**< CRYPTO_DIN_DATA Position */ 399 #define MXC_F_CTB_CRYPTO_DIN_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_CRYPTO_DIN_DATA_POS)) /**< CRYPTO_DIN_DATA Mask */ 400 401 /**@} end of group CTB_CRYPTO_DIN_Register */ 402 403 /** 404 * @ingroup ctb_registers 405 * @defgroup CTB_CRYPTO_DOUT CTB_CRYPTO_DOUT 406 * @brief Crypto Data Output. Resulting data from cipher calculation. Data is placed in 407 * the lower words of these four registers depending on the algorithm. For block 408 * cipher modes, this register holds the result of most recent encryption or 409 * decryption operation. These registers are affected by the endian swap bits. 410 * @{ 411 */ 412 #define MXC_F_CTB_CRYPTO_DOUT_DATA_POS 0 /**< CRYPTO_DOUT_DATA Position */ 413 #define MXC_F_CTB_CRYPTO_DOUT_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_CRYPTO_DOUT_DATA_POS)) /**< CRYPTO_DOUT_DATA Mask */ 414 415 /**@} end of group CTB_CRYPTO_DOUT_Register */ 416 417 /** 418 * @ingroup ctb_registers 419 * @defgroup CTB_CRC_POLY CTB_CRC_POLY 420 * @brief CRC Polynomial. The polynomial to be used for Galois Field calculations (CRC or 421 * LFSR) should be written to this register. This register is affected by the MSB 422 * control bit. 423 * @{ 424 */ 425 #define MXC_F_CTB_CRC_POLY_POLY_POS 0 /**< CRC_POLY_POLY Position */ 426 #define MXC_F_CTB_CRC_POLY_POLY ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_CRC_POLY_POLY_POS)) /**< CRC_POLY_POLY Mask */ 427 428 /**@} end of group CTB_CRC_POLY_Register */ 429 430 /** 431 * @ingroup ctb_registers 432 * @defgroup CTB_CRC_VAL CTB_CRC_VAL 433 * @brief CRC Value. This is the state for the Galois Field. This register holds the 434 * result of a CRC calculation or the current state of the LFSR. This register is 435 * affected by the MSB control bit. 436 * @{ 437 */ 438 #define MXC_F_CTB_CRC_VAL_VAL_POS 0 /**< CRC_VAL_VAL Position */ 439 #define MXC_F_CTB_CRC_VAL_VAL ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_CRC_VAL_VAL_POS)) /**< CRC_VAL_VAL Mask */ 440 441 /**@} end of group CTB_CRC_VAL_Register */ 442 443 /** 444 * @ingroup ctb_registers 445 * @defgroup CTB_CRC_PRNG CTB_CRC_PRNG 446 * @brief Pseudo-Random Number Generator. Output of the Galois Field shift register. This 447 * holds the resulting pseudo-random number if entropy is disabled or true random 448 * number if entropy is enabled. 449 * @{ 450 */ 451 #define MXC_F_CTB_CRC_PRNG_PRNG_POS 0 /**< CRC_PRNG_PRNG Position */ 452 #define MXC_F_CTB_CRC_PRNG_PRNG ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_CRC_PRNG_PRNG_POS)) /**< CRC_PRNG_PRNG Mask */ 453 454 /**@} end of group CTB_CRC_PRNG_Register */ 455 456 /** 457 * @ingroup ctb_registers 458 * @defgroup CTB_HAM_ECC CTB_HAM_ECC 459 * @brief Hamming ECC Register. 460 * @{ 461 */ 462 #define MXC_F_CTB_HAM_ECC_ECC_POS 0 /**< HAM_ECC_ECC Position */ 463 #define MXC_F_CTB_HAM_ECC_ECC ((uint32_t)(0xFFFFUL << MXC_F_CTB_HAM_ECC_ECC_POS)) /**< HAM_ECC_ECC Mask */ 464 465 #define MXC_F_CTB_HAM_ECC_PAR_POS 16 /**< HAM_ECC_PAR Position */ 466 #define MXC_F_CTB_HAM_ECC_PAR ((uint32_t)(0x1UL << MXC_F_CTB_HAM_ECC_PAR_POS)) /**< HAM_ECC_PAR Mask */ 467 468 /**@} end of group CTB_HAM_ECC_Register */ 469 470 /** 471 * @ingroup ctb_registers 472 * @defgroup CTB_CIPHER_INIT CTB_CIPHER_INIT 473 * @brief Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR 474 * modes, this register holds the initial value. This register is updated with each 475 * encryption or decryption operation. This register is affected by the endian swap 476 * bits. 477 * @{ 478 */ 479 #define MXC_F_CTB_CIPHER_INIT_IVEC_POS 0 /**< CIPHER_INIT_IVEC Position */ 480 #define MXC_F_CTB_CIPHER_INIT_IVEC ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_CIPHER_INIT_IVEC_POS)) /**< CIPHER_INIT_IVEC Mask */ 481 482 /**@} end of group CTB_CIPHER_INIT_Register */ 483 484 /** 485 * @ingroup ctb_registers 486 * @defgroup CTB_CIPHER_KEY CTB_CIPHER_KEY 487 * @brief Cipher Key. This register holds the key used for block cipher operations. The 488 * lower words are used for block ciphers that use shorter key lengths. This 489 * register is affected by the endian swap input control bits. 490 * @{ 491 */ 492 #define MXC_F_CTB_CIPHER_KEY_KEY_POS 0 /**< CIPHER_KEY_KEY Position */ 493 #define MXC_F_CTB_CIPHER_KEY_KEY ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_CIPHER_KEY_KEY_POS)) /**< CIPHER_KEY_KEY Mask */ 494 495 /**@} end of group CTB_CIPHER_KEY_Register */ 496 497 /** 498 * @ingroup ctb_registers 499 * @defgroup CTB_HASH_DIGEST CTB_HASH_DIGEST 500 * @brief This register holds the calculated hash value. This register is affected by the 501 * endian swap bits. 502 * @{ 503 */ 504 #define MXC_F_CTB_HASH_DIGEST_HASH_POS 0 /**< HASH_DIGEST_HASH Position */ 505 #define MXC_F_CTB_HASH_DIGEST_HASH ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_HASH_DIGEST_HASH_POS)) /**< HASH_DIGEST_HASH Mask */ 506 507 /**@} end of group CTB_HASH_DIGEST_Register */ 508 509 /** 510 * @ingroup ctb_registers 511 * @defgroup CTB_HASH_MSG_SZ CTB_HASH_MSG_SZ 512 * @brief Message Size. This register holds the lowest 32-bit of message size in bytes. 513 * @{ 514 */ 515 #define MXC_F_CTB_HASH_MSG_SZ_MSGSZ_POS 0 /**< HASH_MSG_SZ_MSGSZ Position */ 516 #define MXC_F_CTB_HASH_MSG_SZ_MSGSZ ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_HASH_MSG_SZ_MSGSZ_POS)) /**< HASH_MSG_SZ_MSGSZ Mask */ 517 518 /**@} end of group CTB_HASH_MSG_SZ_Register */ 519 520 /** 521 * @ingroup ctb_registers 522 * @defgroup CTB_A_LENGTH_0 CTB_A_LENGTH_0 523 * @brief .AAD Length Register 0. 524 * @{ 525 */ 526 #define MXC_F_CTB_A_LENGTH_0_A_LENGTH_POS 0 /**< A_LENGTH_0_A_LENGTH Position */ 527 #define MXC_F_CTB_A_LENGTH_0_A_LENGTH ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_A_LENGTH_0_A_LENGTH_POS)) /**< A_LENGTH_0_A_LENGTH Mask */ 528 529 /**@} end of group CTB_A_LENGTH_0_Register */ 530 531 /** 532 * @ingroup ctb_registers 533 * @defgroup CTB_A_LENGTH_1 CTB_A_LENGTH_1 534 * @brief .AAD Length Register 1. 535 * @{ 536 */ 537 #define MXC_F_CTB_A_LENGTH_1_A_LENGTH_POS 0 /**< A_LENGTH_1_A_LENGTH Position */ 538 #define MXC_F_CTB_A_LENGTH_1_A_LENGTH ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_A_LENGTH_1_A_LENGTH_POS)) /**< A_LENGTH_1_A_LENGTH Mask */ 539 540 /**@} end of group CTB_A_LENGTH_1_Register */ 541 542 /** 543 * @ingroup ctb_registers 544 * @defgroup CTB_PLD_LENGTH_0 CTB_PLD_LENGTH_0 545 * @brief .PLD Length Register 0. 546 * @{ 547 */ 548 #define MXC_F_CTB_PLD_LENGTH_0_PLD_LENGTH_POS 0 /**< PLD_LENGTH_0_PLD_LENGTH Position */ 549 #define MXC_F_CTB_PLD_LENGTH_0_PLD_LENGTH ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_PLD_LENGTH_0_PLD_LENGTH_POS)) /**< PLD_LENGTH_0_PLD_LENGTH Mask */ 550 551 /**@} end of group CTB_PLD_LENGTH_0_Register */ 552 553 /** 554 * @ingroup ctb_registers 555 * @defgroup CTB_PLD_LENGTH_1 CTB_PLD_LENGTH_1 556 * @brief .LENGTH. 557 * @{ 558 */ 559 #define MXC_F_CTB_PLD_LENGTH_1_PLD_LENGTH_POS 0 /**< PLD_LENGTH_1_PLD_LENGTH Position */ 560 #define MXC_F_CTB_PLD_LENGTH_1_PLD_LENGTH ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_PLD_LENGTH_1_PLD_LENGTH_POS)) /**< PLD_LENGTH_1_PLD_LENGTH Mask */ 561 562 /**@} end of group CTB_PLD_LENGTH_1_Register */ 563 564 /** 565 * @ingroup ctb_registers 566 * @defgroup CTB_TAGMIC CTB_TAGMIC 567 * @brief TAG/MIC Registers. 568 * @{ 569 */ 570 #define MXC_F_CTB_TAGMIC_TAGMIC_POS 0 /**< TAGMIC_TAGMIC Position */ 571 #define MXC_F_CTB_TAGMIC_TAGMIC ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_TAGMIC_TAGMIC_POS)) /**< TAGMIC_TAGMIC Mask */ 572 573 /**@} end of group CTB_TAGMIC_Register */ 574 575 /** 576 * @ingroup ctb_registers 577 * @defgroup CTB_SCA_CN CTB_SCA_CN 578 * @brief SCA Control 0 Register. 579 * @{ 580 */ 581 #define MXC_F_CTB_SCA_CN_STC_POS 0 /**< SCA_CN_STC Position */ 582 #define MXC_F_CTB_SCA_CN_STC ((uint32_t)(0x1UL << MXC_F_CTB_SCA_CN_STC_POS)) /**< SCA_CN_STC Mask */ 583 584 #define MXC_F_CTB_SCA_CN_SCAIE_POS 1 /**< SCA_CN_SCAIE Position */ 585 #define MXC_F_CTB_SCA_CN_SCAIE ((uint32_t)(0x1UL << MXC_F_CTB_SCA_CN_SCAIE_POS)) /**< SCA_CN_SCAIE Mask */ 586 587 #define MXC_F_CTB_SCA_CN_ABORT_POS 2 /**< SCA_CN_ABORT Position */ 588 #define MXC_F_CTB_SCA_CN_ABORT ((uint32_t)(0x1UL << MXC_F_CTB_SCA_CN_ABORT_POS)) /**< SCA_CN_ABORT Mask */ 589 590 #define MXC_F_CTB_SCA_CN_ERMEM_POS 4 /**< SCA_CN_ERMEM Position */ 591 #define MXC_F_CTB_SCA_CN_ERMEM ((uint32_t)(0x1UL << MXC_F_CTB_SCA_CN_ERMEM_POS)) /**< SCA_CN_ERMEM Mask */ 592 593 #define MXC_F_CTB_SCA_CN_MANPARAM_POS 5 /**< SCA_CN_MANPARAM Position */ 594 #define MXC_F_CTB_SCA_CN_MANPARAM ((uint32_t)(0x1UL << MXC_F_CTB_SCA_CN_MANPARAM_POS)) /**< SCA_CN_MANPARAM Mask */ 595 596 #define MXC_F_CTB_SCA_CN_HWKEY_POS 6 /**< SCA_CN_HWKEY Position */ 597 #define MXC_F_CTB_SCA_CN_HWKEY ((uint32_t)(0x1UL << MXC_F_CTB_SCA_CN_HWKEY_POS)) /**< SCA_CN_HWKEY Mask */ 598 599 #define MXC_F_CTB_SCA_CN_OPCODE_POS 8 /**< SCA_CN_OPCODE Position */ 600 #define MXC_F_CTB_SCA_CN_OPCODE ((uint32_t)(0x1FUL << MXC_F_CTB_SCA_CN_OPCODE_POS)) /**< SCA_CN_OPCODE Mask */ 601 602 #define MXC_F_CTB_SCA_CN_MODADDR_POS 16 /**< SCA_CN_MODADDR Position */ 603 #define MXC_F_CTB_SCA_CN_MODADDR ((uint32_t)(0x1FUL << MXC_F_CTB_SCA_CN_MODADDR_POS)) /**< SCA_CN_MODADDR Mask */ 604 605 #define MXC_F_CTB_SCA_CN_ECCSIZE_POS 24 /**< SCA_CN_ECCSIZE Position */ 606 #define MXC_F_CTB_SCA_CN_ECCSIZE ((uint32_t)(0x3UL << MXC_F_CTB_SCA_CN_ECCSIZE_POS)) /**< SCA_CN_ECCSIZE Mask */ 607 608 /**@} end of group CTB_SCA_CN_Register */ 609 610 /** 611 * @ingroup ctb_registers 612 * @defgroup CTB_SCA_ACN CTB_SCA_ACN 613 * @brief SCA Advanced Control Register. 614 * @{ 615 */ 616 #define MXC_F_CTB_SCA_ACN_MAN_POS 0 /**< SCA_ACN_MAN Position */ 617 #define MXC_F_CTB_SCA_ACN_MAN ((uint32_t)(0x1UL << MXC_F_CTB_SCA_ACN_MAN_POS)) /**< SCA_ACN_MAN Mask */ 618 619 #define MXC_F_CTB_SCA_ACN_AUTOCARRY_POS 1 /**< SCA_ACN_AUTOCARRY Position */ 620 #define MXC_F_CTB_SCA_ACN_AUTOCARRY ((uint32_t)(0x1UL << MXC_F_CTB_SCA_ACN_AUTOCARRY_POS)) /**< SCA_ACN_AUTOCARRY Mask */ 621 622 #define MXC_F_CTB_SCA_ACN_PLUSONE_POS 2 /**< SCA_ACN_PLUSONE Position */ 623 #define MXC_F_CTB_SCA_ACN_PLUSONE ((uint32_t)(0x1UL << MXC_F_CTB_SCA_ACN_PLUSONE_POS)) /**< SCA_ACN_PLUSONE Mask */ 624 625 #define MXC_F_CTB_SCA_ACN_RESSELECT_POS 3 /**< SCA_ACN_RESSELECT Position */ 626 #define MXC_F_CTB_SCA_ACN_RESSELECT ((uint32_t)(0x3UL << MXC_F_CTB_SCA_ACN_RESSELECT_POS)) /**< SCA_ACN_RESSELECT Mask */ 627 628 #define MXC_F_CTB_SCA_ACN_CARRYPOS_POS 8 /**< SCA_ACN_CARRYPOS Position */ 629 #define MXC_F_CTB_SCA_ACN_CARRYPOS ((uint32_t)(0x3FFUL << MXC_F_CTB_SCA_ACN_CARRYPOS_POS)) /**< SCA_ACN_CARRYPOS Mask */ 630 631 /**@} end of group CTB_SCA_ACN_Register */ 632 633 /** 634 * @ingroup ctb_registers 635 * @defgroup CTB_SCA_ST CTB_SCA_ST 636 * @brief SCA Status Register. 637 * @{ 638 */ 639 #define MXC_F_CTB_SCA_ST_BUSY_POS 0 /**< SCA_ST_BUSY Position */ 640 #define MXC_F_CTB_SCA_ST_BUSY ((uint32_t)(0x1UL << MXC_F_CTB_SCA_ST_BUSY_POS)) /**< SCA_ST_BUSY Mask */ 641 642 #define MXC_F_CTB_SCA_ST_SCAIF_POS 1 /**< SCA_ST_SCAIF Position */ 643 #define MXC_F_CTB_SCA_ST_SCAIF ((uint32_t)(0x1UL << MXC_F_CTB_SCA_ST_SCAIF_POS)) /**< SCA_ST_SCAIF Mask */ 644 645 #define MXC_F_CTB_SCA_ST_PVF1_POS 2 /**< SCA_ST_PVF1 Position */ 646 #define MXC_F_CTB_SCA_ST_PVF1 ((uint32_t)(0x1UL << MXC_F_CTB_SCA_ST_PVF1_POS)) /**< SCA_ST_PVF1 Mask */ 647 648 #define MXC_F_CTB_SCA_ST_PVF2_POS 3 /**< SCA_ST_PVF2 Position */ 649 #define MXC_F_CTB_SCA_ST_PVF2 ((uint32_t)(0x1UL << MXC_F_CTB_SCA_ST_PVF2_POS)) /**< SCA_ST_PVF2 Mask */ 650 651 #define MXC_F_CTB_SCA_ST_FSMERR_POS 4 /**< SCA_ST_FSMERR Position */ 652 #define MXC_F_CTB_SCA_ST_FSMERR ((uint32_t)(0x1UL << MXC_F_CTB_SCA_ST_FSMERR_POS)) /**< SCA_ST_FSMERR Mask */ 653 654 #define MXC_F_CTB_SCA_ST_COMPERR_POS 5 /**< SCA_ST_COMPERR Position */ 655 #define MXC_F_CTB_SCA_ST_COMPERR ((uint32_t)(0x1UL << MXC_F_CTB_SCA_ST_COMPERR_POS)) /**< SCA_ST_COMPERR Mask */ 656 657 #define MXC_F_CTB_SCA_ST_MEMERR_POS 6 /**< SCA_ST_MEMERR Position */ 658 #define MXC_F_CTB_SCA_ST_MEMERR ((uint32_t)(0x1UL << MXC_F_CTB_SCA_ST_MEMERR_POS)) /**< SCA_ST_MEMERR Mask */ 659 660 #define MXC_F_CTB_SCA_ST_CARRY_POS 8 /**< SCA_ST_CARRY Position */ 661 #define MXC_F_CTB_SCA_ST_CARRY ((uint32_t)(0x1UL << MXC_F_CTB_SCA_ST_CARRY_POS)) /**< SCA_ST_CARRY Mask */ 662 663 #define MXC_F_CTB_SCA_ST_GTE2I2_POS 9 /**< SCA_ST_GTE2I2 Position */ 664 #define MXC_F_CTB_SCA_ST_GTE2I2 ((uint32_t)(0x1UL << MXC_F_CTB_SCA_ST_GTE2I2_POS)) /**< SCA_ST_GTE2I2 Mask */ 665 666 #define MXC_F_CTB_SCA_ST_ALUNEG1_POS 10 /**< SCA_ST_ALUNEG1 Position */ 667 #define MXC_F_CTB_SCA_ST_ALUNEG1 ((uint32_t)(0x1UL << MXC_F_CTB_SCA_ST_ALUNEG1_POS)) /**< SCA_ST_ALUNEG1 Mask */ 668 669 #define MXC_F_CTB_SCA_ST_ALUNEG2_POS 11 /**< SCA_ST_ALUNEG2 Position */ 670 #define MXC_F_CTB_SCA_ST_ALUNEG2 ((uint32_t)(0x1UL << MXC_F_CTB_SCA_ST_ALUNEG2_POS)) /**< SCA_ST_ALUNEG2 Mask */ 671 672 /**@} end of group CTB_SCA_ST_Register */ 673 674 /** 675 * @ingroup ctb_registers 676 * @defgroup CTB_SCA_PPX_ADDR CTB_SCA_PPX_ADDR 677 * @brief PPX Coordinate Data Pointer Register. 678 * @{ 679 */ 680 #define MXC_F_CTB_SCA_PPX_ADDR_PPX_ADDR_POS 0 /**< SCA_PPX_ADDR_PPX_ADDR Position */ 681 #define MXC_F_CTB_SCA_PPX_ADDR_PPX_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_SCA_PPX_ADDR_PPX_ADDR_POS)) /**< SCA_PPX_ADDR_PPX_ADDR Mask */ 682 683 /**@} end of group CTB_SCA_PPX_ADDR_Register */ 684 685 /** 686 * @ingroup ctb_registers 687 * @defgroup CTB_SCA_PPY_ADDR CTB_SCA_PPY_ADDR 688 * @brief PPY Coordinate Data Pointer Register. 689 * @{ 690 */ 691 #define MXC_F_CTB_SCA_PPY_ADDR_PPY_ADDR_POS 0 /**< SCA_PPY_ADDR_PPY_ADDR Position */ 692 #define MXC_F_CTB_SCA_PPY_ADDR_PPY_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_SCA_PPY_ADDR_PPY_ADDR_POS)) /**< SCA_PPY_ADDR_PPY_ADDR Mask */ 693 694 /**@} end of group CTB_SCA_PPY_ADDR_Register */ 695 696 /** 697 * @ingroup ctb_registers 698 * @defgroup CTB_SCA_PPZ_ADDR CTB_SCA_PPZ_ADDR 699 * @brief PPZ Coordinate Data Pointer Register. 700 * @{ 701 */ 702 #define MXC_F_CTB_SCA_PPZ_ADDR_PPZ_ADDR_POS 0 /**< SCA_PPZ_ADDR_PPZ_ADDR Position */ 703 #define MXC_F_CTB_SCA_PPZ_ADDR_PPZ_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_SCA_PPZ_ADDR_PPZ_ADDR_POS)) /**< SCA_PPZ_ADDR_PPZ_ADDR Mask */ 704 705 /**@} end of group CTB_SCA_PPZ_ADDR_Register */ 706 707 /** 708 * @ingroup ctb_registers 709 * @defgroup CTB_SCA_PQX_ADDR CTB_SCA_PQX_ADDR 710 * @brief PQX Coordinate Data Pointer Register. 711 * @{ 712 */ 713 #define MXC_F_CTB_SCA_PQX_ADDR_PQX_ADDR_POS 0 /**< SCA_PQX_ADDR_PQX_ADDR Position */ 714 #define MXC_F_CTB_SCA_PQX_ADDR_PQX_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_SCA_PQX_ADDR_PQX_ADDR_POS)) /**< SCA_PQX_ADDR_PQX_ADDR Mask */ 715 716 /**@} end of group CTB_SCA_PQX_ADDR_Register */ 717 718 /** 719 * @ingroup ctb_registers 720 * @defgroup CTB_SCA_PQY_ADDR CTB_SCA_PQY_ADDR 721 * @brief PQY Coordinate Data Pointer Register. 722 * @{ 723 */ 724 #define MXC_F_CTB_SCA_PQY_ADDR_PQY_ADDR_POS 0 /**< SCA_PQY_ADDR_PQY_ADDR Position */ 725 #define MXC_F_CTB_SCA_PQY_ADDR_PQY_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_SCA_PQY_ADDR_PQY_ADDR_POS)) /**< SCA_PQY_ADDR_PQY_ADDR Mask */ 726 727 /**@} end of group CTB_SCA_PQY_ADDR_Register */ 728 729 /** 730 * @ingroup ctb_registers 731 * @defgroup CTB_SCA_PQZ_ADDR CTB_SCA_PQZ_ADDR 732 * @brief PQZ Coordinate Data Pointer Register. 733 * @{ 734 */ 735 #define MXC_F_CTB_SCA_PQZ_ADDR_PQZ_ADDR_POS 0 /**< SCA_PQZ_ADDR_PQZ_ADDR Position */ 736 #define MXC_F_CTB_SCA_PQZ_ADDR_PQZ_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_SCA_PQZ_ADDR_PQZ_ADDR_POS)) /**< SCA_PQZ_ADDR_PQZ_ADDR Mask */ 737 738 /**@} end of group CTB_SCA_PQZ_ADDR_Register */ 739 740 /** 741 * @ingroup ctb_registers 742 * @defgroup CTB_SCA_RDSA_ADDR CTB_SCA_RDSA_ADDR 743 * @brief SCA RDSA Address Register. 744 * @{ 745 */ 746 #define MXC_F_CTB_SCA_RDSA_ADDR_RDSA_ADDR_POS 0 /**< SCA_RDSA_ADDR_RDSA_ADDR Position */ 747 #define MXC_F_CTB_SCA_RDSA_ADDR_RDSA_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_SCA_RDSA_ADDR_RDSA_ADDR_POS)) /**< SCA_RDSA_ADDR_RDSA_ADDR Mask */ 748 749 /**@} end of group CTB_SCA_RDSA_ADDR_Register */ 750 751 /** 752 * @ingroup ctb_registers 753 * @defgroup CTB_SCA_RES_ADDR CTB_SCA_RES_ADDR 754 * @brief SCA Result Address Register. 755 * @{ 756 */ 757 #define MXC_F_CTB_SCA_RES_ADDR_RES_ADDR_POS 0 /**< SCA_RES_ADDR_RES_ADDR Position */ 758 #define MXC_F_CTB_SCA_RES_ADDR_RES_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_SCA_RES_ADDR_RES_ADDR_POS)) /**< SCA_RES_ADDR_RES_ADDR Mask */ 759 760 /**@} end of group CTB_SCA_RES_ADDR_Register */ 761 762 /** 763 * @ingroup ctb_registers 764 * @defgroup CTB_SCA_OP_BUFF_ADDR CTB_SCA_OP_BUFF_ADDR 765 * @brief SCA Operation Buffer Address Register. 766 * @{ 767 */ 768 #define MXC_F_CTB_SCA_OP_BUFF_ADDR_OPBUFF_ADDR_POS 0 /**< SCA_OP_BUFF_ADDR_OPBUFF_ADDR Position */ 769 #define MXC_F_CTB_SCA_OP_BUFF_ADDR_OPBUFF_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_SCA_OP_BUFF_ADDR_OPBUFF_ADDR_POS)) /**< SCA_OP_BUFF_ADDR_OPBUFF_ADDR Mask */ 770 771 /**@} end of group CTB_SCA_OP_BUFF_ADDR_Register */ 772 773 /** 774 * @ingroup ctb_registers 775 * @defgroup CTB_SCA_MODDATA CTB_SCA_MODDATA 776 * @brief SCA Modulo Data Input Register. 777 * @{ 778 */ 779 #define MXC_F_CTB_SCA_MODDATA_MODDATA_POS 0 /**< SCA_MODDATA_MODDATA Position */ 780 #define MXC_F_CTB_SCA_MODDATA_MODDATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_CTB_SCA_MODDATA_MODDATA_POS)) /**< SCA_MODDATA_MODDATA Mask */ 781 782 /**@} end of group CTB_SCA_MODDATA_Register */ 783 784 #ifdef __cplusplus 785 } 786 #endif 787 788 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32520_INCLUDE_CTB_REGS_H_ 789
