1 /** 2 * @file tpu_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the TPU Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup tpu_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_TPU_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_TPU_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup tpu 67 * @defgroup tpu_registers TPU_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the TPU Peripheral Module. 69 * @details The Trust Protection Unit used to assist the computationally intensive operations of several common cryptographic algorithms. 70 */ 71 72 /** 73 * @ingroup tpu_registers 74 * Structure type to access the TPU Registers. 75 */ 76 typedef struct { 77 __IO uint32_t ctrl; /**< <tt>\b 0x00:</tt> TPU CTRL Register */ 78 __IO uint32_t cipher_ctrl; /**< <tt>\b 0x04:</tt> TPU CIPHER_CTRL Register */ 79 __IO uint32_t hash_ctrl; /**< <tt>\b 0x08:</tt> TPU HASH_CTRL Register */ 80 __IO uint32_t crc_ctrl; /**< <tt>\b 0x0C:</tt> TPU CRC_CTRL Register */ 81 __IO uint32_t dma_src; /**< <tt>\b 0x10:</tt> TPU DMA_SRC Register */ 82 __IO uint32_t dma_dst; /**< <tt>\b 0x14:</tt> TPU DMA_DST Register */ 83 __IO uint32_t dma_cnt; /**< <tt>\b 0x18:</tt> TPU DMA_CNT Register */ 84 __IO uint32_t maa_ctrl; /**< <tt>\b 0x1C:</tt> TPU MAA_CTRL Register */ 85 __O uint32_t data_in[4]; /**< <tt>\b 0x20:</tt> TPU DATA_IN Register */ 86 __I uint32_t data_out[4]; /**< <tt>\b 0x30:</tt> TPU DATA_OUT Register */ 87 __IO uint32_t crc_poly; /**< <tt>\b 0x40:</tt> TPU CRC_POLY Register */ 88 __IO uint32_t crc_val; /**< <tt>\b 0x44:</tt> TPU CRC_VAL Register */ 89 __I uint32_t crc_prng; /**< <tt>\b 0x48:</tt> TPU CRC_PRNG Register */ 90 __IO uint32_t ham_ecc; /**< <tt>\b 0x4C:</tt> TPU HAM_ECC Register */ 91 __IO uint32_t cipher_init[4]; /**< <tt>\b 0x50:</tt> TPU CIPHER_INIT Register */ 92 __O uint32_t cipher_key[8]; /**< <tt>\b 0x60:</tt> TPU CIPHER_KEY Register */ 93 __IO uint32_t hash_digest[16]; /**< <tt>\b 0x80:</tt> TPU HASH_DIGEST Register */ 94 __IO uint32_t hash_msg_sz[4]; /**< <tt>\b 0xC0:</tt> TPU HASH_MSG_SZ Register */ 95 __IO uint32_t maa_maws; /**< <tt>\b 0xD0:</tt> TPU MAA_MAWS Register */ 96 } mxc_tpu_regs_t; 97 98 /* Register offsets for module TPU */ 99 /** 100 * @ingroup tpu_registers 101 * @defgroup TPU_Register_Offsets Register Offsets 102 * @brief TPU Peripheral Register Offsets from the TPU Base Peripheral Address. 103 * @{ 104 */ 105 #define MXC_R_TPU_CTRL ((uint32_t)0x00000000UL) /**< Offset from TPU Base Address: <tt> 0x0000</tt> */ 106 #define MXC_R_TPU_CIPHER_CTRL ((uint32_t)0x00000004UL) /**< Offset from TPU Base Address: <tt> 0x0004</tt> */ 107 #define MXC_R_TPU_HASH_CTRL ((uint32_t)0x00000008UL) /**< Offset from TPU Base Address: <tt> 0x0008</tt> */ 108 #define MXC_R_TPU_CRC_CTRL ((uint32_t)0x0000000CUL) /**< Offset from TPU Base Address: <tt> 0x000C</tt> */ 109 #define MXC_R_TPU_DMA_SRC ((uint32_t)0x00000010UL) /**< Offset from TPU Base Address: <tt> 0x0010</tt> */ 110 #define MXC_R_TPU_DMA_DST ((uint32_t)0x00000014UL) /**< Offset from TPU Base Address: <tt> 0x0014</tt> */ 111 #define MXC_R_TPU_DMA_CNT ((uint32_t)0x00000018UL) /**< Offset from TPU Base Address: <tt> 0x0018</tt> */ 112 #define MXC_R_TPU_MAA_CTRL ((uint32_t)0x0000001CUL) /**< Offset from TPU Base Address: <tt> 0x001C</tt> */ 113 #define MXC_R_TPU_DATA_IN ((uint32_t)0x00000020UL) /**< Offset from TPU Base Address: <tt> 0x0020</tt> */ 114 #define MXC_R_TPU_DATA_OUT ((uint32_t)0x00000030UL) /**< Offset from TPU Base Address: <tt> 0x0030</tt> */ 115 #define MXC_R_TPU_CRC_POLY ((uint32_t)0x00000040UL) /**< Offset from TPU Base Address: <tt> 0x0040</tt> */ 116 #define MXC_R_TPU_CRC_VAL ((uint32_t)0x00000044UL) /**< Offset from TPU Base Address: <tt> 0x0044</tt> */ 117 #define MXC_R_TPU_CRC_PRNG ((uint32_t)0x00000048UL) /**< Offset from TPU Base Address: <tt> 0x0048</tt> */ 118 #define MXC_R_TPU_HAM_ECC ((uint32_t)0x0000004CUL) /**< Offset from TPU Base Address: <tt> 0x004C</tt> */ 119 #define MXC_R_TPU_CIPHER_INIT ((uint32_t)0x00000050UL) /**< Offset from TPU Base Address: <tt> 0x0050</tt> */ 120 #define MXC_R_TPU_CIPHER_KEY ((uint32_t)0x00000060UL) /**< Offset from TPU Base Address: <tt> 0x0060</tt> */ 121 #define MXC_R_TPU_HASH_DIGEST ((uint32_t)0x00000080UL) /**< Offset from TPU Base Address: <tt> 0x0080</tt> */ 122 #define MXC_R_TPU_HASH_MSG_SZ ((uint32_t)0x000000C0UL) /**< Offset from TPU Base Address: <tt> 0x00C0</tt> */ 123 #define MXC_R_TPU_MAA_MAWS ((uint32_t)0x000000D0UL) /**< Offset from TPU Base Address: <tt> 0x00D0</tt> */ 124 /**@} end of group tpu_registers */ 125 126 /** 127 * @ingroup tpu_registers 128 * @defgroup TPU_CTRL TPU_CTRL 129 * @brief Crypto Control Register. 130 * @{ 131 */ 132 #define MXC_F_TPU_CTRL_RST_POS 0 /**< CTRL_RST Position */ 133 #define MXC_F_TPU_CTRL_RST ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_RST_POS)) /**< CTRL_RST Mask */ 134 135 #define MXC_F_TPU_CTRL_INT_POS 1 /**< CTRL_INT Position */ 136 #define MXC_F_TPU_CTRL_INT ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_INT_POS)) /**< CTRL_INT Mask */ 137 138 #define MXC_F_TPU_CTRL_SRC_POS 2 /**< CTRL_SRC Position */ 139 #define MXC_F_TPU_CTRL_SRC ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_SRC_POS)) /**< CTRL_SRC Mask */ 140 141 #define MXC_F_TPU_CTRL_BSO_POS 4 /**< CTRL_BSO Position */ 142 #define MXC_F_TPU_CTRL_BSO ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_BSO_POS)) /**< CTRL_BSO Mask */ 143 144 #define MXC_F_TPU_CTRL_BSI_POS 5 /**< CTRL_BSI Position */ 145 #define MXC_F_TPU_CTRL_BSI ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_BSI_POS)) /**< CTRL_BSI Mask */ 146 147 #define MXC_F_TPU_CTRL_WAIT_EN_POS 6 /**< CTRL_WAIT_EN Position */ 148 #define MXC_F_TPU_CTRL_WAIT_EN ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_WAIT_EN_POS)) /**< CTRL_WAIT_EN Mask */ 149 150 #define MXC_F_TPU_CTRL_WAIT_POL_POS 7 /**< CTRL_WAIT_POL Position */ 151 #define MXC_F_TPU_CTRL_WAIT_POL ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_WAIT_POL_POS)) /**< CTRL_WAIT_POL Mask */ 152 153 #define MXC_F_TPU_CTRL_WRSRC_POS 8 /**< CTRL_WRSRC Position */ 154 #define MXC_F_TPU_CTRL_WRSRC ((uint32_t)(0x3UL << MXC_F_TPU_CTRL_WRSRC_POS)) /**< CTRL_WRSRC Mask */ 155 #define MXC_V_TPU_CTRL_WRSRC_NONE ((uint32_t)0x0UL) /**< CTRL_WRSRC_NONE Value */ 156 #define MXC_S_TPU_CTRL_WRSRC_NONE (MXC_V_TPU_CTRL_WRSRC_NONE << MXC_F_TPU_CTRL_WRSRC_POS) /**< CTRL_WRSRC_NONE Setting */ 157 #define MXC_V_TPU_CTRL_WRSRC_CIPHEROUTPUT ((uint32_t)0x1UL) /**< CTRL_WRSRC_CIPHEROUTPUT Value */ 158 #define MXC_S_TPU_CTRL_WRSRC_CIPHEROUTPUT (MXC_V_TPU_CTRL_WRSRC_CIPHEROUTPUT << MXC_F_TPU_CTRL_WRSRC_POS) /**< CTRL_WRSRC_CIPHEROUTPUT Setting */ 159 #define MXC_V_TPU_CTRL_WRSRC_READFIFO ((uint32_t)0x2UL) /**< CTRL_WRSRC_READFIFO Value */ 160 #define MXC_S_TPU_CTRL_WRSRC_READFIFO (MXC_V_TPU_CTRL_WRSRC_READFIFO << MXC_F_TPU_CTRL_WRSRC_POS) /**< CTRL_WRSRC_READFIFO Setting */ 161 162 #define MXC_F_TPU_CTRL_RDSRC_POS 10 /**< CTRL_RDSRC Position */ 163 #define MXC_F_TPU_CTRL_RDSRC ((uint32_t)(0x3UL << MXC_F_TPU_CTRL_RDSRC_POS)) /**< CTRL_RDSRC Mask */ 164 #define MXC_V_TPU_CTRL_RDSRC_DMADISABLED ((uint32_t)0x0UL) /**< CTRL_RDSRC_DMADISABLED Value */ 165 #define MXC_S_TPU_CTRL_RDSRC_DMADISABLED (MXC_V_TPU_CTRL_RDSRC_DMADISABLED << MXC_F_TPU_CTRL_RDSRC_POS) /**< CTRL_RDSRC_DMADISABLED Setting */ 166 #define MXC_V_TPU_CTRL_RDSRC_DMAORAPB ((uint32_t)0x1UL) /**< CTRL_RDSRC_DMAORAPB Value */ 167 #define MXC_S_TPU_CTRL_RDSRC_DMAORAPB (MXC_V_TPU_CTRL_RDSRC_DMAORAPB << MXC_F_TPU_CTRL_RDSRC_POS) /**< CTRL_RDSRC_DMAORAPB Setting */ 168 #define MXC_V_TPU_CTRL_RDSRC_RNG ((uint32_t)0x2UL) /**< CTRL_RDSRC_RNG Value */ 169 #define MXC_S_TPU_CTRL_RDSRC_RNG (MXC_V_TPU_CTRL_RDSRC_RNG << MXC_F_TPU_CTRL_RDSRC_POS) /**< CTRL_RDSRC_RNG Setting */ 170 171 #define MXC_F_TPU_CTRL_FLAG_MODE_POS 14 /**< CTRL_FLAG_MODE Position */ 172 #define MXC_F_TPU_CTRL_FLAG_MODE ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_FLAG_MODE_POS)) /**< CTRL_FLAG_MODE Mask */ 173 174 #define MXC_F_TPU_CTRL_DMADNE_MSK_POS 15 /**< CTRL_DMADNE_MSK Position */ 175 #define MXC_F_TPU_CTRL_DMADNE_MSK ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_DMADNE_MSK_POS)) /**< CTRL_DMADNE_MSK Mask */ 176 177 #define MXC_F_TPU_CTRL_DMA_DONE_POS 24 /**< CTRL_DMA_DONE Position */ 178 #define MXC_F_TPU_CTRL_DMA_DONE ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_DMA_DONE_POS)) /**< CTRL_DMA_DONE Mask */ 179 180 #define MXC_F_TPU_CTRL_GLS_DONE_POS 25 /**< CTRL_GLS_DONE Position */ 181 #define MXC_F_TPU_CTRL_GLS_DONE ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_GLS_DONE_POS)) /**< CTRL_GLS_DONE Mask */ 182 183 #define MXC_F_TPU_CTRL_HSH_DONE_POS 26 /**< CTRL_HSH_DONE Position */ 184 #define MXC_F_TPU_CTRL_HSH_DONE ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_HSH_DONE_POS)) /**< CTRL_HSH_DONE Mask */ 185 186 #define MXC_F_TPU_CTRL_CPH_DONE_POS 27 /**< CTRL_CPH_DONE Position */ 187 #define MXC_F_TPU_CTRL_CPH_DONE ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_CPH_DONE_POS)) /**< CTRL_CPH_DONE Mask */ 188 189 #define MXC_F_TPU_CTRL_MAA_DONE_POS 28 /**< CTRL_MAA_DONE Position */ 190 #define MXC_F_TPU_CTRL_MAA_DONE ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_MAA_DONE_POS)) /**< CTRL_MAA_DONE Mask */ 191 192 #define MXC_F_TPU_CTRL_ERR_POS 29 /**< CTRL_ERR Position */ 193 #define MXC_F_TPU_CTRL_ERR ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_ERR_POS)) /**< CTRL_ERR Mask */ 194 195 #define MXC_F_TPU_CTRL_RDY_POS 30 /**< CTRL_RDY Position */ 196 #define MXC_F_TPU_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_RDY_POS)) /**< CTRL_RDY Mask */ 197 198 #define MXC_F_TPU_CTRL_DONE_POS 31 /**< CTRL_DONE Position */ 199 #define MXC_F_TPU_CTRL_DONE ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_DONE_POS)) /**< CTRL_DONE Mask */ 200 201 /**@} end of group TPU_CTRL_Register */ 202 203 /** 204 * @ingroup tpu_registers 205 * @defgroup TPU_CIPHER_CTRL TPU_CIPHER_CTRL 206 * @brief Cipher Control Register. 207 * @{ 208 */ 209 #define MXC_F_TPU_CIPHER_CTRL_ENC_POS 0 /**< CIPHER_CTRL_ENC Position */ 210 #define MXC_F_TPU_CIPHER_CTRL_ENC ((uint32_t)(0x1UL << MXC_F_TPU_CIPHER_CTRL_ENC_POS)) /**< CIPHER_CTRL_ENC Mask */ 211 212 #define MXC_F_TPU_CIPHER_CTRL_KEY_POS 1 /**< CIPHER_CTRL_KEY Position */ 213 #define MXC_F_TPU_CIPHER_CTRL_KEY ((uint32_t)(0x1UL << MXC_F_TPU_CIPHER_CTRL_KEY_POS)) /**< CIPHER_CTRL_KEY Mask */ 214 215 #define MXC_F_TPU_CIPHER_CTRL_SRC_POS 2 /**< CIPHER_CTRL_SRC Position */ 216 #define MXC_F_TPU_CIPHER_CTRL_SRC ((uint32_t)(0x3UL << MXC_F_TPU_CIPHER_CTRL_SRC_POS)) /**< CIPHER_CTRL_SRC Mask */ 217 #define MXC_V_TPU_CIPHER_CTRL_SRC_CIPHERKEY ((uint32_t)0x0UL) /**< CIPHER_CTRL_SRC_CIPHERKEY Value */ 218 #define MXC_S_TPU_CIPHER_CTRL_SRC_CIPHERKEY (MXC_V_TPU_CIPHER_CTRL_SRC_CIPHERKEY << MXC_F_TPU_CIPHER_CTRL_SRC_POS) /**< CIPHER_CTRL_SRC_CIPHERKEY Setting */ 219 #define MXC_V_TPU_CIPHER_CTRL_SRC_REGFILE ((uint32_t)0x2UL) /**< CIPHER_CTRL_SRC_REGFILE Value */ 220 #define MXC_S_TPU_CIPHER_CTRL_SRC_REGFILE (MXC_V_TPU_CIPHER_CTRL_SRC_REGFILE << MXC_F_TPU_CIPHER_CTRL_SRC_POS) /**< CIPHER_CTRL_SRC_REGFILE Setting */ 221 #define MXC_V_TPU_CIPHER_CTRL_SRC_QSPIKEY_REGFILE ((uint32_t)0x3UL) /**< CIPHER_CTRL_SRC_QSPIKEY_REGFILE Value */ 222 #define MXC_S_TPU_CIPHER_CTRL_SRC_QSPIKEY_REGFILE (MXC_V_TPU_CIPHER_CTRL_SRC_QSPIKEY_REGFILE << MXC_F_TPU_CIPHER_CTRL_SRC_POS) /**< CIPHER_CTRL_SRC_QSPIKEY_REGFILE Setting */ 223 224 #define MXC_F_TPU_CIPHER_CTRL_CIPHER_POS 4 /**< CIPHER_CTRL_CIPHER Position */ 225 #define MXC_F_TPU_CIPHER_CTRL_CIPHER ((uint32_t)(0x7UL << MXC_F_TPU_CIPHER_CTRL_CIPHER_POS)) /**< CIPHER_CTRL_CIPHER Mask */ 226 #define MXC_V_TPU_CIPHER_CTRL_CIPHER_DIS ((uint32_t)0x0UL) /**< CIPHER_CTRL_CIPHER_DIS Value */ 227 #define MXC_S_TPU_CIPHER_CTRL_CIPHER_DIS (MXC_V_TPU_CIPHER_CTRL_CIPHER_DIS << MXC_F_TPU_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_DIS Setting */ 228 #define MXC_V_TPU_CIPHER_CTRL_CIPHER_AES128 ((uint32_t)0x1UL) /**< CIPHER_CTRL_CIPHER_AES128 Value */ 229 #define MXC_S_TPU_CIPHER_CTRL_CIPHER_AES128 (MXC_V_TPU_CIPHER_CTRL_CIPHER_AES128 << MXC_F_TPU_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_AES128 Setting */ 230 #define MXC_V_TPU_CIPHER_CTRL_CIPHER_AES192 ((uint32_t)0x2UL) /**< CIPHER_CTRL_CIPHER_AES192 Value */ 231 #define MXC_S_TPU_CIPHER_CTRL_CIPHER_AES192 (MXC_V_TPU_CIPHER_CTRL_CIPHER_AES192 << MXC_F_TPU_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_AES192 Setting */ 232 #define MXC_V_TPU_CIPHER_CTRL_CIPHER_AES256 ((uint32_t)0x3UL) /**< CIPHER_CTRL_CIPHER_AES256 Value */ 233 #define MXC_S_TPU_CIPHER_CTRL_CIPHER_AES256 (MXC_V_TPU_CIPHER_CTRL_CIPHER_AES256 << MXC_F_TPU_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_AES256 Setting */ 234 #define MXC_V_TPU_CIPHER_CTRL_CIPHER_DES ((uint32_t)0x4UL) /**< CIPHER_CTRL_CIPHER_DES Value */ 235 #define MXC_S_TPU_CIPHER_CTRL_CIPHER_DES (MXC_V_TPU_CIPHER_CTRL_CIPHER_DES << MXC_F_TPU_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_DES Setting */ 236 #define MXC_V_TPU_CIPHER_CTRL_CIPHER_TDES ((uint32_t)0x5UL) /**< CIPHER_CTRL_CIPHER_TDES Value */ 237 #define MXC_S_TPU_CIPHER_CTRL_CIPHER_TDES (MXC_V_TPU_CIPHER_CTRL_CIPHER_TDES << MXC_F_TPU_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_TDES Setting */ 238 239 #define MXC_F_TPU_CIPHER_CTRL_MODE_POS 8 /**< CIPHER_CTRL_MODE Position */ 240 #define MXC_F_TPU_CIPHER_CTRL_MODE ((uint32_t)(0x7UL << MXC_F_TPU_CIPHER_CTRL_MODE_POS)) /**< CIPHER_CTRL_MODE Mask */ 241 #define MXC_V_TPU_CIPHER_CTRL_MODE_ECB ((uint32_t)0x0UL) /**< CIPHER_CTRL_MODE_ECB Value */ 242 #define MXC_S_TPU_CIPHER_CTRL_MODE_ECB (MXC_V_TPU_CIPHER_CTRL_MODE_ECB << MXC_F_TPU_CIPHER_CTRL_MODE_POS) /**< CIPHER_CTRL_MODE_ECB Setting */ 243 #define MXC_V_TPU_CIPHER_CTRL_MODE_CBC ((uint32_t)0x1UL) /**< CIPHER_CTRL_MODE_CBC Value */ 244 #define MXC_S_TPU_CIPHER_CTRL_MODE_CBC (MXC_V_TPU_CIPHER_CTRL_MODE_CBC << MXC_F_TPU_CIPHER_CTRL_MODE_POS) /**< CIPHER_CTRL_MODE_CBC Setting */ 245 #define MXC_V_TPU_CIPHER_CTRL_MODE_CFB ((uint32_t)0x2UL) /**< CIPHER_CTRL_MODE_CFB Value */ 246 #define MXC_S_TPU_CIPHER_CTRL_MODE_CFB (MXC_V_TPU_CIPHER_CTRL_MODE_CFB << MXC_F_TPU_CIPHER_CTRL_MODE_POS) /**< CIPHER_CTRL_MODE_CFB Setting */ 247 #define MXC_V_TPU_CIPHER_CTRL_MODE_OFB ((uint32_t)0x3UL) /**< CIPHER_CTRL_MODE_OFB Value */ 248 #define MXC_S_TPU_CIPHER_CTRL_MODE_OFB (MXC_V_TPU_CIPHER_CTRL_MODE_OFB << MXC_F_TPU_CIPHER_CTRL_MODE_POS) /**< CIPHER_CTRL_MODE_OFB Setting */ 249 #define MXC_V_TPU_CIPHER_CTRL_MODE_CTR ((uint32_t)0x4UL) /**< CIPHER_CTRL_MODE_CTR Value */ 250 #define MXC_S_TPU_CIPHER_CTRL_MODE_CTR (MXC_V_TPU_CIPHER_CTRL_MODE_CTR << MXC_F_TPU_CIPHER_CTRL_MODE_POS) /**< CIPHER_CTRL_MODE_CTR Setting */ 251 252 /**@} end of group TPU_CIPHER_CTRL_Register */ 253 254 /** 255 * @ingroup tpu_registers 256 * @defgroup TPU_HASH_CTRL TPU_HASH_CTRL 257 * @brief HASH Control Register. 258 * @{ 259 */ 260 #define MXC_F_TPU_HASH_CTRL_INIT_POS 0 /**< HASH_CTRL_INIT Position */ 261 #define MXC_F_TPU_HASH_CTRL_INIT ((uint32_t)(0x1UL << MXC_F_TPU_HASH_CTRL_INIT_POS)) /**< HASH_CTRL_INIT Mask */ 262 263 #define MXC_F_TPU_HASH_CTRL_XOR_POS 1 /**< HASH_CTRL_XOR Position */ 264 #define MXC_F_TPU_HASH_CTRL_XOR ((uint32_t)(0x1UL << MXC_F_TPU_HASH_CTRL_XOR_POS)) /**< HASH_CTRL_XOR Mask */ 265 266 #define MXC_F_TPU_HASH_CTRL_HASH_POS 2 /**< HASH_CTRL_HASH Position */ 267 #define MXC_F_TPU_HASH_CTRL_HASH ((uint32_t)(0x7UL << MXC_F_TPU_HASH_CTRL_HASH_POS)) /**< HASH_CTRL_HASH Mask */ 268 #define MXC_V_TPU_HASH_CTRL_HASH_DIS ((uint32_t)0x0UL) /**< HASH_CTRL_HASH_DIS Value */ 269 #define MXC_S_TPU_HASH_CTRL_HASH_DIS (MXC_V_TPU_HASH_CTRL_HASH_DIS << MXC_F_TPU_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_DIS Setting */ 270 #define MXC_V_TPU_HASH_CTRL_HASH_SHA1 ((uint32_t)0x1UL) /**< HASH_CTRL_HASH_SHA1 Value */ 271 #define MXC_S_TPU_HASH_CTRL_HASH_SHA1 (MXC_V_TPU_HASH_CTRL_HASH_SHA1 << MXC_F_TPU_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_SHA1 Setting */ 272 #define MXC_V_TPU_HASH_CTRL_HASH_SHA224 ((uint32_t)0x2UL) /**< HASH_CTRL_HASH_SHA224 Value */ 273 #define MXC_S_TPU_HASH_CTRL_HASH_SHA224 (MXC_V_TPU_HASH_CTRL_HASH_SHA224 << MXC_F_TPU_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_SHA224 Setting */ 274 #define MXC_V_TPU_HASH_CTRL_HASH_SHA256 ((uint32_t)0x3UL) /**< HASH_CTRL_HASH_SHA256 Value */ 275 #define MXC_S_TPU_HASH_CTRL_HASH_SHA256 (MXC_V_TPU_HASH_CTRL_HASH_SHA256 << MXC_F_TPU_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_SHA256 Setting */ 276 #define MXC_V_TPU_HASH_CTRL_HASH_SHA384 ((uint32_t)0x4UL) /**< HASH_CTRL_HASH_SHA384 Value */ 277 #define MXC_S_TPU_HASH_CTRL_HASH_SHA384 (MXC_V_TPU_HASH_CTRL_HASH_SHA384 << MXC_F_TPU_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_SHA384 Setting */ 278 #define MXC_V_TPU_HASH_CTRL_HASH_SHA512 ((uint32_t)0x5UL) /**< HASH_CTRL_HASH_SHA512 Value */ 279 #define MXC_S_TPU_HASH_CTRL_HASH_SHA512 (MXC_V_TPU_HASH_CTRL_HASH_SHA512 << MXC_F_TPU_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_SHA512 Setting */ 280 281 #define MXC_F_TPU_HASH_CTRL_LAST_POS 5 /**< HASH_CTRL_LAST Position */ 282 #define MXC_F_TPU_HASH_CTRL_LAST ((uint32_t)(0x1UL << MXC_F_TPU_HASH_CTRL_LAST_POS)) /**< HASH_CTRL_LAST Mask */ 283 284 /**@} end of group TPU_HASH_CTRL_Register */ 285 286 /** 287 * @ingroup tpu_registers 288 * @defgroup TPU_CRC_CTRL TPU_CRC_CTRL 289 * @brief CRC Control Register. 290 * @{ 291 */ 292 #define MXC_F_TPU_CRC_CTRL_CRC_EN_POS 0 /**< CRC_CTRL_CRC_EN Position */ 293 #define MXC_F_TPU_CRC_CTRL_CRC_EN ((uint32_t)(0x1UL << MXC_F_TPU_CRC_CTRL_CRC_EN_POS)) /**< CRC_CTRL_CRC_EN Mask */ 294 295 #define MXC_F_TPU_CRC_CTRL_MSB_POS 1 /**< CRC_CTRL_MSB Position */ 296 #define MXC_F_TPU_CRC_CTRL_MSB ((uint32_t)(0x1UL << MXC_F_TPU_CRC_CTRL_MSB_POS)) /**< CRC_CTRL_MSB Mask */ 297 298 #define MXC_F_TPU_CRC_CTRL_PRNG_POS 2 /**< CRC_CTRL_PRNG Position */ 299 #define MXC_F_TPU_CRC_CTRL_PRNG ((uint32_t)(0x1UL << MXC_F_TPU_CRC_CTRL_PRNG_POS)) /**< CRC_CTRL_PRNG Mask */ 300 301 #define MXC_F_TPU_CRC_CTRL_ENT_POS 3 /**< CRC_CTRL_ENT Position */ 302 #define MXC_F_TPU_CRC_CTRL_ENT ((uint32_t)(0x1UL << MXC_F_TPU_CRC_CTRL_ENT_POS)) /**< CRC_CTRL_ENT Mask */ 303 304 #define MXC_F_TPU_CRC_CTRL_HAM_POS 4 /**< CRC_CTRL_HAM Position */ 305 #define MXC_F_TPU_CRC_CTRL_HAM ((uint32_t)(0x1UL << MXC_F_TPU_CRC_CTRL_HAM_POS)) /**< CRC_CTRL_HAM Mask */ 306 307 #define MXC_F_TPU_CRC_CTRL_HRST_POS 5 /**< CRC_CTRL_HRST Position */ 308 #define MXC_F_TPU_CRC_CTRL_HRST ((uint32_t)(0x1UL << MXC_F_TPU_CRC_CTRL_HRST_POS)) /**< CRC_CTRL_HRST Mask */ 309 310 /**@} end of group TPU_CRC_CTRL_Register */ 311 312 /** 313 * @ingroup tpu_registers 314 * @defgroup TPU_DMA_SRC TPU_DMA_SRC 315 * @brief Crypto DMA Source Address. 316 * @{ 317 */ 318 #define MXC_F_TPU_DMA_SRC_SRC_ADDR_POS 0 /**< DMA_SRC_SRC_ADDR Position */ 319 #define MXC_F_TPU_DMA_SRC_SRC_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_DMA_SRC_SRC_ADDR_POS)) /**< DMA_SRC_SRC_ADDR Mask */ 320 321 /**@} end of group TPU_DMA_SRC_Register */ 322 323 /** 324 * @ingroup tpu_registers 325 * @defgroup TPU_DMA_DST TPU_DMA_DST 326 * @brief Crypto DMA Destination Address. 327 * @{ 328 */ 329 #define MXC_F_TPU_DMA_DST_DST_ADDR_POS 0 /**< DMA_DST_DST_ADDR Position */ 330 #define MXC_F_TPU_DMA_DST_DST_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_DMA_DST_DST_ADDR_POS)) /**< DMA_DST_DST_ADDR Mask */ 331 332 /**@} end of group TPU_DMA_DST_Register */ 333 334 /** 335 * @ingroup tpu_registers 336 * @defgroup TPU_DMA_CNT TPU_DMA_CNT 337 * @brief Crypto DMA Byte Count. 338 * @{ 339 */ 340 #define MXC_F_TPU_DMA_CNT_COUNT_POS 0 /**< DMA_CNT_COUNT Position */ 341 #define MXC_F_TPU_DMA_CNT_COUNT ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_DMA_CNT_COUNT_POS)) /**< DMA_CNT_COUNT Mask */ 342 343 /**@} end of group TPU_DMA_CNT_Register */ 344 345 /** 346 * @ingroup tpu_registers 347 * @defgroup TPU_MAA_CTRL TPU_MAA_CTRL 348 * @brief MAA Control Register. 349 * @{ 350 */ 351 #define MXC_F_TPU_MAA_CTRL_STC_POS 0 /**< MAA_CTRL_STC Position */ 352 #define MXC_F_TPU_MAA_CTRL_STC ((uint32_t)(0x1UL << MXC_F_TPU_MAA_CTRL_STC_POS)) /**< MAA_CTRL_STC Mask */ 353 354 #define MXC_F_TPU_MAA_CTRL_CLC_POS 1 /**< MAA_CTRL_CLC Position */ 355 #define MXC_F_TPU_MAA_CTRL_CLC ((uint32_t)(0x7UL << MXC_F_TPU_MAA_CTRL_CLC_POS)) /**< MAA_CTRL_CLC Mask */ 356 #define MXC_V_TPU_MAA_CTRL_CLC_EXP ((uint32_t)0x0UL) /**< MAA_CTRL_CLC_EXP Value */ 357 #define MXC_S_TPU_MAA_CTRL_CLC_EXP (MXC_V_TPU_MAA_CTRL_CLC_EXP << MXC_F_TPU_MAA_CTRL_CLC_POS) /**< MAA_CTRL_CLC_EXP Setting */ 358 #define MXC_V_TPU_MAA_CTRL_CLC_SQ ((uint32_t)0x1UL) /**< MAA_CTRL_CLC_SQ Value */ 359 #define MXC_S_TPU_MAA_CTRL_CLC_SQ (MXC_V_TPU_MAA_CTRL_CLC_SQ << MXC_F_TPU_MAA_CTRL_CLC_POS) /**< MAA_CTRL_CLC_SQ Setting */ 360 #define MXC_V_TPU_MAA_CTRL_CLC_MUL ((uint32_t)0x2UL) /**< MAA_CTRL_CLC_MUL Value */ 361 #define MXC_S_TPU_MAA_CTRL_CLC_MUL (MXC_V_TPU_MAA_CTRL_CLC_MUL << MXC_F_TPU_MAA_CTRL_CLC_POS) /**< MAA_CTRL_CLC_MUL Setting */ 362 #define MXC_V_TPU_MAA_CTRL_CLC_SQMUL ((uint32_t)0x3UL) /**< MAA_CTRL_CLC_SQMUL Value */ 363 #define MXC_S_TPU_MAA_CTRL_CLC_SQMUL (MXC_V_TPU_MAA_CTRL_CLC_SQMUL << MXC_F_TPU_MAA_CTRL_CLC_POS) /**< MAA_CTRL_CLC_SQMUL Setting */ 364 #define MXC_V_TPU_MAA_CTRL_CLC_ADD ((uint32_t)0x4UL) /**< MAA_CTRL_CLC_ADD Value */ 365 #define MXC_S_TPU_MAA_CTRL_CLC_ADD (MXC_V_TPU_MAA_CTRL_CLC_ADD << MXC_F_TPU_MAA_CTRL_CLC_POS) /**< MAA_CTRL_CLC_ADD Setting */ 366 #define MXC_V_TPU_MAA_CTRL_CLC_SUB ((uint32_t)0x5UL) /**< MAA_CTRL_CLC_SUB Value */ 367 #define MXC_S_TPU_MAA_CTRL_CLC_SUB (MXC_V_TPU_MAA_CTRL_CLC_SUB << MXC_F_TPU_MAA_CTRL_CLC_POS) /**< MAA_CTRL_CLC_SUB Setting */ 368 369 #define MXC_F_TPU_MAA_CTRL_OCALC_POS 4 /**< MAA_CTRL_OCALC Position */ 370 #define MXC_F_TPU_MAA_CTRL_OCALC ((uint32_t)(0x1UL << MXC_F_TPU_MAA_CTRL_OCALC_POS)) /**< MAA_CTRL_OCALC Mask */ 371 372 #define MXC_F_TPU_MAA_CTRL_MAAER_POS 7 /**< MAA_CTRL_MAAER Position */ 373 #define MXC_F_TPU_MAA_CTRL_MAAER ((uint32_t)(0x1UL << MXC_F_TPU_MAA_CTRL_MAAER_POS)) /**< MAA_CTRL_MAAER Mask */ 374 375 #define MXC_F_TPU_MAA_CTRL_AMS_POS 8 /**< MAA_CTRL_AMS Position */ 376 #define MXC_F_TPU_MAA_CTRL_AMS ((uint32_t)(0x3UL << MXC_F_TPU_MAA_CTRL_AMS_POS)) /**< MAA_CTRL_AMS Mask */ 377 378 #define MXC_F_TPU_MAA_CTRL_BMS_POS 10 /**< MAA_CTRL_BMS Position */ 379 #define MXC_F_TPU_MAA_CTRL_BMS ((uint32_t)(0x3UL << MXC_F_TPU_MAA_CTRL_BMS_POS)) /**< MAA_CTRL_BMS Mask */ 380 381 #define MXC_F_TPU_MAA_CTRL_EMS_POS 12 /**< MAA_CTRL_EMS Position */ 382 #define MXC_F_TPU_MAA_CTRL_EMS ((uint32_t)(0x3UL << MXC_F_TPU_MAA_CTRL_EMS_POS)) /**< MAA_CTRL_EMS Mask */ 383 384 #define MXC_F_TPU_MAA_CTRL_MMS_POS 14 /**< MAA_CTRL_MMS Position */ 385 #define MXC_F_TPU_MAA_CTRL_MMS ((uint32_t)(0x3UL << MXC_F_TPU_MAA_CTRL_MMS_POS)) /**< MAA_CTRL_MMS Mask */ 386 387 #define MXC_F_TPU_MAA_CTRL_AMA_POS 16 /**< MAA_CTRL_AMA Position */ 388 #define MXC_F_TPU_MAA_CTRL_AMA ((uint32_t)(0xFUL << MXC_F_TPU_MAA_CTRL_AMA_POS)) /**< MAA_CTRL_AMA Mask */ 389 390 #define MXC_F_TPU_MAA_CTRL_BMA_POS 20 /**< MAA_CTRL_BMA Position */ 391 #define MXC_F_TPU_MAA_CTRL_BMA ((uint32_t)(0xFUL << MXC_F_TPU_MAA_CTRL_BMA_POS)) /**< MAA_CTRL_BMA Mask */ 392 393 #define MXC_F_TPU_MAA_CTRL_RMA_POS 24 /**< MAA_CTRL_RMA Position */ 394 #define MXC_F_TPU_MAA_CTRL_RMA ((uint32_t)(0xFUL << MXC_F_TPU_MAA_CTRL_RMA_POS)) /**< MAA_CTRL_RMA Mask */ 395 396 #define MXC_F_TPU_MAA_CTRL_TMA_POS 28 /**< MAA_CTRL_TMA Position */ 397 #define MXC_F_TPU_MAA_CTRL_TMA ((uint32_t)(0xFUL << MXC_F_TPU_MAA_CTRL_TMA_POS)) /**< MAA_CTRL_TMA Mask */ 398 399 /**@} end of group TPU_MAA_CTRL_Register */ 400 401 /** 402 * @ingroup tpu_registers 403 * @defgroup TPU_DATA_IN TPU_DATA_IN 404 * @brief Crypto Data Input. Data input can be written to this register instead of using 405 * the DMA. This register writes to the FIFO. This register occupies four 406 * successive words to allow the use of multi-store instructions. Words can be 407 * written to any location, they will be placed in the FIFO in the order they are 408 * written. The endian swap input control bit affects this register. 409 * @{ 410 */ 411 #define MXC_F_TPU_DATA_IN_DATA_POS 0 /**< DATA_IN_DATA Position */ 412 #define MXC_F_TPU_DATA_IN_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_DATA_IN_DATA_POS)) /**< DATA_IN_DATA Mask */ 413 414 /**@} end of group TPU_DATA_IN_Register */ 415 416 /** 417 * @ingroup tpu_registers 418 * @defgroup TPU_DATA_OUT TPU_DATA_OUT 419 * @brief Crypto Data Output. Resulting data from cipher calculation. Data is placed in 420 * the lower words of these four registers depending on the algorithm. For block 421 * cipher modes, this register holds the result of most recent encryption or 422 * decryption operation. These registers are affected by the endian swap bits. 423 * @{ 424 */ 425 #define MXC_F_TPU_DATA_OUT_DATA_POS 0 /**< DATA_OUT_DATA Position */ 426 #define MXC_F_TPU_DATA_OUT_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_DATA_OUT_DATA_POS)) /**< DATA_OUT_DATA Mask */ 427 428 /**@} end of group TPU_DATA_OUT_Register */ 429 430 /** 431 * @ingroup tpu_registers 432 * @defgroup TPU_CRC_POLY TPU_CRC_POLY 433 * @brief CRC Polynomial. The polynomial to be used for Galois Field calculations (CRC or 434 * LFSR) should be written to this register. This register is affected by the MSB 435 * control bit. 436 * @{ 437 */ 438 #define MXC_F_TPU_CRC_POLY_SRC_ADDR_POS 0 /**< CRC_POLY_SRC_ADDR Position */ 439 #define MXC_F_TPU_CRC_POLY_SRC_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_CRC_POLY_SRC_ADDR_POS)) /**< CRC_POLY_SRC_ADDR Mask */ 440 441 /**@} end of group TPU_CRC_POLY_Register */ 442 443 /** 444 * @ingroup tpu_registers 445 * @defgroup TPU_CRC_VAL TPU_CRC_VAL 446 * @brief CRC Value. This is the state for the Galois Field. This register holds the 447 * result of a CRC calculation or the current state of the LFSR. This register is 448 * affected by the MSB control bit. 449 * @{ 450 */ 451 #define MXC_F_TPU_CRC_VAL_VAL_POS 0 /**< CRC_VAL_VAL Position */ 452 #define MXC_F_TPU_CRC_VAL_VAL ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_CRC_VAL_VAL_POS)) /**< CRC_VAL_VAL Mask */ 453 454 /**@} end of group TPU_CRC_VAL_Register */ 455 456 /** 457 * @ingroup tpu_registers 458 * @defgroup TPU_CRC_PRNG TPU_CRC_PRNG 459 * @brief Pseudo Random Value. Output of the Galois Field shift register. This holds the 460 * resulting pseudo-random number if entropy is disabled or true random number if 461 * entropy is enabled. 462 * @{ 463 */ 464 #define MXC_F_TPU_CRC_PRNG_PRNG_POS 0 /**< CRC_PRNG_PRNG Position */ 465 #define MXC_F_TPU_CRC_PRNG_PRNG ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_CRC_PRNG_PRNG_POS)) /**< CRC_PRNG_PRNG Mask */ 466 467 /**@} end of group TPU_CRC_PRNG_Register */ 468 469 /** 470 * @ingroup tpu_registers 471 * @defgroup TPU_HAM_ECC TPU_HAM_ECC 472 * @brief Hamming ECC Register. 473 * @{ 474 */ 475 #define MXC_F_TPU_HAM_ECC_ECC_POS 0 /**< HAM_ECC_ECC Position */ 476 #define MXC_F_TPU_HAM_ECC_ECC ((uint32_t)(0xFFFFUL << MXC_F_TPU_HAM_ECC_ECC_POS)) /**< HAM_ECC_ECC Mask */ 477 478 #define MXC_F_TPU_HAM_ECC_PAR_POS 16 /**< HAM_ECC_PAR Position */ 479 #define MXC_F_TPU_HAM_ECC_PAR ((uint32_t)(0x1UL << MXC_F_TPU_HAM_ECC_PAR_POS)) /**< HAM_ECC_PAR Mask */ 480 481 /**@} end of group TPU_HAM_ECC_Register */ 482 483 /** 484 * @ingroup tpu_registers 485 * @defgroup TPU_CIPHER_INIT TPU_CIPHER_INIT 486 * @brief Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR 487 * modes, this register holds the initial value. This register is updated with each 488 * encryption or decryption operation. This register is affected by the endian swap 489 * bits. 490 * @{ 491 */ 492 #define MXC_F_TPU_CIPHER_INIT_IVEC_POS 0 /**< CIPHER_INIT_IVEC Position */ 493 #define MXC_F_TPU_CIPHER_INIT_IVEC ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_CIPHER_INIT_IVEC_POS)) /**< CIPHER_INIT_IVEC Mask */ 494 495 /**@} end of group TPU_CIPHER_INIT_Register */ 496 497 /** 498 * @ingroup tpu_registers 499 * @defgroup TPU_CIPHER_KEY TPU_CIPHER_KEY 500 * @brief Cipher Key. This register holds the key used for block cipher operations. The 501 * lower words are used for block ciphers that use shorter key lengths. This 502 * register is affected by the endian swap input control bits. 503 * @{ 504 */ 505 #define MXC_F_TPU_CIPHER_KEY_KEY_POS 0 /**< CIPHER_KEY_KEY Position */ 506 #define MXC_F_TPU_CIPHER_KEY_KEY ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_CIPHER_KEY_KEY_POS)) /**< CIPHER_KEY_KEY Mask */ 507 508 /**@} end of group TPU_CIPHER_KEY_Register */ 509 510 /** 511 * @ingroup tpu_registers 512 * @defgroup TPU_HASH_DIGEST TPU_HASH_DIGEST 513 * @brief This register holds the calculated hash value. This register is affected by the 514 * endian swap bits. 515 * @{ 516 */ 517 #define MXC_F_TPU_HASH_DIGEST_HASH_POS 0 /**< HASH_DIGEST_HASH Position */ 518 #define MXC_F_TPU_HASH_DIGEST_HASH ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_HASH_DIGEST_HASH_POS)) /**< HASH_DIGEST_HASH Mask */ 519 520 /**@} end of group TPU_HASH_DIGEST_Register */ 521 522 /** 523 * @ingroup tpu_registers 524 * @defgroup TPU_HASH_MSG_SZ TPU_HASH_MSG_SZ 525 * @brief Message Size. This register holds the lowest 32-bit of message size in bytes. 526 * @{ 527 */ 528 #define MXC_F_TPU_HASH_MSG_SZ_MSGSZ_POS 0 /**< HASH_MSG_SZ_MSGSZ Position */ 529 #define MXC_F_TPU_HASH_MSG_SZ_MSGSZ ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_HASH_MSG_SZ_MSGSZ_POS)) /**< HASH_MSG_SZ_MSGSZ Mask */ 530 531 /**@} end of group TPU_HASH_MSG_SZ_Register */ 532 533 /** 534 * @ingroup tpu_registers 535 * @defgroup TPU_MAA_MAWS TPU_MAA_MAWS 536 * @brief MAA Word Size. This register defines the number of bits for a modular operation. 537 * This register must be set to a valid value prior to the MAA operation start. 538 * Valid values are from 1 to 2048. Invalid values are ignored and will not 539 * initiate a MAA operation. 540 * @{ 541 */ 542 #define MXC_F_TPU_MAA_MAWS_MSGSZ_POS 0 /**< MAA_MAWS_MSGSZ Position */ 543 #define MXC_F_TPU_MAA_MAWS_MSGSZ ((uint32_t)(0xFFFUL << MXC_F_TPU_MAA_MAWS_MSGSZ_POS)) /**< MAA_MAWS_MSGSZ Mask */ 544 545 /**@} end of group TPU_MAA_MAWS_Register */ 546 547 #ifdef __cplusplus 548 } 549 #endif 550 551 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_TPU_REGS_H_ 552
