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Searched refs:RTC_CORE_INTR_SOURCE (Results 1 – 10 of 10) sorted by relevance

/Zephyr-latest/include/zephyr/dt-bindings/interrupt-controller/
Desp-esp32c2-intmux.h31 #define RTC_CORE_INTR_SOURCE 21 macro
Desp-esp32c3-intmux.h37 #define RTC_CORE_INTR_SOURCE 27 macro
Desp-xtensa-intmux.h57 #define RTC_CORE_INTR_SOURCE 46 /* rtc core, level, include rtc watchdog */ macro
Desp32s2-xtensa-intmux.h59 #define RTC_CORE_INTR_SOURCE 49 /* rtc core, level, include rtc watchdog */ macro
Desp32s3-xtensa-intmux.h46 #define RTC_CORE_INTR_SOURCE 39 /* interrupt of rtc core and watchdog, level*/ macro
/Zephyr-latest/dts/xtensa/espressif/esp32s2/
Desp32s2_common.dtsi139 interrupts = <RTC_CORE_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
148 interrupts = <RTC_CORE_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
233 interrupts = <RTC_CORE_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
352 interrupts = <RTC_CORE_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
/Zephyr-latest/dts/xtensa/espressif/esp32/
Desp32_common.dtsi196 interrupts = <RTC_CORE_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
335 interrupts = <RTC_CORE_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
464 interrupts = <RTC_CORE_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
/Zephyr-latest/dts/riscv/espressif/esp32c3/
Desp32c3_common.dtsi125 interrupts = <RTC_CORE_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
134 interrupts = <RTC_CORE_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
/Zephyr-latest/dts/xtensa/espressif/esp32s3/
Desp32s3_common.dtsi181 interrupts = <RTC_CORE_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
190 interrupts = <RTC_CORE_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
278 interrupts = <RTC_CORE_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
/Zephyr-latest/dts/riscv/espressif/esp32c2/
Desp32c2_common.dtsi101 interrupts = <RTC_CORE_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;