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Searched refs:GD32_RESET_GPIOC (Results 1 – 16 of 16) sorted by relevance

/Zephyr-latest/include/zephyr/dt-bindings/reset/
Dgd32f3x0.h55 #define GD32_RESET_GPIOC GD32_RESET_CONFIG(AHBRST, 19U) macro
Dgd32l23x.h32 #define GD32_RESET_GPIOC GD32_RESET_CONFIG(AHB1RST, 19U) macro
Dgd32vf103.h32 #define GD32_RESET_GPIOC GD32_RESET_CONFIG(APB2RST, 4U) macro
Dgd32a50x.h39 #define GD32_RESET_GPIOC GD32_RESET_CONFIG(AHBRST, 19U) macro
Dgd32e10x.h33 #define GD32_RESET_GPIOC GD32_RESET_CONFIG(APB2RST, 4U) macro
Dgd32f403.h33 #define GD32_RESET_GPIOC GD32_RESET_CONFIG(APB2RST, 4U) macro
Dgd32e50x.h33 #define GD32_RESET_GPIOC GD32_RESET_CONFIG(APB2RST, 4U) macro
Dgd32f4xx.h34 #define GD32_RESET_GPIOC GD32_RESET_CONFIG(AHB1RST, 2U) macro
/Zephyr-latest/dts/arm/gd/gd32f3x0/
Dgd32f3x0.dtsi153 resets = <&rctl GD32_RESET_GPIOC>;
/Zephyr-latest/dts/arm/gd/gd32l23x/
Dgd32l23x.dtsi153 resets = <&rctl GD32_RESET_GPIOC>;
/Zephyr-latest/dts/arm/gd/gd32a50x/
Dgd32a50x.dtsi248 resets = <&rctl GD32_RESET_GPIOC>;
/Zephyr-latest/dts/riscv/gd/
Dgd32vf103.dtsi274 resets = <&rctl GD32_RESET_GPIOC>;
/Zephyr-latest/dts/arm/gd/gd32e50x/
Dgd32e50x.dtsi251 resets = <&rctl GD32_RESET_GPIOC>;
/Zephyr-latest/dts/arm/gd/gd32e10x/
Dgd32e10x.dtsi215 resets = <&rctl GD32_RESET_GPIOC>;
/Zephyr-latest/dts/arm/gd/gd32f403/
Dgd32f403.dtsi253 resets = <&rctl GD32_RESET_GPIOC>;
/Zephyr-latest/dts/arm/gd/gd32f4xx/
Dgd32f4xx.dtsi325 resets = <&rctl GD32_RESET_GPIOC>;