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/Zephyr-Core-3.5.0/tests/drivers/clock_control/adsp_clock/src/
Dmain.c10 static void check_clocks(struct adsp_cpu_clock_info *clocks, uint32_t freq_idx) in check_clocks() argument
16 zassert_equal(clocks[i].current_freq, freq_idx, ""); in check_clocks()
22 struct adsp_cpu_clock_info *clocks = adsp_cpu_clocks_get(); in ZTEST() local
24 zassert_not_null(clocks, ""); in ZTEST()
27 check_clocks(clocks, ADSP_CPU_CLOCK_FREQ_LPRO); in ZTEST()
30 check_clocks(clocks, ADSP_CPU_CLOCK_FREQ_HPRO); in ZTEST()
34 check_clocks(clocks, ADSP_CPU_CLOCK_FREQ_WOVCRO); in ZTEST()
40 struct adsp_cpu_clock_info *clocks = adsp_cpu_clocks_get(); in ZTEST() local
43 zassert_not_null(clocks, ""); in ZTEST()
47 check_clocks(clocks, ADSP_CPU_CLOCK_FREQ_LPRO); in ZTEST()
[all …]
/Zephyr-Core-3.5.0/dts/arm/atmel/
Dsamd20.dtsi21 clocks = <&gclk 0x13>, <&pm 0x20 8>;
29 clocks = <&gclk 0x14>, <&pm 0x20 10>;
37 clocks = <&gclk 0x16>, <&pm 0x20 14>;
45 clocks = <&gclk 26>, <&pm 0x20 18>;
51 clocks = <&gclk 0xd>, <&pm 0x20 2>;
57 clocks = <&gclk 0xe>, <&pm 0x20 3>;
63 clocks = <&gclk 0xf>, <&pm 0x20 4>;
69 clocks = <&gclk 0x10>, <&pm 0x20 5>;
75 clocks = <&gclk 0x11>, <&pm 0x20 6>;
81 clocks = <&gclk 0x12>, <&pm 0x20 7>;
[all …]
Dsaml21.dtsi30 clocks = <&gclk 25>, <&mclk 0x1c 5>;
41 clocks = <&gclk 25>, <&mclk 0x1c 6>;
52 clocks = <&gclk 26>, <&mclk 0x1c 7>;
63 clocks = <&gclk 32>, <&mclk 0x1c 12>;
69 clocks = <&gclk 18>, <&mclk 0x1c 0>;
75 clocks = <&gclk 19>, <&mclk 0x1c 1>;
81 clocks = <&gclk 20>, <&mclk 0x1c 2>;
87 clocks = <&gclk 21>, <&mclk 0x1c 3>;
93 clocks = <&gclk 22>, <&mclk 0x1c 4>;
99 clocks = <&gclk 24>, <&mclk 0x20 1>;
[all …]
Dsamd21.dtsi34 clocks = <&gclk 0x1d>, <&pm 0x20 14>;
42 clocks = <&gclk 26>, <&pm 0x20 8>;
53 clocks = <&gclk 26>, <&pm 0x20 9>;
64 clocks = <&gclk 27>, <&pm 0x20 10>;
75 clocks = <&gclk 33>, <&pm 0x20 18>;
81 clocks = <&gclk 0x14>, <&pm 0x20 2>;
87 clocks = <&gclk 0x15>, <&pm 0x20 3>;
93 clocks = <&gclk 0x16>, <&pm 0x20 4>;
99 clocks = <&gclk 0x17>, <&pm 0x20 5>;
105 clocks = <&gclk 0x18>, <&pm 0x20 6>;
[all …]
Dsame70.dtsi64 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
82 clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
93 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
104 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
115 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
125 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
135 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>;
143 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
151 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
159 clocks = <&pmc PMC_TYPE_PERIPHERAL 44>;
[all …]
Dsamr21.dtsi51 clocks = <&gclk 26>, <&pm 0x20 8>;
62 clocks = <&gclk 26>, <&pm 0x20 9>;
73 clocks = <&gclk 27>, <&pm 0x20 10>;
84 clocks = <&gclk 0x14>, <&pm 0x20 2>;
90 clocks = <&gclk 0x15>, <&pm 0x20 3>;
96 clocks = <&gclk 0x16>, <&pm 0x20 4>;
102 clocks = <&gclk 0x17>, <&pm 0x20 5>;
108 clocks = <&gclk 0x18>, <&pm 0x20 6>;
114 clocks = <&gclk 0x19>, <&pm 0x20 7>;
120 clocks = <&gclk 0x1c>, <&pm 0x20 12>;
[all …]
Dsam4e.dtsi58 clocks = <&pmc PMC_TYPE_PERIPHERAL 30>;
67 clocks = <&pmc PMC_TYPE_PERIPHERAL 31>;
75 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
92 clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
101 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>;
112 clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
124 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
132 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
140 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>;
148 clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
[all …]
Dsam3x.dtsi49 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
73 clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
82 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
93 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
103 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
111 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>;
119 clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
127 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
135 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
149 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
[all …]
Dsam4s.dtsi59 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
76 clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
85 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
96 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
108 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
116 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
124 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
132 clocks = <&pmc PMC_TYPE_PERIPHERAL 31>;
143 clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
151 clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
[all …]
/Zephyr-Core-3.5.0/dts/arm/nuvoton/
Dm46x.dtsi84 clocks = <&pcc NUMAKER_UART0_MODULE NUMAKER_CLK_CLKSEL1_UART0SEL_HIRC
94 clocks = <&pcc NUMAKER_UART1_MODULE NUMAKER_CLK_CLKSEL1_UART1SEL_HIRC
104 clocks = <&pcc NUMAKER_UART2_MODULE NUMAKER_CLK_CLKSEL3_UART2SEL_HIRC
114 clocks = <&pcc NUMAKER_UART3_MODULE NUMAKER_CLK_CLKSEL3_UART3SEL_HIRC
124 clocks = <&pcc NUMAKER_UART4_MODULE NUMAKER_CLK_CLKSEL3_UART4SEL_HIRC
134 clocks = <&pcc NUMAKER_UART5_MODULE NUMAKER_CLK_CLKSEL3_UART5SEL_HIRC
144 clocks = <&pcc NUMAKER_UART6_MODULE NUMAKER_CLK_CLKSEL3_UART6SEL_HIRC
154 clocks = <&pcc NUMAKER_UART7_MODULE NUMAKER_CLK_CLKSEL3_UART7SEL_HIRC
164 clocks = <&pcc NUMAKER_UART8_MODULE NUMAKER_CLK_CLKSEL2_UART8SEL_HIRC
174 clocks = <&pcc NUMAKER_UART9_MODULE NUMAKER_CLK_CLKSEL2_UART9SEL_HIRC
[all …]
/Zephyr-Core-3.5.0/dts/arm/nxp/
Dnxp_s32z27x_rtu0_r52.dtsi23 clocks = <&clock NXP_S32_RTU0_REG_INTF_CLK>;
31 clocks = <&clock NXP_S32_RTU0_REG_INTF_CLK>;
39 clocks = <&clock NXP_S32_RTU0_REG_INTF_CLK>;
47 clocks = <&clock NXP_S32_RTU0_REG_INTF_CLK>;
55 clocks = <&clock NXP_S32_FIRC_CLK>;
63 clocks = <&clock NXP_S32_FIRC_CLK>;
71 clocks = <&clock NXP_S32_FIRC_CLK>;
79 clocks = <&clock NXP_S32_FIRC_CLK>;
87 clocks = <&clock NXP_S32_FIRC_CLK>;
95 clocks = <&clock NXP_S32_P0_REG_INTF_CLK>;
Dnxp_s32z27x_rtu1_r52.dtsi23 clocks = <&clock NXP_S32_RTU1_REG_INTF_CLK>;
31 clocks = <&clock NXP_S32_RTU1_REG_INTF_CLK>;
39 clocks = <&clock NXP_S32_RTU1_REG_INTF_CLK>;
47 clocks = <&clock NXP_S32_RTU1_REG_INTF_CLK>;
55 clocks = <&clock NXP_S32_FIRC_CLK>;
63 clocks = <&clock NXP_S32_FIRC_CLK>;
71 clocks = <&clock NXP_S32_FIRC_CLK>;
79 clocks = <&clock NXP_S32_FIRC_CLK>;
87 clocks = <&clock NXP_S32_FIRC_CLK>;
95 clocks = <&clock NXP_S32_P1_REG_INTF_CLK>;
Dnxp_ke1xf.dtsi151 clocks = <&sosc_clk>;
159 clocks = <&pll>;
166 clocks = <&firc_clk>;
173 clocks = <&core_clk>;
180 clocks = <&core_clk>;
188 clocks = <&firc_clk>;
194 clocks = <&spll_clk>;
201 clocks = <&spll_clk>;
208 clocks = <&sirc_clk>;
215 clocks = <&sirc_clk>;
[all …]
/Zephyr-Core-3.5.0/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/
Dg0_i2c1_hsi_lptim1_lse_adc1_pllp.overlay27 /delete-property/ clocks;
32 /delete-property/ clocks;
55 clocks = <&clk_hsi>;
60 clocks = <&pll>;
67 /delete-property/ clocks;
68 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>,
74 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>,
80 clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00100000>,
/Zephyr-Core-3.5.0/dts/arm/infineon/psoc6/
Dsystem_clocks.dtsi10 clocks {
24 clocks = <&clk_imo>;
32 clocks = <&clk_imo>;
40 clocks = <&clk_imo>;
48 clocks = <&clk_imo>;
56 clocks = <&clk_imo>;
81 clocks = <&fll0>;
90 clocks = <&path_mux1>;
99 clocks = <&path_mux2>;
108 clocks = <&path_mux3>;
[all …]
/Zephyr-Core-3.5.0/include/zephyr/devicetree/
Dclocks.h53 DT_PROP_HAS_IDX(node_id, clocks, idx)
84 DT_PROP_HAS_NAME(node_id, clocks, name)
108 DT_PROP_LEN(node_id, clocks)
137 DT_PHANDLE_BY_IDX(node_id, clocks, idx)
174 DT_PHANDLE_BY_NAME(node_id, clocks, name)
208 DT_PHA_BY_IDX(node_id, clocks, idx, cell)
244 DT_PHA_BY_NAME(node_id, clocks, name, cell)
/Zephyr-Core-3.5.0/dts/arm/st/l4/
Dstm32l496.dtsi13 clocks {
23 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00040000>,
33 clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000002>;
47 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000100>;
56 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x04000000>; //RCC_APB1ENR1_CAN2EN
64 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00010000>;
71 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00001000>,
76 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000400>,
Dstm32l4p5.dtsi21 clocks {
41 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00040000>,
53 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000008>;
61 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
69 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000020>;
77 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>;
85 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000100>;
92 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
101 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
110 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
[all …]
Dstm32l431.dtsi13 clocks {
27 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000008>;
35 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
43 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00040000>,
52 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
64 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
74 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
82 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
91 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
107 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
[all …]
Dstm32l451.dtsi13 clocks {
28 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000008>;
36 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
41 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00040000>,
51 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
63 clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000002>;
74 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
84 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
92 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
101 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
[all …]
Dstm32l471.dtsi20 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000008>;
28 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
36 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000020>;
44 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>;
51 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
60 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
69 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
81 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
92 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
102 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
[all …]
/Zephyr-Core-3.5.0/dts/arm/gigadevice/gd32f4xx/
Dgd32f4xx.dtsi12 #include <zephyr/dt-bindings/clock/gd32f4xx-clocks.h>
76 clocks = <&cctl GD32_CLOCK_USART0>;
85 clocks = <&cctl GD32_CLOCK_USART1>;
94 clocks = <&cctl GD32_CLOCK_USART2>;
103 clocks = <&cctl GD32_CLOCK_UART3>;
112 clocks = <&cctl GD32_CLOCK_UART4>;
121 clocks = <&cctl GD32_CLOCK_USART5>;
130 clocks = <&cctl GD32_CLOCK_UART6>;
139 clocks = <&cctl GD32_CLOCK_UART7>;
147 clocks = <&cctl GD32_CLOCK_DAC>;
[all …]
/Zephyr-Core-3.5.0/dts/arm/st/f1/
Dstm32f105.dtsi10 clocks {
22 clocks = <&clk_hse>;
41 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
52 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x06000000>;
60 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
68 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
77 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
88 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
98 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
106 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
[all …]
/Zephyr-Core-3.5.0/dts/arm/st/h5/
Dstm32h562.dtsi11 clocks {
29 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
37 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000020>;
45 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>;
53 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000100>;
60 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
69 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
78 clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000001>;
87 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x04000000>;
96 clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000002>;
[all …]
/Zephyr-Core-3.5.0/dts/arm/st/mp1/
Dstm32mp157.dtsi88 clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000001>;
96 clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000002>;
104 clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000004>;
112 clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000008>;
120 clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000010>;
128 clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000020>;
136 clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000040>;
144 clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000080>;
152 clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000100>;
160 clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000200>;
[all …]

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