1/*
2 * Copyright (c) 2018 Pushpal Sidhu
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <mem.h>
8#include <st/l4/stm32l4.dtsi>
9#include <zephyr/dt-bindings/flash_controller/ospi.h>
10
11/delete-node/ &quadspi;
12
13/ {
14	sram0: memory@20000000 {
15		reg = <0x20000000 DT_SIZE_K(320)>;
16	};
17
18	soc {
19		compatible = "st,stm32l4p5", "st,stm32l4", "simple-bus";
20
21		clocks {
22			clk_hsi48: clk-hsi48 {
23				#clock-cells = <0>;
24				compatible = "fixed-clock";
25				clock-frequency = <DT_FREQ_M(48)>;
26				status = "disabled";
27			};
28		};
29
30		flash-controller@40022000 {
31			flash0: flash@8000000 {
32				erase-block-size = <4096>;
33			};
34		};
35
36		rcc: rcc@40021000 {
37			undershoot-prevention;
38		};
39
40		rng: rng@50060800 {
41			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00040000>,
42				 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
43		};
44
45		pinctrl: pin-controller@48000000 {
46			reg = <0x48000000 0x2400>;
47
48			gpiod: gpio@48000c00 {
49				compatible = "st,stm32-gpio";
50				gpio-controller;
51				#gpio-cells = <2>;
52				reg = <0x48000c00 0x400>;
53				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000008>;
54			};
55
56			gpioe: gpio@48001000 {
57				compatible = "st,stm32-gpio";
58				gpio-controller;
59				#gpio-cells = <2>;
60				reg = <0x48001000 0x400>;
61				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
62			};
63
64			gpiof: gpio@48001400 {
65				compatible = "st,stm32-gpio";
66				gpio-controller;
67				#gpio-cells = <2>;
68				reg = <0x48001400 0x400>;
69				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000020>;
70			};
71
72			gpiog: gpio@48001800 {
73				compatible = "st,stm32-gpio";
74				gpio-controller;
75				#gpio-cells = <2>;
76				reg = <0x48001800 0x400>;
77				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>;
78			};
79
80			gpioi: gpio@48002000 {
81				compatible = "st,stm32-gpio";
82				gpio-controller;
83				#gpio-cells = <2>;
84				reg = <0x48002000 0x400>;
85				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000100>;
86			};
87		};
88
89		usart3: serial@40004800 {
90			compatible = "st,stm32-usart", "st,stm32-uart";
91			reg = <0x40004800 0x400>;
92			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
93			resets = <&rctl STM32_RESET(APB1L, 18U)>;
94			interrupts = <39 0>;
95			status = "disabled";
96		};
97
98		uart4: serial@40004c00 {
99			compatible = "st,stm32-uart";
100			reg = <0x40004c00 0x400>;
101			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
102			resets = <&rctl STM32_RESET(APB1L, 19U)>;
103			interrupts = <52 0>;
104			status = "disabled";
105		};
106
107		uart5: serial@40005000 {
108			compatible = "st,stm32-uart";
109			reg = <0x40005000 0x400>;
110			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
111			resets = <&rctl STM32_RESET(APB1L, 20U)>;
112			interrupts = <53 0>;
113			status = "disabled";
114		};
115
116		i2c2: i2c@40005800 {
117			compatible = "st,stm32-i2c-v2";
118			clock-frequency = <I2C_BITRATE_STANDARD>;
119			#address-cells = <1>;
120			#size-cells = <0>;
121			reg = <0x40005800 0x400>;
122			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
123			interrupts = <33 0>, <34 0>;
124			interrupt-names = "event", "error";
125			status = "disabled";
126		};
127
128		i2c4: i2c@40008400 {
129			compatible = "st,stm32-i2c-v2";
130			clock-frequency = <I2C_BITRATE_STANDARD>;
131			#address-cells = <1>;
132			#size-cells = <0>;
133			reg = <0x40008400 0x400>;
134			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000002>;
135			interrupts = <84 0>, <83 0>;
136			interrupt-names = "event", "error";
137			status = "disabled";
138		};
139
140		spi2: spi@40003800 {
141			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
142			#address-cells = <1>;
143			#size-cells = <0>;
144			reg = <0x40003800 0x400>;
145			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
146			interrupts = <36 5>;
147			status = "disabled";
148		};
149
150		spi3: spi@40003c00 {
151			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
152			#address-cells = <1>;
153			#size-cells = <0>;
154			reg = <0x40003c00 0x400>;
155			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
156			interrupts = <51 5>;
157			status = "disabled";
158		};
159
160		timers3: timers@40000400 {
161			compatible = "st,stm32-timers";
162			reg = <0x40000400 0x400>;
163			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
164			resets = <&rctl STM32_RESET(APB1L, 1U)>;
165			interrupts = <29 0>;
166			interrupt-names = "global";
167			st,prescaler = <0>;
168			status = "disabled";
169
170			pwm {
171				compatible = "st,stm32-pwm";
172				status = "disabled";
173				#pwm-cells = <3>;
174			};
175
176			counter {
177				compatible = "st,stm32-counter";
178				status = "disabled";
179			};
180		};
181
182		timers4: timers@40000800 {
183			compatible = "st,stm32-timers";
184			reg = <0x40000800 0x400>;
185			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
186			resets = <&rctl STM32_RESET(APB1L, 2U)>;
187			interrupts = <30 0>;
188			interrupt-names = "global";
189			st,prescaler = <0>;
190			status = "disabled";
191
192			pwm {
193				compatible = "st,stm32-pwm";
194				status = "disabled";
195				#pwm-cells = <3>;
196			};
197
198			counter {
199				compatible = "st,stm32-counter";
200				status = "disabled";
201			};
202		};
203
204		timers5: timers@40000c00 {
205			compatible = "st,stm32-timers";
206			reg = <0x40000c00 0x400>;
207			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
208			resets = <&rctl STM32_RESET(APB1L, 3U)>;
209			interrupts = <50 0>;
210			interrupt-names = "global";
211			st,prescaler = <0>;
212			status = "disabled";
213
214			pwm {
215				compatible = "st,stm32-pwm";
216				status = "disabled";
217				#pwm-cells = <3>;
218			};
219
220			counter {
221				compatible = "st,stm32-counter";
222				status = "disabled";
223			};
224		};
225
226		timers7: timers@40001400 {
227			compatible = "st,stm32-timers";
228			reg = <0x40001400 0x400>;
229			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
230			resets = <&rctl STM32_RESET(APB1L, 5U)>;
231			interrupts = <55 0>;
232			interrupt-names = "global";
233			st,prescaler = <0>;
234			status = "disabled";
235
236			pwm {
237				compatible = "st,stm32-pwm";
238				status = "disabled";
239				#pwm-cells = <3>;
240			};
241
242			counter {
243				compatible = "st,stm32-counter";
244				status = "disabled";
245			};
246		};
247
248		timers8: timers@40013400 {
249			compatible = "st,stm32-timers";
250			reg = <0x40013400 0x400>;
251			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
252			resets = <&rctl STM32_RESET(APB2, 13U)>;
253			interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
254			interrupt-names = "brk", "up", "trgcom", "cc";
255			st,prescaler = <0>;
256			status = "disabled";
257
258			pwm {
259				compatible = "st,stm32-pwm";
260				status = "disabled";
261				#pwm-cells = <3>;
262			};
263		};
264
265		timers17: timers@40014800 {
266			compatible = "st,stm32-timers";
267			reg = <0x40014800 0x400>;
268			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00040000>;
269			resets = <&rctl STM32_RESET(APB2, 18U)>;
270			interrupts = <26 0>;
271			interrupt-names = "global";
272			st,prescaler = <0>;
273			status = "disabled";
274
275			pwm {
276				compatible = "st,stm32-pwm";
277				status = "disabled";
278				#pwm-cells = <3>;
279			};
280
281			counter {
282				compatible = "st,stm32-counter";
283				status = "disabled";
284			};
285		};
286
287		can1: can@40006400 {
288			compatible = "st,stm32-bxcan";
289			reg = <0x40006400 0x400>;
290			interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
291			interrupt-names = "TX", "RX0", "RX1", "SCE";
292			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>; //RCC_APB1ENR1_CAN1EN
293			status = "disabled";
294			sample-point = <875>;
295		};
296
297		aes: aes@50060000 {
298			compatible = "st,stm32-aes";
299			reg = <0x50060000 0x400>;
300			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00010000>;
301			interrupts = <79 0>;
302			interrupt-names = "aes";
303			status = "disabled";
304		};
305
306		usbotg_fs: otgfs@50000000 {
307			compatible = "st,stm32-otgfs";
308			reg = <0x50000000 0x40000>;
309			interrupts = <67 0>;
310			interrupt-names = "otgfs";
311			num-bidir-endpoints = <6>;
312			ram-size = <1280>;
313			maximum-speed = "full-speed";
314			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00001000>,
315				 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
316			phys = <&otgfs_phy>;
317			status = "disabled";
318		};
319
320		dma1: dma@40020000 {
321			dma-offset = <0>;
322		};
323
324		dma2: dma@40020400 {
325			dma-offset = <7>;
326		};
327
328		dmamux1: dmamux@40020800 {
329			compatible = "st,stm32-dmamux";
330			#dma-cells = <3>;
331			reg = <0x40020800 0x400>;
332			interrupts = <94 0>;
333			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x4>;
334			dma-channels = <14>;
335			dma-generators = <4>;
336			dma-requests= <89>;
337			status = "disabled";
338		};
339
340		sdmmc1: sdmmc@50062400 {
341			compatible = "st,stm32-sdmmc";
342			reg = <0x50062400 0x400>;
343			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x400000>,
344				 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
345			resets = <&rctl STM32_RESET(AHB2, 22U)>;
346			interrupts = <49 0>;
347			status = "disabled";
348		};
349
350		sdmmc2: sdmmc@50062800 {
351			compatible = "st,stm32-sdmmc";
352			reg = <0x50062800 0x400>;
353			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x800000>,
354				 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
355			resets = <&rctl STM32_RESET(AHB2, 23U)>;
356			interrupts = <47 0>;
357			status = "disabled";
358		};
359
360		dac1: dac@40007400 {
361			compatible = "st,stm32-dac";
362			reg = <0x40007400 0x400>;
363			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
364			status = "disabled";
365			#io-channel-cells = <1>;
366		};
367
368		octospi1: octospi@a0001000 {
369			compatible = "st,stm32-ospi";
370			reg = <0xa0001000 0x400>;
371			interrupts = <71 0>;
372			clock-names = "ospix", "ospi-ker", "ospi-mgr";
373			clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00000100>,
374				<&rcc STM32_SRC_SYSCLK OSPI_SEL(0)>,
375				<&rcc STM32_CLOCK_BUS_AHB2 0x00100000>;
376
377			#address-cells = <1>;
378			#size-cells = <0>;
379			status = "disabled";
380		};
381
382		octospi2: octospi@a0001400 {
383			compatible = "st,stm32-ospi";
384			reg = <0xa0001400 0x400>;
385			interrupts = <76 0>;
386			clock-names = "ospix", "ospi-ker", "ospi-mgr";
387			clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00000200>,
388				<&rcc STM32_SRC_SYSCLK OSPI_SEL(0)>,
389				<&rcc STM32_CLOCK_BUS_AHB2 0x00100000>;
390
391			#address-cells = <1>;
392			#size-cells = <0>;
393			status = "disabled";
394		};
395	};
396
397	otgfs_phy: otgfs_phy {
398		compatible = "usb-nop-xceiv";
399		#phy-cells = <0>;
400	};
401};
402