1/* 2 * Copyright (c) 2017 Linaro Limited 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <st/l4/stm32l4.dtsi> 8 9/ { 10 soc { 11 compatible = "st,stm32l471", "st,stm32l4", "simple-bus"; 12 13 pinctrl: pin-controller@48000000 { 14 15 gpiod: gpio@48000c00 { 16 compatible = "st,stm32-gpio"; 17 gpio-controller; 18 #gpio-cells = <2>; 19 reg = <0x48000c00 0x400>; 20 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000008>; 21 }; 22 23 gpioe: gpio@48001000 { 24 compatible = "st,stm32-gpio"; 25 gpio-controller; 26 #gpio-cells = <2>; 27 reg = <0x48001000 0x400>; 28 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>; 29 }; 30 31 gpiof: gpio@48001400 { 32 compatible = "st,stm32-gpio"; 33 gpio-controller; 34 #gpio-cells = <2>; 35 reg = <0x48001400 0x400>; 36 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000020>; 37 }; 38 39 gpiog: gpio@48001800 { 40 compatible = "st,stm32-gpio"; 41 gpio-controller; 42 #gpio-cells = <2>; 43 reg = <0x48001800 0x400>; 44 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>; 45 }; 46 }; 47 48 usart3: serial@40004800 { 49 compatible = "st,stm32-usart", "st,stm32-uart"; 50 reg = <0x40004800 0x400>; 51 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>; 52 resets = <&rctl STM32_RESET(APB1L, 18U)>; 53 interrupts = <39 0>; 54 status = "disabled"; 55 }; 56 57 uart4: serial@40004c00 { 58 compatible = "st,stm32-uart"; 59 reg = <0x40004c00 0x400>; 60 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>; 61 resets = <&rctl STM32_RESET(APB1L, 19U)>; 62 interrupts = <52 0>; 63 status = "disabled"; 64 }; 65 66 uart5: serial@40005000 { 67 compatible = "st,stm32-uart"; 68 reg = <0x40005000 0x400>; 69 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>; 70 resets = <&rctl STM32_RESET(APB1L, 20U)>; 71 interrupts = <53 0>; 72 status = "disabled"; 73 }; 74 75 i2c2: i2c@40005800 { 76 compatible = "st,stm32-i2c-v2"; 77 clock-frequency = <I2C_BITRATE_STANDARD>; 78 #address-cells = <1>; 79 #size-cells = <0>; 80 reg = <0x40005800 0x400>; 81 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>; 82 interrupts = <33 0>, <34 0>; 83 interrupt-names = "event", "error"; 84 status = "disabled"; 85 }; 86 87 spi2: spi@40003800 { 88 compatible = "st,stm32-spi-fifo", "st,stm32-spi"; 89 #address-cells = <1>; 90 #size-cells = <0>; 91 reg = <0x40003800 0x400>; 92 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>; 93 interrupts = <36 5>; 94 status = "disabled"; 95 }; 96 97 spi3: spi@40003c00 { 98 compatible = "st,stm32-spi-fifo", "st,stm32-spi"; 99 #address-cells = <1>; 100 #size-cells = <0>; 101 reg = <0x40003c00 0x400>; 102 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>; 103 interrupts = <51 5>; 104 status = "disabled"; 105 }; 106 107 timers3: timers@40000400 { 108 compatible = "st,stm32-timers"; 109 reg = <0x40000400 0x400>; 110 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>; 111 resets = <&rctl STM32_RESET(APB1L, 1U)>; 112 interrupts = <29 0>; 113 interrupt-names = "global"; 114 st,prescaler = <0>; 115 status = "disabled"; 116 117 pwm { 118 compatible = "st,stm32-pwm"; 119 status = "disabled"; 120 #pwm-cells = <3>; 121 }; 122 123 counter { 124 compatible = "st,stm32-counter"; 125 status = "disabled"; 126 }; 127 }; 128 129 timers4: timers@40000800 { 130 compatible = "st,stm32-timers"; 131 reg = <0x40000800 0x400>; 132 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>; 133 resets = <&rctl STM32_RESET(APB1L, 2U)>; 134 interrupts = <30 0>; 135 interrupt-names = "global"; 136 st,prescaler = <0>; 137 status = "disabled"; 138 139 pwm { 140 compatible = "st,stm32-pwm"; 141 status = "disabled"; 142 #pwm-cells = <3>; 143 }; 144 145 counter { 146 compatible = "st,stm32-counter"; 147 status = "disabled"; 148 }; 149 }; 150 151 timers5: timers@40000c00 { 152 compatible = "st,stm32-timers"; 153 reg = <0x40000c00 0x400>; 154 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>; 155 resets = <&rctl STM32_RESET(APB1L, 3U)>; 156 interrupts = <50 0>; 157 interrupt-names = "global"; 158 st,prescaler = <0>; 159 status = "disabled"; 160 161 pwm { 162 compatible = "st,stm32-pwm"; 163 status = "disabled"; 164 #pwm-cells = <3>; 165 }; 166 167 counter { 168 compatible = "st,stm32-counter"; 169 status = "disabled"; 170 }; 171 }; 172 173 timers7: timers@40001400 { 174 compatible = "st,stm32-timers"; 175 reg = <0x40001400 0x400>; 176 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>; 177 resets = <&rctl STM32_RESET(APB1L, 5U)>; 178 interrupts = <55 0>; 179 interrupt-names = "global"; 180 st,prescaler = <0>; 181 status = "disabled"; 182 183 counter { 184 compatible = "st,stm32-counter"; 185 status = "disabled"; 186 }; 187 }; 188 189 timers8: timers@40013400 { 190 compatible = "st,stm32-timers"; 191 reg = <0x40013400 0x400>; 192 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>; 193 resets = <&rctl STM32_RESET(APB2, 13U)>; 194 interrupts = <43 0>, <44 0>, <45 0>, <46 0>; 195 interrupt-names = "brk", "up", "trgcom", "cc"; 196 st,prescaler = <0>; 197 status = "disabled"; 198 199 pwm { 200 compatible = "st,stm32-pwm"; 201 status = "disabled"; 202 #pwm-cells = <3>; 203 }; 204 }; 205 206 timers17: timers@40014800 { 207 compatible = "st,stm32-timers"; 208 reg = <0x40014800 0x400>; 209 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00040000>; 210 resets = <&rctl STM32_RESET(APB2, 18U)>; 211 interrupts = <26 0>; 212 interrupt-names = "global"; 213 st,prescaler = <0>; 214 status = "disabled"; 215 216 pwm { 217 compatible = "st,stm32-pwm"; 218 status = "disabled"; 219 #pwm-cells = <3>; 220 }; 221 222 counter { 223 compatible = "st,stm32-counter"; 224 status = "disabled"; 225 }; 226 }; 227 228 can1: can@40006400 { 229 compatible = "st,stm32-bxcan"; 230 reg = <0x40006400 0x400>; 231 interrupts = <19 0>, <20 0>, <21 0>, <22 0>; 232 interrupt-names = "TX", "RX0", "RX1", "SCE"; 233 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>; //RCC_APB1ENR1_CAN1EN 234 status = "disabled"; 235 sample-point = <875>; 236 }; 237 238 sdmmc1: sdmmc@40012800 { 239 compatible = "st,stm32-sdmmc"; 240 reg = <0x40012800 0x400>; 241 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000400>, 242 <&rcc STM32_SRC_MSI CLK48_SEL(3)>; 243 resets = <&rctl STM32_RESET(APB2, 10U)>; 244 interrupts = <49 0>; 245 status = "disabled"; 246 }; 247 248 dac1: dac@40007400 { 249 compatible = "st,stm32-dac"; 250 reg = <0x40007400 0x400>; 251 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>; 252 status = "disabled"; 253 #io-channel-cells = <1>; 254 }; 255 256 adc3: adc@50040200 { 257 compatible = "st,stm32-adc"; 258 reg = <0x50040200 0x100>; 259 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00002000>; 260 interrupts = <47 0>; 261 status = "disabled"; 262 #io-channel-cells = <1>; 263 }; 264 265 rtc@40002800 { 266 bbram: backup_regs { 267 compatible = "st,stm32-bbram"; 268 st,backup-regs = <32>; 269 status = "disabled"; 270 }; 271 }; 272 }; 273 274 die_temp: dietemp { 275 ts-cal2-temp = <110>; 276 }; 277}; 278
