1/*
2 * Copyright (c) 2023 SILA Embedded Solutions GmbH
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <st/l4/stm32l4.dtsi>
8
9/ {
10	soc {
11		compatible = "st,stm32l451", "st,stm32l4", "simple-bus";
12
13		clocks {
14			clk_hsi48: clk-hsi48 {
15				#clock-cells = <0>;
16				compatible = "fixed-clock";
17				clock-frequency = <DT_FREQ_M(48)>;
18				status = "disabled";
19			};
20		};
21
22		pinctrl: pin-controller@48000000 {
23			gpiod: gpio@48000c00 {
24				compatible = "st,stm32-gpio";
25				gpio-controller;
26				#gpio-cells = <2>;
27				reg = <0x48000c00 0x400>;
28				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000008>;
29			};
30
31			gpioe: gpio@48001000 {
32				compatible = "st,stm32-gpio";
33				gpio-controller;
34				#gpio-cells = <2>;
35				reg = <0x48001000 0x400>;
36				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
37			};
38		};
39
40		rng: rng@50060800 {
41			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00040000>,
42				 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
43		};
44
45		i2c2: i2c@40005800 {
46			compatible = "st,stm32-i2c-v2";
47			clock-frequency = <I2C_BITRATE_STANDARD>;
48			#address-cells = <1>;
49			#size-cells = <0>;
50			reg = <0x40005800 0x400>;
51			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
52			interrupts = <33 0>, <34 0>;
53			interrupt-names = "event", "error";
54			status = "disabled";
55		};
56
57		i2c4: i2c@40008400 {
58			compatible = "st,stm32-i2c-v2";
59			clock-frequency = <I2C_BITRATE_STANDARD>;
60			#address-cells = <1>;
61			#size-cells = <0>;
62			reg = <0x40008400 0x400>;
63			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000002>;
64			interrupts = <83 0>, <84 0>;
65			interrupt-names = "event", "error";
66			status = "disabled";
67		};
68
69		spi2: spi@40003800 {
70			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
71			#address-cells = <1>;
72			#size-cells = <0>;
73			reg = <0x40003800 0x400>;
74			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
75			interrupts = <36 5>;
76			status = "disabled";
77		};
78
79		spi3: spi@40003c00 {
80			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
81			#address-cells = <1>;
82			#size-cells = <0>;
83			reg = <0x40003c00 0x400>;
84			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
85			interrupts = <51 5>;
86			status = "disabled";
87		};
88
89		usart3: serial@40004800 {
90			compatible = "st,stm32-usart", "st,stm32-uart";
91			reg = <0x40004800 0x400>;
92			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
93			resets = <&rctl STM32_RESET(APB1L, 18U)>;
94			interrupts = <39 0>;
95			status = "disabled";
96		};
97
98		uart4: serial@40004c00 {
99			compatible = "st,stm32-uart";
100			reg = <0x40004c00 0x400>;
101			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
102			resets = <&rctl STM32_RESET(APB1L, 19U)>;
103			interrupts = <52 0>;
104			status = "disabled";
105		};
106
107		timers3: timers@40000400 {
108			compatible = "st,stm32-timers";
109			reg = <0x40000400 0x400>;
110			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
111			resets = <&rctl STM32_RESET(APB1L, 1U)>;
112			interrupts = <29 0>;
113			interrupt-names = "global";
114			st,prescaler = <0>;
115			status = "disabled";
116
117			pwm {
118				compatible = "st,stm32-pwm";
119				status = "disabled";
120				#pwm-cells = <3>;
121			};
122
123			counter {
124				compatible = "st,stm32-counter";
125				status = "disabled";
126			};
127		};
128
129		dac1: dac@40007400 {
130			compatible = "st,stm32-dac";
131			reg = <0x40007400 0x400>;
132			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
133			status = "disabled";
134			#io-channel-cells = <1>;
135		};
136
137		can1: can@40006400 {
138			compatible = "st,stm32-bxcan";
139			reg = <0x40006400 0x400>;
140			interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
141			interrupt-names = "TX", "RX0", "RX1", "SCE";
142			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>; //RCC_APB1ENR1_CAN1EN
143			status = "disabled";
144			sample-point = <875>;
145		};
146
147		sdmmc1: sdmmc@40012800 {
148			compatible = "st,stm32-sdmmc";
149			reg = <0x40012800 0x400>;
150			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000400>,
151				 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
152			resets = <&rctl STM32_RESET(APB2, 10U)>;
153			interrupts = <49 0>;
154			status = "disabled";
155		};
156
157		rtc@40002800 {
158			bbram: backup_regs {
159				compatible = "st,stm32-bbram";
160				st,backup-regs = <32>;
161				status = "disabled";
162			};
163		};
164	};
165};
166