1/* 2 * Copyright (c) 2023 Nuvoton Technology Corporation. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include <arm/armv7-m.dtsi> 8#include <mem.h> 9#include <zephyr/dt-bindings/pinctrl/numaker-m46x-pinctrl.h> 10#include <zephyr/dt-bindings/clock/numaker_m46x_clock.h> 11#include <zephyr/dt-bindings/reset/numaker_m46x_reset.h> 12#include <zephyr/dt-bindings/gpio/gpio.h> 13 14/ { 15 chosen { 16 zephyr,flash-controller = &fmc; 17 }; 18 19 cpus { 20 #address-cells = <1>; 21 #size-cells = <0>; 22 23 cpu@0 { 24 device_type = "cpu"; 25 compatible = "arm,cortex-m4f"; 26 reg = <0>; 27 }; 28 }; 29 30 sram0: memory@20000000 { 31 compatible = "mmio-sram"; 32 reg = <0x20000000 DT_SIZE_K(512)>; 33 }; 34 35 sysclk: system-clock { 36 compatible = "fixed-clock"; 37 clock-frequency = <200000000>; 38 #clock-cells = <0>; 39 }; 40 41 soc { 42 scc: system-clock-controller@40000200 { 43 compatible = "nuvoton,numaker-scc"; 44 reg = <0x40000200 0x100>; 45 #clock-cells = <0>; 46 /* hxt = "enable"; */ 47 /* lxt = "enable"; */ 48 clk-pclkdiv = <(NUMAKER_CLK_PCLKDIV_APB0DIV_DIV2 | 49 NUMAKER_CLK_PCLKDIV_APB1DIV_DIV2)>; 50 core-clock = <200000000>; 51 52 pcc: peripheral-clock-controller { 53 compatible = "nuvoton,numaker-pcc"; 54 #clock-cells = <3>; 55 }; 56 }; 57 58 rst: reset-controller@40000000 { 59 compatible = "nuvoton,numaker-rst"; 60 reg = <0x40000000 0x20>; 61 #reset-cells = <1>; 62 status = "okay"; 63 }; 64 65 fmc: flash-controller@4000c000 { 66 compatible = "nuvoton,numaker-fmc"; 67 reg = <0x4000c000 0x110>; 68 #address-cells = <1>; 69 #size-cells = <1>; 70 71 flash0: flash@0 { 72 compatible = "soc-nv-flash"; 73 reg = <0 DT_SIZE_K(1024)>; 74 erase-block-size = <4096>; 75 write-block-size = <4>; 76 }; 77 }; 78 79 uart0: serial@40070000 { 80 compatible = "nuvoton,numaker-uart"; 81 reg = <0x40070000 0x1000>; 82 interrupts = <36 0>; 83 resets = <&rst NUMAKER_UART0_RST>; 84 clocks = <&pcc NUMAKER_UART0_MODULE NUMAKER_CLK_CLKSEL1_UART0SEL_HIRC 85 NUMAKER_CLK_CLKDIV0_UART0(1)>; 86 status = "disabled"; 87 }; 88 89 uart1: serial@40071000 { 90 compatible = "nuvoton,numaker-uart"; 91 reg = <0x40071000 0x1000>; 92 interrupts = <37 0>; 93 resets = <&rst NUMAKER_UART1_RST>; 94 clocks = <&pcc NUMAKER_UART1_MODULE NUMAKER_CLK_CLKSEL1_UART1SEL_HIRC 95 NUMAKER_CLK_CLKDIV0_UART1(1)>; 96 status = "disabled"; 97 }; 98 99 uart2: serial@40072000 { 100 compatible = "nuvoton,numaker-uart"; 101 reg = <0x40072000 0x1000>; 102 interrupts = <48 0>; 103 resets = <&rst NUMAKER_UART2_RST>; 104 clocks = <&pcc NUMAKER_UART2_MODULE NUMAKER_CLK_CLKSEL3_UART2SEL_HIRC 105 NUMAKER_CLK_CLKDIV4_UART2(1)>; 106 status = "disabled"; 107 }; 108 109 uart3: serial@40073000 { 110 compatible = "nuvoton,numaker-uart"; 111 reg = <0x40073000 0x1000>; 112 interrupts = <49 0>; 113 resets = <&rst NUMAKER_UART3_RST>; 114 clocks = <&pcc NUMAKER_UART3_MODULE NUMAKER_CLK_CLKSEL3_UART3SEL_HIRC 115 NUMAKER_CLK_CLKDIV4_UART3(1)>; 116 status = "disabled"; 117 }; 118 119 uart4: serial@40074000 { 120 compatible = "nuvoton,numaker-uart"; 121 reg = <0x40074000 0x1000>; 122 interrupts = <74 0>; 123 resets = <&rst NUMAKER_UART4_RST>; 124 clocks = <&pcc NUMAKER_UART4_MODULE NUMAKER_CLK_CLKSEL3_UART4SEL_HIRC 125 NUMAKER_CLK_CLKDIV4_UART4(1)>; 126 status = "disabled"; 127 }; 128 129 uart5: serial@40075000 { 130 compatible = "nuvoton,numaker-uart"; 131 reg = <0x40075000 0x1000>; 132 interrupts = <75 0>; 133 resets = <&rst NUMAKER_UART5_RST>; 134 clocks = <&pcc NUMAKER_UART5_MODULE NUMAKER_CLK_CLKSEL3_UART5SEL_HIRC 135 NUMAKER_CLK_CLKDIV4_UART5(1)>; 136 status = "disabled"; 137 }; 138 139 uart6: serial@40076000 { 140 compatible = "nuvoton,numaker-uart"; 141 reg = <0x40076000 0x1000>; 142 interrupts = <102 0>; 143 resets = <&rst NUMAKER_UART6_RST>; 144 clocks = <&pcc NUMAKER_UART6_MODULE NUMAKER_CLK_CLKSEL3_UART6SEL_HIRC 145 NUMAKER_CLK_CLKDIV4_UART6(1)>; 146 status = "disabled"; 147 }; 148 149 uart7: serial@40077000 { 150 compatible = "nuvoton,numaker-uart"; 151 reg = <0x40077000 0x1000>; 152 interrupts = <103 0>; 153 resets = <&rst NUMAKER_UART7_RST>; 154 clocks = <&pcc NUMAKER_UART7_MODULE NUMAKER_CLK_CLKSEL3_UART7SEL_HIRC 155 NUMAKER_CLK_CLKDIV4_UART7(1)>; 156 status = "disabled"; 157 }; 158 159 uart8: serial@40078000 { 160 compatible = "nuvoton,numaker-uart"; 161 reg = <0x40078000 0x1000>; 162 interrupts = <99 0>; 163 resets = <&rst NUMAKER_UART8_RST>; 164 clocks = <&pcc NUMAKER_UART8_MODULE NUMAKER_CLK_CLKSEL2_UART8SEL_HIRC 165 NUMAKER_CLK_CLKDIV5_UART8(1)>; 166 status = "disabled"; 167 }; 168 169 uart9: serial@40079000 { 170 compatible = "nuvoton,numaker-uart"; 171 reg = <0x40079000 0x1000>; 172 interrupts = <100 0>; 173 resets = <&rst NUMAKER_UART9_RST>; 174 clocks = <&pcc NUMAKER_UART9_MODULE NUMAKER_CLK_CLKSEL2_UART9SEL_HIRC 175 NUMAKER_CLK_CLKDIV5_UART9(1)>; 176 status = "disabled"; 177 }; 178 179 pinctrl: pin-controller@40000080 { 180 compatible = "nuvoton,numaker-pinctrl"; 181 reg = <0x40000080 0x28 182 0x40000500 0xa0>; 183 reg-names = "mfos", "mfp"; 184 status = "okay"; 185 }; 186 187 gpioa: gpio@40004000 { 188 compatible = "nuvoton,numaker-gpio"; 189 gpio-controller; 190 #gpio-cells = <2>; 191 reg = <0x40004000 0x40>; 192 clocks = <&pcc NUMAKER_GPA_MODULE 0 0>; 193 status = "disabled"; 194 interrupts = <16 2>; 195 }; 196 197 gpiob: gpio@40004040 { 198 compatible = "nuvoton,numaker-gpio"; 199 gpio-controller; 200 #gpio-cells = <2>; 201 reg = <0x40004040 0x40>; 202 clocks = <&pcc NUMAKER_GPB_MODULE 0 0>; 203 status = "disabled"; 204 interrupts = <17 2>; 205 }; 206 207 gpioc: gpio@40004080 { 208 compatible = "nuvoton,numaker-gpio"; 209 gpio-controller; 210 #gpio-cells = <2>; 211 reg = <0x40004080 0x40>; 212 clocks = <&pcc NUMAKER_GPC_MODULE 0 0>; 213 status = "disabled"; 214 interrupts = <18 2>; 215 }; 216 217 gpiod: gpio@400040c0 { 218 compatible = "nuvoton,numaker-gpio"; 219 gpio-controller; 220 #gpio-cells = <2>; 221 reg = <0x400040c0 0x40>; 222 clocks = <&pcc NUMAKER_GPD_MODULE 0 0>; 223 status = "disabled"; 224 interrupts = <19 2>; 225 }; 226 227 gpioe: gpio@40004100 { 228 compatible = "nuvoton,numaker-gpio"; 229 gpio-controller; 230 #gpio-cells = <2>; 231 reg = <0x40004100 0x40>; 232 clocks = <&pcc NUMAKER_GPE_MODULE 0 0>; 233 status = "disabled"; 234 interrupts = <20 2>; 235 }; 236 237 gpiof: gpio@40004140 { 238 compatible = "nuvoton,numaker-gpio"; 239 gpio-controller; 240 #gpio-cells = <2>; 241 reg = <0x40004140 0x40>; 242 clocks = <&pcc NUMAKER_GPF_MODULE 0 0>; 243 status = "disabled"; 244 interrupts = <21 2>; 245 }; 246 247 gpiog: gpio@40004180 { 248 compatible = "nuvoton,numaker-gpio"; 249 gpio-controller; 250 #gpio-cells = <2>; 251 reg = <0x40004180 0x40>; 252 clocks = <&pcc NUMAKER_GPG_MODULE 0 0>; 253 status = "disabled"; 254 interrupts = <72 2>; 255 }; 256 257 gpioh: gpio@400041c0 { 258 compatible = "nuvoton,numaker-gpio"; 259 gpio-controller; 260 #gpio-cells = <2>; 261 reg = <0x400041c0 0x40>; 262 clocks = <&pcc NUMAKER_GPH_MODULE 0 0>; 263 status = "disabled"; 264 interrupts = <88 2>; 265 }; 266 267 gpioi: gpio@40004200 { 268 compatible = "nuvoton,numaker-gpio"; 269 gpio-controller; 270 #gpio-cells = <2>; 271 reg = <0x40004200 0x40>; 272 clocks = <&pcc NUMAKER_GPI_MODULE 0 0>; 273 status = "disabled"; 274 interrupts = <110 2>; 275 }; 276 277 gpioj: gpio@40004240 { 278 compatible = "nuvoton,numaker-gpio"; 279 gpio-controller; 280 #gpio-cells = <2>; 281 reg = <0x40004240 0x40>; 282 clocks = <&pcc NUMAKER_GPJ_MODULE 0 0>; 283 status = "disabled"; 284 interrupts = <61 2>; 285 }; 286 287 spi0: spi@40061000 { 288 compatible = "nuvoton,numaker-spi"; 289 reg = <0x40061000 0x6c>; 290 interrupts = <23 0>; 291 resets = <&rst NUMAKER_SPI0_RST>; 292 clocks = <&pcc NUMAKER_SPI0_MODULE NUMAKER_CLK_CLKSEL2_SPI0SEL_HIRC 0>; 293 #address-cells = <1>; 294 #size-cells = <0>; 295 status = "disabled"; 296 }; 297 298 spi1: spi@40062000 { 299 compatible = "nuvoton,numaker-spi"; 300 reg = <0x40062000 0x6c>; 301 interrupts = <51 0>; 302 resets = <&rst NUMAKER_SPI1_RST>; 303 clocks = <&pcc NUMAKER_SPI1_MODULE NUMAKER_CLK_CLKSEL2_SPI1SEL_HIRC 0>; 304 #address-cells = <1>; 305 #size-cells = <0>; 306 status = "disabled"; 307 }; 308 309 spi2: spi@40063000 { 310 compatible = "nuvoton,numaker-spi"; 311 reg = <0x40063000 0x6c>; 312 interrupts = <52 0>; 313 resets = <&rst NUMAKER_SPI2_RST>; 314 clocks = <&pcc NUMAKER_SPI2_MODULE NUMAKER_CLK_CLKSEL3_SPI2SEL_HIRC 0>; 315 #address-cells = <1>; 316 #size-cells = <0>; 317 status = "disabled"; 318 }; 319 320 spi3: spi@40064000 { 321 compatible = "nuvoton,numaker-spi"; 322 reg = <0x40064000 0x6c>; 323 interrupts = <62 0>; 324 resets = <&rst NUMAKER_SPI3_RST>; 325 clocks = <&pcc NUMAKER_SPI3_MODULE NUMAKER_CLK_CLKSEL3_SPI3SEL_HIRC 0>; 326 #address-cells = <1>; 327 #size-cells = <0>; 328 status = "disabled"; 329 }; 330 331 spi4: spi@40065000 { 332 compatible = "nuvoton,numaker-spi"; 333 reg = <0x40065000 0x6c>; 334 interrupts = <63 0>; 335 resets = <&rst NUMAKER_SPI4_RST>; 336 clocks = <&pcc NUMAKER_SPI4_MODULE NUMAKER_CLK_CLKSEL4_SPI4SEL_HIRC 0>; 337 #address-cells = <1>; 338 #size-cells = <0>; 339 status = "disabled"; 340 }; 341 342 spi5: spi@40066000 { 343 compatible = "nuvoton,numaker-spi"; 344 reg = <0x40066000 0x6c>; 345 interrupts = <57 0>; 346 resets = <&rst NUMAKER_SPI5_RST>; 347 clocks = <&pcc NUMAKER_SPI5_MODULE NUMAKER_CLK_CLKSEL4_SPI5SEL_HIRC 0>; 348 #address-cells = <1>; 349 #size-cells = <0>; 350 status = "disabled"; 351 }; 352 353 spi6: spi@40067000 { 354 compatible = "nuvoton,numaker-spi"; 355 reg = <0x40067000 0x6c>; 356 interrupts = <70 0>; 357 resets = <&rst NUMAKER_SPI6_RST>; 358 clocks = <&pcc NUMAKER_SPI6_MODULE NUMAKER_CLK_CLKSEL4_SPI6SEL_HIRC 0>; 359 #address-cells = <1>; 360 #size-cells = <0>; 361 status = "disabled"; 362 }; 363 364 spi7: spi@40068000 { 365 compatible = "nuvoton,numaker-spi"; 366 reg = <0x40068000 0x6c>; 367 interrupts = <77 0>; 368 resets = <&rst NUMAKER_SPI7_RST>; 369 clocks = <&pcc NUMAKER_SPI7_MODULE NUMAKER_CLK_CLKSEL4_SPI7SEL_HIRC 0>; 370 #address-cells = <1>; 371 #size-cells = <0>; 372 status = "disabled"; 373 }; 374 375 spi8: spi@4006b000 { 376 compatible = "nuvoton,numaker-spi"; 377 reg = <0x4006b000 0x6c>; 378 interrupts = <108 0>; 379 resets = <&rst NUMAKER_SPI8_RST>; 380 clocks = <&pcc NUMAKER_SPI8_MODULE NUMAKER_CLK_CLKSEL4_SPI8SEL_HIRC 0>; 381 #address-cells = <1>; 382 #size-cells = <0>; 383 status = "disabled"; 384 }; 385 386 spi9: spi@4006c000 { 387 compatible = "nuvoton,numaker-spi"; 388 reg = <0x4006c000 0x6c>; 389 interrupts = <111 0>; 390 resets = <&rst NUMAKER_SPI9_RST>; 391 clocks = <&pcc NUMAKER_SPI9_MODULE NUMAKER_CLK_CLKSEL4_SPI9SEL_HIRC 0>; 392 #address-cells = <1>; 393 #size-cells = <0>; 394 status = "disabled"; 395 }; 396 397 spi10: spi@4006d000 { 398 compatible = "nuvoton,numaker-spi"; 399 reg = <0x4006d000 0x6c>; 400 interrupts = <119 0>; 401 resets = <&rst NUMAKER_SPI10_RST>; 402 clocks = <&pcc NUMAKER_SPI10_MODULE NUMAKER_CLK_CLKSEL4_SPI10SEL_HIRC 0>; 403 #address-cells = <1>; 404 #size-cells = <0>; 405 status = "disabled"; 406 }; 407 408 epwm0: epwm@40058000 { 409 compatible = "nuvoton,numaker-pwm"; 410 reg = <0x40058000 0x37c>; 411 interrupts = <25 0>, <26 0>, <27 0>; 412 interrupt-names = "pair0", "pair1", "pair2"; 413 resets = <&rst NUMAKER_EPWM0_RST>; 414 prescaler = <19>; 415 clocks = <&pcc NUMAKER_EPWM0_MODULE NUMAKER_CLK_CLKSEL2_EPWM0SEL_PCLK0 0>; 416 #pwm-cells = <3>; 417 status = "disabled"; 418 }; 419 420 epwm1: epwm@40059000 { 421 compatible = "nuvoton,numaker-pwm"; 422 reg = <0x40059000 0x37c>; 423 interrupts = <29 0>, <30 0>, <31 0>; 424 interrupt-names = "pair0", "pair1", "pair2"; 425 resets = <&rst NUMAKER_EPWM1_RST>; 426 prescaler = <19>; 427 clocks = <&pcc NUMAKER_EPWM1_MODULE NUMAKER_CLK_CLKSEL2_EPWM1SEL_PCLK1 0>; 428 #pwm-cells = <3>; 429 status = "disabled"; 430 }; 431 }; 432}; 433 434&nvic { 435 arm,num-irq-priority-bits = <4>; 436}; 437
