1/*
2 * Copyright (c) 2022 Liam Clark
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <st/l4/stm32l4.dtsi>
8
9/ {
10	soc {
11		compatible = "st,stm32l431", "st,stm32l4", "simple-bus";
12
13		clocks {
14			clk_hsi48: clk-hsi48 {
15				#clock-cells = <0>;
16				compatible = "fixed-clock";
17				clock-frequency = <DT_FREQ_M(48)>;
18				status = "disabled";
19			};
20		};
21
22		pinctrl: pin-controller@48000000 {
23
24			gpiod: gpio@48000c00 {
25				compatible = "st,stm32-gpio";
26				reg = <0x48000c00 0x400>;
27				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000008>;
28				gpio-controller;
29				#gpio-cells = <2>;
30			};
31
32			gpioe: gpio@48001000 {
33				compatible = "st,stm32-gpio";
34				reg = <0x48001000 0x400>;
35				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
36				gpio-controller;
37				#gpio-cells = <2>;
38			};
39
40		};
41
42		rng: rng@50060800 {
43			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00040000>,
44				 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
45		};
46
47		i2c2: i2c@40005800 {
48			compatible = "st,stm32-i2c-v2";
49			#address-cells = <1>;
50			#size-cells = <0>;
51			reg = <0x40005800 0x400>;
52			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
53			clock-frequency = <I2C_BITRATE_STANDARD>;
54			interrupts = <33 0>, <34 0>;
55			interrupt-names = "event", "error";
56			status = "disabled";
57		};
58
59		spi2: spi@40003800 {
60			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
61			#address-cells = <1>;
62			#size-cells = <0>;
63			reg = <0x40003800 0x400>;
64			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
65			interrupts = <36 5>;
66			status = "disabled";
67		};
68
69		spi3: spi@40003c00 {
70			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
71			#address-cells = <1>;
72			#size-cells = <0>;
73			reg = <0x40003c00 0x400>;
74			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
75			interrupts = <51 5>;
76			status = "disabled";
77		};
78
79		usart3: serial@40004800 {
80			compatible = "st,stm32-usart", "st,stm32-uart";
81			reg = <0x40004800 0x400>;
82			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
83			resets = <&rctl STM32_RESET(APB1L, 18U)>;
84			interrupts = <39 0>;
85			status = "disabled";
86		};
87
88		timers7: timers@40001400 {
89			compatible = "st,stm32-timers";
90			reg = <0x40001400 0x400>;
91			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
92			resets = <&rctl STM32_RESET(APB1L, 5U)>;
93			interrupts = <55 0>;
94			interrupt-names = "global";
95			st,prescaler = <0>;
96			status = "disabled";
97
98			counter {
99				compatible = "st,stm32-counter";
100				status = "disabled";
101			};
102		};
103
104		can1: can@40006400 {
105			compatible = "st,stm32-bxcan";
106			reg = <0x40006400 0x400>;
107			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
108			interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
109			interrupt-names = "TX", "RX0", "RX1", "SCE";
110			sample-point = <875>;
111			status = "disabled";
112		};
113
114		sdmmc1: sdmmc@40012800 {
115			compatible = "st,stm32-sdmmc";
116			reg = <0x40012800 0x400>;
117			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000400>,
118				 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
119			resets = <&rctl STM32_RESET(APB2, 10U)>;
120			interrupts = <49 0>;
121			status = "disabled";
122		};
123
124		dac1: dac@40007400 {
125			compatible = "st,stm32-dac";
126			reg = <0x40007400 0x400>;
127			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
128			#io-channel-cells = <1>;
129			status = "disabled";
130		};
131	};
132};
133