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Searched refs:SPI2_INTR_SOURCE (Results 1 – 10 of 10) sorted by relevance

/Zephyr-latest/include/zephyr/dt-bindings/interrupt-controller/
Desp-esp32c2-intmux.h26 #define SPI2_INTR_SOURCE 16 macro
Desp-esp32c3-intmux.h29 #define SPI2_INTR_SOURCE 19 macro
Desp-xtensa-intmux.h40 #define SPI2_INTR_SOURCE 30 /* SPI2, level */ macro
Desp32s3-xtensa-intmux.h31 #define SPI2_INTR_SOURCE 21 /* interrupt of SPI2, level*/ macro
Desp32s2-xtensa-intmux.h43 #define SPI2_INTR_SOURCE 33 /* SPI2, level */ macro
/Zephyr-latest/dts/riscv/espressif/esp32c2/
Desp32c2_common.dtsi195 interrupts = <SPI2_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
/Zephyr-latest/dts/riscv/espressif/esp32c3/
Desp32c3_common.dtsi271 interrupts = <SPI2_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
/Zephyr-latest/dts/xtensa/espressif/esp32s2/
Desp32s2_common.dtsi297 interrupts = <SPI2_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
/Zephyr-latest/dts/xtensa/espressif/esp32/
Desp32_common.dtsi374 interrupts = <SPI2_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
/Zephyr-latest/dts/xtensa/espressif/esp32s3/
Desp32s3_common.dtsi327 interrupts = <SPI2_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;