| /Zephyr-latest/include/zephyr/dt-bindings/pinctrl/silabs/ |
| D | xg23-pinctrl.h | 173 #define ACMP0_ACMPOUT_PA1 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x1)
183 #define ACMP0_ACMPOUT_PB0 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x0)
184 #define ACMP0_ACMPOUT_PB1 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x1)
185 #define ACMP0_ACMPOUT_PB2 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x2)
186 #define ACMP0_ACMPOUT_PB3 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x3)
187 #define ACMP0_ACMPOUT_PB4 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x4)
188 #define ACMP0_ACMPOUT_PB5 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x5)
189 #define ACMP0_ACMPOUT_PB6 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x6)
191 #define ACMP0_ACMPOUT_PC1 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x1)
201 #define ACMP0_ACMPOUT_PD1 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x1)
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| D | xg22-pinctrl.h | 127 #define CMU_CLKOUT0_PC1 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x1)
135 #define CMU_CLKOUT0_PD1 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x1)
139 #define CMU_CLKOUT1_PC1 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x1)
147 #define CMU_CLKOUT1_PD1 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x1)
151 #define CMU_CLKOUT2_PA1 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x1)
159 #define CMU_CLKOUT2_PB0 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x0)
160 #define CMU_CLKOUT2_PB1 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x1)
161 #define CMU_CLKOUT2_PB2 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x2)
162 #define CMU_CLKOUT2_PB3 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x3)
163 #define CMU_CLKOUT2_PB4 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x4)
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| D | xg27-pinctrl.h | 131 #define ACMP0_ACMPOUT_PA1 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x1)
139 #define ACMP0_ACMPOUT_PB0 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x0)
140 #define ACMP0_ACMPOUT_PB1 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x1)
141 #define ACMP0_ACMPOUT_PB2 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x2)
142 #define ACMP0_ACMPOUT_PB3 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x3)
143 #define ACMP0_ACMPOUT_PB4 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x4)
145 #define ACMP0_ACMPOUT_PC1 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x1)
153 #define ACMP0_ACMPOUT_PD1 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x1)
158 #define CMU_CLKOUT0_PC1 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x1)
166 #define CMU_CLKOUT0_PD1 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x1)
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| D | xg24-pinctrl.h | 156 #define ACMP0_ACMPOUT_PA1 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x1)
165 #define ACMP0_ACMPOUT_PB0 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x0)
166 #define ACMP0_ACMPOUT_PB1 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x1)
167 #define ACMP0_ACMPOUT_PB2 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x2)
168 #define ACMP0_ACMPOUT_PB3 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x3)
169 #define ACMP0_ACMPOUT_PB4 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x4)
170 #define ACMP0_ACMPOUT_PB5 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x5)
172 #define ACMP0_ACMPOUT_PC1 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x1)
182 #define ACMP0_ACMPOUT_PD1 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x1)
189 #define ACMP1_ACMPOUT_PA1 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x1)
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| D | xg21-pinctrl.h | 111 #define ACMP0_ACMPOUT_PA1 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x1)
117 #define ACMP0_ACMPOUT_PB0 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x0)
118 #define ACMP0_ACMPOUT_PB1 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x1)
120 #define ACMP0_ACMPOUT_PC1 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x1)
126 #define ACMP0_ACMPOUT_PD1 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x1)
132 #define ACMP1_ACMPOUT_PA1 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x1)
138 #define ACMP1_ACMPOUT_PB0 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0x0)
139 #define ACMP1_ACMPOUT_PB1 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0x1)
141 #define ACMP1_ACMPOUT_PC1 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x1)
147 #define ACMP1_ACMPOUT_PD1 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x1)
[all …]
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| /Zephyr-latest/drivers/disk/nvme/ |
| D | nvme_helpers.h | 31 #define NVME_CAP_LO_REG_CQR_MASK (0x1)
48 #define NVME_CAP_HI_REG_NSSRS_MASK (0x1)
52 #define NVME_CAP_HI_REG_CSS_NVM_MASK (0x1)
54 #define NVME_CAP_HI_REG_BPS_MASK (0x1)
60 #define NVME_CAP_HI_REG_PMRS_MASK (0x1)
62 #define NVME_CAP_HI_REG_CMBS_MASK (0x1)
83 #define NVME_CC_REG_EN_MASK (0x1)
98 #define NVME_CSTS_REG_RDY_MASK (0x1)
100 #define NVME_CSTS_REG_CFS_MASK (0x1)
104 #define NVME_CSTS_REG_NVSRO_MASK (0x1)
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| /Zephyr-latest/soc/microchip/mec/common/ |
| D | soc_dt.h | 12 #define MCHP_XEC_PIN_FEAT_EN 0x1
13 #define MCHP_XEC_NO_PULL 0x1
14 #define MCHP_XEC_PULL_UP 0x1
15 #define MCHP_XEC_PULL_DOWN 0x1
16 #define MCHP_XEC_PUSH_PULL 0x1
17 #define MCHP_XEC_OPEN_DRAIN 0x1
18 #define MCHP_XEC_OUT_DIS 0x1
19 #define MCHP_XEC_OUT_EN 0x1
20 #define MCHP_XEC_OUT_DRV_LOW 0x1
21 #define MCHP_XEC_OUT_DRV_HIGH 0x1
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| /Zephyr-latest/drivers/watchdog/ |
| D | wdt_nxp_fs26.h | 13 #define FS26_M_FS (0x1 << 31)
20 #define FS26_RW (0x1 << 24)
29 #define FS26_M_AVAL (0x1 << 31)
31 #define FS26_FS_EN (0x1 << 30)
33 #define FS26_FS_G (0x1 << 29)
35 #define FS26_COM_G (0x1 << 28)
37 #define FS26_WIO_G (0x1 << 27)
39 #define FS26_VSUP_G (0x1 << 26)
41 #define FS26_REG_G (0x1 << 25)
43 #define FS26_TSD_G (0x1 << 24)
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| /Zephyr-latest/soc/sifive/sifive_freedom/fe300/ |
| D | prci.h | 27 #define ROSC_EN(x) (((x) & 0x1) << 30)
28 #define ROSC_RDY(x) (((x) & 0x1) << 31)
30 #define XOSC_EN(x) (((x) & 0x1) << 30)
31 #define XOSC_RDY(x) (((x) & 0x1) << 31)
37 #define PLL_SEL(x) (((x) & 0x1) << 16)
38 #define PLL_REFSEL(x) (((x) & 0x1) << 17)
39 #define PLL_BYPASS(x) (((x) & 0x1) << 18)
40 #define PLL_LOCK(x) (((x) & 0x1) << 31)
42 #define PLL_R_default 0x1
47 #define PLL_REFSEL_HFXOSC 0x1
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| /Zephyr-latest/arch/arm64/core/ |
| D | switch.S | 40 stp x19, x20, [x1, #_thread_offset_to_callee_saved_x19_x20]
41 stp x21, x22, [x1, #_thread_offset_to_callee_saved_x21_x22]
42 stp x23, x24, [x1, #_thread_offset_to_callee_saved_x23_x24]
43 stp x25, x26, [x1, #_thread_offset_to_callee_saved_x25_x26]
44 stp x27, x28, [x1, #_thread_offset_to_callee_saved_x27_x28]
46 stp x29, x4, [x1, #_thread_offset_to_callee_saved_x29_sp_el0]
48 str x29, [x1, #_thread_offset_to_callee_saved_x29_sp_el0]
53 stp x4, lr, [x1, #_thread_offset_to_callee_saved_sp_elx_lr]
58 strb w2, [x1, #_thread_offset_to_exception_depth]
72 stp x0, x1, [sp, #-16]!
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| D | isr_wrapper.S | 43 ldr x1, [x0, #___cpu_t_irq_stack_OFFSET]
45 mov sp, x1
48 sub x1, x1, #CONFIG_ISR_STACK_SIZE
49 str x1, [x0, #_cpu_offset_to_current_stack_limit]
81 mov x1, #(CONFIG_NUM_IRQS - 1)
82 cmp x0, x1
88 ldr x1, =_sw_isr_table
89 add x1, x1, x0, lsl #4 /* table is 16-byte wide */
90 ldp x0, x3, [x1] /* arg in x0, ISR in x3 */
124 ldr x1, [sp]
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| /Zephyr-latest/drivers/sensor/ti/fdc2x1x/ |
| D | fdc2x1x.h | 75 #define FDC2X1X_STATUS_ERR_WD(x) (((x) >> 11) & 0x1)
76 #define FDC2X1X_STATUS_ERR_AHW(x) (((x) >> 10) & 0x1)
77 #define FDC2X1X_STATUS_ERR_ALW(x) (((x) >> 9) & 0x1)
78 #define FDC2X1X_STATUS_DRDY(x) (((x) >> 6) & 0x1)
79 #define FDC2X1X_STATUS_CH0_UNREADCONV_RDY(x) (((x) >> 3) & 0x1)
80 #define FDC2X1X_STATUS_CH1_UNREADCONV_RDY(x) (((x) >> 2) & 0x1)
81 #define FDC2X1X_STATUS_CH2_UNREADCONV_RDY(x) (((x) >> 1) & 0x1)
82 #define FDC2X1X_STATUS_CH3_UNREADCONV_RDY(x) (((x) >> 0) & 0x1)
86 #define FDC2X1X_ERROR_CONFIG_WD_ERR2OUT_SET(x) (((x) & 0x1) << 13)
87 #define FDC2X1X_ERROR_CONFIG_WD_ERR2OUT_GET(x) (((x) >> 13) & 0x1)
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| /Zephyr-latest/include/zephyr/dt-bindings/display/ |
| D | panel.h | 26 #define PANEL_PIXEL_FORMAT_RGB_888 (0x1 << 0)
27 #define PANEL_PIXEL_FORMAT_MONO01 (0x1 << 1) /* 0=Black 1=White */
28 #define PANEL_PIXEL_FORMAT_MONO10 (0x1 << 2) /* 1=Black 0=White */
29 #define PANEL_PIXEL_FORMAT_ARGB_8888 (0x1 << 3)
30 #define PANEL_PIXEL_FORMAT_RGB_565 (0x1 << 4)
31 #define PANEL_PIXEL_FORMAT_BGR_565 (0x1 << 5)
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| /Zephyr-latest/tests/kernel/common/src/ |
| D | printk.c | 61 "0x1 0x1 0x1 0x1 0x1\n"
62 "0x1 0x1 0x1 0x1\n"
74 "0x1 0x01 0x0001 0x00000001 0x0000000000000001\n"
75 "0x1 0x 1 0x 1 0x 1\n"
93 "0x1 0x1 0x1 0x1 0x1\n"
94 "0x1 0x1 0x1 0x1\n"
101 "0x1 0x01 0x0001 0x00000001 0x0000000000000001\n"
102 "0x1 0x 1 0x 1 0x 1\n"
117 "0x1 0x01 0x0001 0x00000001 0x0000000000000001\n"
118 "0x1 0x 1 0x 1 0x 1\n"
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| /Zephyr-latest/include/zephyr/dt-bindings/pinctrl/ |
| D | stm32f1-pinctrl.h | 55 #define GPIO_IN 0x1 /* Input */
77 #define STM32_MODE_OUTPUT (0x1 << STM32_MODE_INOUT_SHIFT)
78 #define STM32_MODE_INOUT_MASK 0x1
83 #define STM32_CNF_IN_FLOAT (0x1 << STM32_CNF_IN_SHIFT)
90 #define STM32_MODE_OUTPUT_MAX_2 (0x1 << STM32_MODE_OSPEED_SHIFT)
96 #define STM32_CNF_OPEN_DRAIN (0x1 << STM32_CNF_OUT_0_SHIFT)
97 #define STM32_CNF_OUT_0_MASK 0x1
101 #define STM32_CNF_ALT_FUNC (0x1 << STM32_CNF_OUT_1_SHIFT)
102 #define STM32_CNF_OUT_1_MASK 0x1
107 #define STM32_PUPD_PULL_UP (0x1 << STM32_PUPD_SHIFT)
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| D | xmc4xxx-pinctrl.h | 22 #define XMC4XXX_PULL_DOWN_MASK 0x1
25 #define XMC4XXX_PULL_UP_MASK 0x1
28 #define XMC4XXX_PUSH_PULL_MASK 0x1
31 #define XMC4XXX_OPEN_DRAIN_MASK 0x1
34 #define XMC4XXX_OUT_HIGH_MASK 0x1
37 #define XMC4XXX_OUT_LOW_MASK 0x1
40 #define XMC4XXX_INV_INPUT_MASK 0x1
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| /Zephyr-latest/boards/toradex/colibri_imx7d/ |
| D | colibri_imx7d-pinctrl.dtsi | 18 drive-strength = "x1";
30 drive-strength = "x1";
42 drive-strength = "x1";
54 drive-strength = "x1";
66 drive-strength = "x1";
77 drive-strength = "x1";
88 drive-strength = "x1";
99 drive-strength = "x1";
110 drive-strength = "x1";
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| /Zephyr-latest/drivers/pinctrl/ |
| D | pinctrl_mci_io_mux.c | 64 mask = (0x1 << (gpio_idx & 0x1F)); in configure_pin_props()
84 ~(0x1 << IOMUX_GET_CTIMER_CLR_OFFSET(gpio_setting)); in select_gpio_mode()
86 ~(0x1 << IOMUX_GET_CTIMER_CLR_OFFSET(gpio_setting)); in select_gpio_mode()
91 ~(0x1 << IOMUX_GET_SCTIMER_IN_CLR_OFFSET(gpio_setting)); in select_gpio_mode()
95 ~(0x1 << (IOMUX_GET_SCTIMER_OUT_CLR_OFFSET(gpio_setting) + 16)); in select_gpio_mode()
98 mci_iomux->S_GPIO &= ~(0x1 << (gpio_idx - 32)); in select_gpio_mode()
125 (0x1 << IOMUX_GET_FLEXCOMM_BIT(pin_mux)); in pinctrl_configure_pins()
129 (0x1 << IOMUX_GET_FSEL_BIT(pin_mux)); in pinctrl_configure_pins()
133 (0x1 << IOMUX_GET_CTIMER_BIT(pin_mux)); in pinctrl_configure_pins()
137 (0x1 << IOMUX_GET_CTIMER_BIT(pin_mux)); in pinctrl_configure_pins()
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| /Zephyr-latest/drivers/sensor/adi/adxl372/ |
| D | adxl372.h | 103 #define ADXL372_POWER_CTL_INSTANT_ON_TH_MODE(x) (((x) & 0x1) << 5)
105 #define ADXL372_POWER_CTL_FIL_SETTLE_MODE(x) (((x) & 0x1) << 4)
107 #define ADXL372_POWER_CTL_LPF_DIS_MODE(x) (((x) & 0x1) << 3)
109 #define ADXL372_POWER_CTL_HPF_DIS_MODE(x) (((x) & 0x1) << 2)
115 #define ADXL372_MEASURE_AUTOSLEEP_MODE(x) (((x) & 0x1) << 6)
119 #define ADXL372_MEASURE_LOW_NOISE_MODE(x) (((x) & 0x1) << 3)
129 #define ADXL372_TIMING_EXT_CLK_MODE(x) (((x) & 0x1) << 1)
131 #define ADXL372_TIMING_EXT_SYNC_MODE(x) (((x) & 0x1) << 0)
142 #define ADXL372_STATUS_1_DATA_RDY(x) (((x) >> 0) & 0x1)
143 #define ADXL372_STATUS_1_FIFO_RDY(x) (((x) >> 1) & 0x1)
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| /Zephyr-latest/soc/nxp/lpc/lpc11u6x/ |
| D | soc.h | 44 #define IOCON_PIO_HYS(x) (((x) & 0x1) << 5)
45 #define IOCON_PIO_HYS_MASK IOCON_PIO_HYS(0x1)
46 #define IOCON_PIO_INVERT(x) (((x) & 0x1) << 2)
47 #define IOCON_PIO_INVERT_MASK IOCON_PIO_INVERT(0x1)
48 #define IOCON_PIO_OD(x) (((x) & 0x1) << 10)
49 #define IOCON_PIO_OD_MASK IOCON_PIO_OD(0x1)
72 #define IOCON_PIO_ADMODE(x) (((x) & 0x1) << 7)
73 #define IOCON_PIO_ADMODE_MASK IOCON_PIO_ADMODE(0x1)
74 #define IOCON_PIO_FILTER(x) (((x) & 0x1) << 8)
75 #define IOCON_PIO_FILTER_MASK IOCON_PIO_FILTER(0x1)
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| /Zephyr-latest/drivers/ethernet/ |
| D | eth_lan865x_priv.h | 25 /* Memory Map Sector (MMS) 1 (0x1) */
26 #define LAN865x_MAC_NCR MMS_REG(0x1, 0x000)
29 #define LAN865x_MAC_NCFGR MMS_REG(0x1, 0x001)
32 #define LAN865x_MAC_HRB MMS_REG(0x1, 0x020)
33 #define LAN865x_MAC_HRT MMS_REG(0x1, 0x021)
34 #define LAN865x_MAC_SAB1 MMS_REG(0x1, 0x022)
35 #define LAN865x_MAC_SAB2 MMS_REG(0x1, 0x024)
36 #define LAN865x_MAC_SAT2 MMS_REG(0x1, 0x025)
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| /Zephyr-latest/boards/technexion/pico_pi/ |
| D | pico_pi-pinctrl.dtsi | 20 drive-strength = "x1";
32 drive-strength = "x1";
44 drive-strength = "x1";
56 drive-strength = "x1";
69 drive-strength = "x1";
82 drive-strength = "x1";
95 drive-strength = "x1";
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| /Zephyr-latest/dts/bindings/dma/ |
| D | gd,gd32-dma.yaml | 12 - 0x1: MEMORY to PERIPH
18 - 0x1: increment address between transfers
22 - 0x1: increase address between transfers
26 - 0x1: 16 bits
32 - 0x1: 16 bits
38 - 0x1: offset size is fixed to 4 (32-bit alignment)
42 - 0x1: medium
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| /Zephyr-latest/soc/renesas/ra/ra4m1/ |
| D | soc.c | 103 .RSVD1 = 0x1, .IWDTSTRT = 0x1, /* Disable independent watchdog timer
106 .IWDTRSTIRQS = 0x1, .RSVD2 = 0x1, .IWDTSTPCTL = 0x1, .RSVD3 = 0x3,
107 .WDTSTRT = 0x1, /* Stop watchdog timer following reset */
109 .WDTRSTIRQS = 0x1, .RSVD4 = 0x1, .WDTSTPCTL = 0x1, .RSVD5 = 0x1,
113 .LVDAS = 0x1, /* Disable voltage monitor 0 following reset */
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| /Zephyr-latest/tests/drivers/build_all/counter/boards/ |
| D | arty_a7_designstart_fpga_cortex_m1.overlay | 15 xlnx,gen0-assert = <0x1>;
16 xlnx,gen1-assert = <0x1>;
18 xlnx,trig0-assert = <0x1>;
19 xlnx,trig1-assert = <0x1>;
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