1 /*
2  * Copyright (c) 2020, Seagate
3  * Copyright 2022 NXP
4  *
5  * SPDX-License-Identifier: Apache-2.0
6  */
7 
8 /**
9  * @file
10  * @brief Board configuration macros for the nxp_lpc11u6x platform
11  *
12  * This header file is used to specify and describe board-level aspects for the
13  * 'nxp_lpc11u6x' platform.
14  */
15 
16 #ifndef _SOC__H_
17 #define _SOC__H_
18 
19 #ifndef _ASMLANGUAGE
20 #include <zephyr/sys/util.h>
21 
22 #include <cmsis_core_m_defaults.h>
23 
24 #endif /* !_ASMLANGUAGE */
25 
26 /**
27  * @brief Pin control register for standard digital I/O pins:
28  *
29  * [0:2]   function.
30  * [3:4]   mode.
31  * [5]     hysteresis.
32  * [6]     invert input.
33  * [7:9]   reserved.
34  * [10]    open-drain mode.
35  * [11:12] digital filter sample mode.
36  * [13:15] clock divisor.
37  * [16:31] reserved.
38  */
39 
40 #define IOCON_PIO_FUNC(x) (((x) & 0x7))
41 #define IOCON_PIO_FUNC_MASK IOCON_PIO_FUNC(0x7)
42 #define IOCON_PIO_MODE(x) (((x) & 0x3) << 3)
43 #define IOCON_PIO_MODE_MASK IOCON_PIO_MODE(0x3)
44 #define IOCON_PIO_HYS(x) (((x) & 0x1) << 5)
45 #define IOCON_PIO_HYS_MASK IOCON_PIO_HYS(0x1)
46 #define IOCON_PIO_INVERT(x) (((x) & 0x1) << 2)
47 #define IOCON_PIO_INVERT_MASK IOCON_PIO_INVERT(0x1)
48 #define IOCON_PIO_OD(x) (((x) & 0x1) << 10)
49 #define IOCON_PIO_OD_MASK IOCON_PIO_OD(0x1)
50 #define IOCON_PIO_SMODE(x) (((x) & 0x3) << 11)
51 #define IOCON_PIO_SMODE_MASK IOCON_PIO_SMODE(0x3)
52 #define IOCON_PIO_CLKDIV(x) (((x) & 0x7) << 13)
53 #define IOCON_PIO_CLKDIV_MASK IOCON_PIO_CLKDIV(0x7)
54 
55 
56 /**
57  * @brief Control registers for digital/analog I/O pins:
58  *
59  * [0:2]   function.
60  * [3:4]   mode.
61  * [5]     hysteresis.
62  * [6]     invert input.
63  * [7]     analog mode.
64  * [8]     input glitch filter.
65  * [9]     reserved.
66  * [10]    open-drain mode.
67  * [11:12] digital filter sample mode.
68  * [13:15] clock divisor.
69  * [16:31] reserved.
70  */
71 
72 #define IOCON_PIO_ADMODE(x) (((x) & 0x1) << 7)
73 #define IOCON_PIO_ADMODE_MASK IOCON_PIO_ADMODE(0x1)
74 #define IOCON_PIO_FILTER(x) (((x) & 0x1) << 8)
75 #define IOCON_PIO_FILTER_MASK IOCON_PIO_FILTER(0x1)
76 
77 
78 
79 /**
80  * @brief Control registers for open-drain I/O pins (I2C):
81  *
82  * [0:2]   function.
83  * [3:7]   reserved.
84  * [8:9]   I2C mode.
85  * [10]    reserved.
86  * [11:12] digital filter sample mode.
87  * [13:15] clock divisor.
88  * [16:31] reserved.
89  */
90 
91 #define IOCON_PIO_I2CMODE(x) (((x) & 0x3) << 8)
92 #define IOCON_PIO_I2CMODE_MASK IOCON_PIO_I2CMODE(0x3)
93 
94 #define IOCON_FUNC0 0
95 #define IOCON_FUNC1 1
96 #define IOCON_FUNC2 2
97 #define IOCON_FUNC3 3
98 #define IOCON_FUNC4 4
99 #define IOCON_FUNC5 5
100 
101 #endif /* _SOC__H_ */
102