Lines Matching full:x1
131 #define ACMP0_ACMPOUT_PA1 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x1)
139 #define ACMP0_ACMPOUT_PB0 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x0)
140 #define ACMP0_ACMPOUT_PB1 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x1)
141 #define ACMP0_ACMPOUT_PB2 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x2)
142 #define ACMP0_ACMPOUT_PB3 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x3)
143 #define ACMP0_ACMPOUT_PB4 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x4)
145 #define ACMP0_ACMPOUT_PC1 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x1)
153 #define ACMP0_ACMPOUT_PD1 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x1)
158 #define CMU_CLKOUT0_PC1 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x1)
166 #define CMU_CLKOUT0_PD1 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x1)
170 #define CMU_CLKOUT1_PC1 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x1)
178 #define CMU_CLKOUT1_PD1 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x1)
182 #define CMU_CLKOUT2_PA1 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x1)
190 #define CMU_CLKOUT2_PB0 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x0)
191 #define CMU_CLKOUT2_PB1 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x1)
192 #define CMU_CLKOUT2_PB2 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x2)
193 #define CMU_CLKOUT2_PB3 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x3)
194 #define CMU_CLKOUT2_PB4 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x4)
196 #define CMU_CLKIN0_PC1 SILABS_DBUS_CMU_CLKIN0(0x2, 0x1)
204 #define CMU_CLKIN0_PD1 SILABS_DBUS_CMU_CLKIN0(0x3, 0x1)
209 #define EUSART0_CS_PA1 SILABS_DBUS_EUSART0_CS(0x0, 0x1)
217 #define EUSART0_CS_PB0 SILABS_DBUS_EUSART0_CS(0x1, 0x0)
218 #define EUSART0_CS_PB1 SILABS_DBUS_EUSART0_CS(0x1, 0x1)
219 #define EUSART0_CS_PB2 SILABS_DBUS_EUSART0_CS(0x1, 0x2)
220 #define EUSART0_CS_PB3 SILABS_DBUS_EUSART0_CS(0x1, 0x3)
221 #define EUSART0_CS_PB4 SILABS_DBUS_EUSART0_CS(0x1, 0x4)
223 #define EUSART0_CS_PC1 SILABS_DBUS_EUSART0_CS(0x2, 0x1)
231 #define EUSART0_CS_PD1 SILABS_DBUS_EUSART0_CS(0x3, 0x1)
235 #define EUSART0_RTS_PA1 SILABS_DBUS_EUSART0_RTS(0x0, 0x1)
243 #define EUSART0_RTS_PB0 SILABS_DBUS_EUSART0_RTS(0x1, 0x0)
244 #define EUSART0_RTS_PB1 SILABS_DBUS_EUSART0_RTS(0x1, 0x1)
245 #define EUSART0_RTS_PB2 SILABS_DBUS_EUSART0_RTS(0x1, 0x2)
246 #define EUSART0_RTS_PB3 SILABS_DBUS_EUSART0_RTS(0x1, 0x3)
247 #define EUSART0_RTS_PB4 SILABS_DBUS_EUSART0_RTS(0x1, 0x4)
249 #define EUSART0_RTS_PC1 SILABS_DBUS_EUSART0_RTS(0x2, 0x1)
257 #define EUSART0_RTS_PD1 SILABS_DBUS_EUSART0_RTS(0x3, 0x1)
261 #define EUSART0_RX_PA1 SILABS_DBUS_EUSART0_RX(0x0, 0x1)
269 #define EUSART0_RX_PB0 SILABS_DBUS_EUSART0_RX(0x1, 0x0)
270 #define EUSART0_RX_PB1 SILABS_DBUS_EUSART0_RX(0x1, 0x1)
271 #define EUSART0_RX_PB2 SILABS_DBUS_EUSART0_RX(0x1, 0x2)
272 #define EUSART0_RX_PB3 SILABS_DBUS_EUSART0_RX(0x1, 0x3)
273 #define EUSART0_RX_PB4 SILABS_DBUS_EUSART0_RX(0x1, 0x4)
275 #define EUSART0_RX_PC1 SILABS_DBUS_EUSART0_RX(0x2, 0x1)
283 #define EUSART0_RX_PD1 SILABS_DBUS_EUSART0_RX(0x3, 0x1)
287 #define EUSART0_SCLK_PA1 SILABS_DBUS_EUSART0_SCLK(0x0, 0x1)
295 #define EUSART0_SCLK_PB0 SILABS_DBUS_EUSART0_SCLK(0x1, 0x0)
296 #define EUSART0_SCLK_PB1 SILABS_DBUS_EUSART0_SCLK(0x1, 0x1)
297 #define EUSART0_SCLK_PB2 SILABS_DBUS_EUSART0_SCLK(0x1, 0x2)
298 #define EUSART0_SCLK_PB3 SILABS_DBUS_EUSART0_SCLK(0x1, 0x3)
299 #define EUSART0_SCLK_PB4 SILABS_DBUS_EUSART0_SCLK(0x1, 0x4)
301 #define EUSART0_SCLK_PC1 SILABS_DBUS_EUSART0_SCLK(0x2, 0x1)
309 #define EUSART0_SCLK_PD1 SILABS_DBUS_EUSART0_SCLK(0x3, 0x1)
313 #define EUSART0_TX_PA1 SILABS_DBUS_EUSART0_TX(0x0, 0x1)
321 #define EUSART0_TX_PB0 SILABS_DBUS_EUSART0_TX(0x1, 0x0)
322 #define EUSART0_TX_PB1 SILABS_DBUS_EUSART0_TX(0x1, 0x1)
323 #define EUSART0_TX_PB2 SILABS_DBUS_EUSART0_TX(0x1, 0x2)
324 #define EUSART0_TX_PB3 SILABS_DBUS_EUSART0_TX(0x1, 0x3)
325 #define EUSART0_TX_PB4 SILABS_DBUS_EUSART0_TX(0x1, 0x4)
327 #define EUSART0_TX_PC1 SILABS_DBUS_EUSART0_TX(0x2, 0x1)
335 #define EUSART0_TX_PD1 SILABS_DBUS_EUSART0_TX(0x3, 0x1)
339 #define EUSART0_CTS_PA1 SILABS_DBUS_EUSART0_CTS(0x0, 0x1)
347 #define EUSART0_CTS_PB0 SILABS_DBUS_EUSART0_CTS(0x1, 0x0)
348 #define EUSART0_CTS_PB1 SILABS_DBUS_EUSART0_CTS(0x1, 0x1)
349 #define EUSART0_CTS_PB2 SILABS_DBUS_EUSART0_CTS(0x1, 0x2)
350 #define EUSART0_CTS_PB3 SILABS_DBUS_EUSART0_CTS(0x1, 0x3)
351 #define EUSART0_CTS_PB4 SILABS_DBUS_EUSART0_CTS(0x1, 0x4)
353 #define EUSART0_CTS_PC1 SILABS_DBUS_EUSART0_CTS(0x2, 0x1)
361 #define EUSART0_CTS_PD1 SILABS_DBUS_EUSART0_CTS(0x3, 0x1)
366 #define PTI_DCLK_PC1 SILABS_DBUS_PTI_DCLK(0x2, 0x1)
374 #define PTI_DCLK_PD1 SILABS_DBUS_PTI_DCLK(0x3, 0x1)
378 #define PTI_DFRAME_PC1 SILABS_DBUS_PTI_DFRAME(0x2, 0x1)
386 #define PTI_DFRAME_PD1 SILABS_DBUS_PTI_DFRAME(0x3, 0x1)
390 #define PTI_DOUT_PC1 SILABS_DBUS_PTI_DOUT(0x2, 0x1)
398 #define PTI_DOUT_PD1 SILABS_DBUS_PTI_DOUT(0x3, 0x1)
403 #define I2C0_SCL_PA1 SILABS_DBUS_I2C0_SCL(0x0, 0x1)
411 #define I2C0_SCL_PB0 SILABS_DBUS_I2C0_SCL(0x1, 0x0)
412 #define I2C0_SCL_PB1 SILABS_DBUS_I2C0_SCL(0x1, 0x1)
413 #define I2C0_SCL_PB2 SILABS_DBUS_I2C0_SCL(0x1, 0x2)
414 #define I2C0_SCL_PB3 SILABS_DBUS_I2C0_SCL(0x1, 0x3)
415 #define I2C0_SCL_PB4 SILABS_DBUS_I2C0_SCL(0x1, 0x4)
417 #define I2C0_SCL_PC1 SILABS_DBUS_I2C0_SCL(0x2, 0x1)
425 #define I2C0_SCL_PD1 SILABS_DBUS_I2C0_SCL(0x3, 0x1)
429 #define I2C0_SDA_PA1 SILABS_DBUS_I2C0_SDA(0x0, 0x1)
437 #define I2C0_SDA_PB0 SILABS_DBUS_I2C0_SDA(0x1, 0x0)
438 #define I2C0_SDA_PB1 SILABS_DBUS_I2C0_SDA(0x1, 0x1)
439 #define I2C0_SDA_PB2 SILABS_DBUS_I2C0_SDA(0x1, 0x2)
440 #define I2C0_SDA_PB3 SILABS_DBUS_I2C0_SDA(0x1, 0x3)
441 #define I2C0_SDA_PB4 SILABS_DBUS_I2C0_SDA(0x1, 0x4)
443 #define I2C0_SDA_PC1 SILABS_DBUS_I2C0_SDA(0x2, 0x1)
451 #define I2C0_SDA_PD1 SILABS_DBUS_I2C0_SDA(0x3, 0x1)
456 #define I2C1_SCL_PC1 SILABS_DBUS_I2C1_SCL(0x2, 0x1)
464 #define I2C1_SCL_PD1 SILABS_DBUS_I2C1_SCL(0x3, 0x1)
468 #define I2C1_SDA_PC1 SILABS_DBUS_I2C1_SDA(0x2, 0x1)
476 #define I2C1_SDA_PD1 SILABS_DBUS_I2C1_SDA(0x3, 0x1)
481 #define LETIMER0_OUT0_PA1 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x1)
489 #define LETIMER0_OUT0_PB0 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x0)
490 #define LETIMER0_OUT0_PB1 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x1)
491 #define LETIMER0_OUT0_PB2 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x2)
492 #define LETIMER0_OUT0_PB3 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x3)
493 #define LETIMER0_OUT0_PB4 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x4)
495 #define LETIMER0_OUT1_PA1 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x1)
503 #define LETIMER0_OUT1_PB0 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x0)
504 #define LETIMER0_OUT1_PB1 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x1)
505 #define LETIMER0_OUT1_PB2 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x2)
506 #define LETIMER0_OUT1_PB3 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x3)
507 #define LETIMER0_OUT1_PB4 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x4)
510 #define MODEM_ANT0_PA1 SILABS_DBUS_MODEM_ANT0(0x0, 0x1)
518 #define MODEM_ANT0_PB0 SILABS_DBUS_MODEM_ANT0(0x1, 0x0)
519 #define MODEM_ANT0_PB1 SILABS_DBUS_MODEM_ANT0(0x1, 0x1)
520 #define MODEM_ANT0_PB2 SILABS_DBUS_MODEM_ANT0(0x1, 0x2)
521 #define MODEM_ANT0_PB3 SILABS_DBUS_MODEM_ANT0(0x1, 0x3)
522 #define MODEM_ANT0_PB4 SILABS_DBUS_MODEM_ANT0(0x1, 0x4)
524 #define MODEM_ANT0_PC1 SILABS_DBUS_MODEM_ANT0(0x2, 0x1)
532 #define MODEM_ANT0_PD1 SILABS_DBUS_MODEM_ANT0(0x3, 0x1)
536 #define MODEM_ANT1_PA1 SILABS_DBUS_MODEM_ANT1(0x0, 0x1)
544 #define MODEM_ANT1_PB0 SILABS_DBUS_MODEM_ANT1(0x1, 0x0)
545 #define MODEM_ANT1_PB1 SILABS_DBUS_MODEM_ANT1(0x1, 0x1)
546 #define MODEM_ANT1_PB2 SILABS_DBUS_MODEM_ANT1(0x1, 0x2)
547 #define MODEM_ANT1_PB3 SILABS_DBUS_MODEM_ANT1(0x1, 0x3)
548 #define MODEM_ANT1_PB4 SILABS_DBUS_MODEM_ANT1(0x1, 0x4)
550 #define MODEM_ANT1_PC1 SILABS_DBUS_MODEM_ANT1(0x2, 0x1)
558 #define MODEM_ANT1_PD1 SILABS_DBUS_MODEM_ANT1(0x3, 0x1)
562 #define MODEM_ANTROLLOVER_PC1 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x1)
570 #define MODEM_ANTROLLOVER_PD1 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x1)
574 #define MODEM_ANTRR0_PC1 SILABS_DBUS_MODEM_ANTRR0(0x2, 0x1)
582 #define MODEM_ANTRR0_PD1 SILABS_DBUS_MODEM_ANTRR0(0x3, 0x1)
586 #define MODEM_ANTRR1_PC1 SILABS_DBUS_MODEM_ANTRR1(0x2, 0x1)
594 #define MODEM_ANTRR1_PD1 SILABS_DBUS_MODEM_ANTRR1(0x3, 0x1)
598 #define MODEM_ANTRR2_PC1 SILABS_DBUS_MODEM_ANTRR2(0x2, 0x1)
606 #define MODEM_ANTRR2_PD1 SILABS_DBUS_MODEM_ANTRR2(0x3, 0x1)
610 #define MODEM_ANTRR3_PC1 SILABS_DBUS_MODEM_ANTRR3(0x2, 0x1)
618 #define MODEM_ANTRR3_PD1 SILABS_DBUS_MODEM_ANTRR3(0x3, 0x1)
622 #define MODEM_ANTRR4_PC1 SILABS_DBUS_MODEM_ANTRR4(0x2, 0x1)
630 #define MODEM_ANTRR4_PD1 SILABS_DBUS_MODEM_ANTRR4(0x3, 0x1)
634 #define MODEM_ANTRR5_PC1 SILABS_DBUS_MODEM_ANTRR5(0x2, 0x1)
642 #define MODEM_ANTRR5_PD1 SILABS_DBUS_MODEM_ANTRR5(0x3, 0x1)
646 #define MODEM_ANTSWEN_PC1 SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x1)
654 #define MODEM_ANTSWEN_PD1 SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x1)
658 #define MODEM_ANTSWUS_PC1 SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x1)
666 #define MODEM_ANTSWUS_PD1 SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x1)
670 #define MODEM_ANTTRIG_PC1 SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x1)
678 #define MODEM_ANTTRIG_PD1 SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x1)
682 #define MODEM_ANTTRIGSTOP_PC1 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x1)
690 #define MODEM_ANTTRIGSTOP_PD1 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x1)
694 #define MODEM_DCLK_PA1 SILABS_DBUS_MODEM_DCLK(0x0, 0x1)
702 #define MODEM_DCLK_PB0 SILABS_DBUS_MODEM_DCLK(0x1, 0x0)
703 #define MODEM_DCLK_PB1 SILABS_DBUS_MODEM_DCLK(0x1, 0x1)
704 #define MODEM_DCLK_PB2 SILABS_DBUS_MODEM_DCLK(0x1, 0x2)
705 #define MODEM_DCLK_PB3 SILABS_DBUS_MODEM_DCLK(0x1, 0x3)
706 #define MODEM_DCLK_PB4 SILABS_DBUS_MODEM_DCLK(0x1, 0x4)
708 #define MODEM_DOUT_PA1 SILABS_DBUS_MODEM_DOUT(0x0, 0x1)
716 #define MODEM_DOUT_PB0 SILABS_DBUS_MODEM_DOUT(0x1, 0x0)
717 #define MODEM_DOUT_PB1 SILABS_DBUS_MODEM_DOUT(0x1, 0x1)
718 #define MODEM_DOUT_PB2 SILABS_DBUS_MODEM_DOUT(0x1, 0x2)
719 #define MODEM_DOUT_PB3 SILABS_DBUS_MODEM_DOUT(0x1, 0x3)
720 #define MODEM_DOUT_PB4 SILABS_DBUS_MODEM_DOUT(0x1, 0x4)
722 #define MODEM_DIN_PA1 SILABS_DBUS_MODEM_DIN(0x0, 0x1)
730 #define MODEM_DIN_PB0 SILABS_DBUS_MODEM_DIN(0x1, 0x0)
731 #define MODEM_DIN_PB1 SILABS_DBUS_MODEM_DIN(0x1, 0x1)
732 #define MODEM_DIN_PB2 SILABS_DBUS_MODEM_DIN(0x1, 0x2)
733 #define MODEM_DIN_PB3 SILABS_DBUS_MODEM_DIN(0x1, 0x3)
734 #define MODEM_DIN_PB4 SILABS_DBUS_MODEM_DIN(0x1, 0x4)
737 #define PDM_CLK_PA1 SILABS_DBUS_PDM_CLK(0x0, 0x1)
745 #define PDM_CLK_PB0 SILABS_DBUS_PDM_CLK(0x1, 0x0)
746 #define PDM_CLK_PB1 SILABS_DBUS_PDM_CLK(0x1, 0x1)
747 #define PDM_CLK_PB2 SILABS_DBUS_PDM_CLK(0x1, 0x2)
748 #define PDM_CLK_PB3 SILABS_DBUS_PDM_CLK(0x1, 0x3)
749 #define PDM_CLK_PB4 SILABS_DBUS_PDM_CLK(0x1, 0x4)
751 #define PDM_CLK_PC1 SILABS_DBUS_PDM_CLK(0x2, 0x1)
759 #define PDM_CLK_PD1 SILABS_DBUS_PDM_CLK(0x3, 0x1)
763 #define PDM_DAT0_PA1 SILABS_DBUS_PDM_DAT0(0x0, 0x1)
771 #define PDM_DAT0_PB0 SILABS_DBUS_PDM_DAT0(0x1, 0x0)
772 #define PDM_DAT0_PB1 SILABS_DBUS_PDM_DAT0(0x1, 0x1)
773 #define PDM_DAT0_PB2 SILABS_DBUS_PDM_DAT0(0x1, 0x2)
774 #define PDM_DAT0_PB3 SILABS_DBUS_PDM_DAT0(0x1, 0x3)
775 #define PDM_DAT0_PB4 SILABS_DBUS_PDM_DAT0(0x1, 0x4)
777 #define PDM_DAT0_PC1 SILABS_DBUS_PDM_DAT0(0x2, 0x1)
785 #define PDM_DAT0_PD1 SILABS_DBUS_PDM_DAT0(0x3, 0x1)
789 #define PDM_DAT1_PA1 SILABS_DBUS_PDM_DAT1(0x0, 0x1)
797 #define PDM_DAT1_PB0 SILABS_DBUS_PDM_DAT1(0x1, 0x0)
798 #define PDM_DAT1_PB1 SILABS_DBUS_PDM_DAT1(0x1, 0x1)
799 #define PDM_DAT1_PB2 SILABS_DBUS_PDM_DAT1(0x1, 0x2)
800 #define PDM_DAT1_PB3 SILABS_DBUS_PDM_DAT1(0x1, 0x3)
801 #define PDM_DAT1_PB4 SILABS_DBUS_PDM_DAT1(0x1, 0x4)
803 #define PDM_DAT1_PC1 SILABS_DBUS_PDM_DAT1(0x2, 0x1)
811 #define PDM_DAT1_PD1 SILABS_DBUS_PDM_DAT1(0x3, 0x1)
816 #define PRS0_ASYNCH0_PA1 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x1)
824 #define PRS0_ASYNCH0_PB0 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x0)
825 #define PRS0_ASYNCH0_PB1 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x1)
826 #define PRS0_ASYNCH0_PB2 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x2)
827 #define PRS0_ASYNCH0_PB3 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x3)
828 #define PRS0_ASYNCH0_PB4 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x4)
830 #define PRS0_ASYNCH1_PA1 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x1)
838 #define PRS0_ASYNCH1_PB0 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x0)
839 #define PRS0_ASYNCH1_PB1 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x1)
840 #define PRS0_ASYNCH1_PB2 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x2)
841 #define PRS0_ASYNCH1_PB3 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x3)
842 #define PRS0_ASYNCH1_PB4 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x4)
844 #define PRS0_ASYNCH2_PA1 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x1)
852 #define PRS0_ASYNCH2_PB0 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x0)
853 #define PRS0_ASYNCH2_PB1 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x1)
854 #define PRS0_ASYNCH2_PB2 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x2)
855 #define PRS0_ASYNCH2_PB3 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x3)
856 #define PRS0_ASYNCH2_PB4 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x4)
858 #define PRS0_ASYNCH3_PA1 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x1)
866 #define PRS0_ASYNCH3_PB0 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x0)
867 #define PRS0_ASYNCH3_PB1 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x1)
868 #define PRS0_ASYNCH3_PB2 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x2)
869 #define PRS0_ASYNCH3_PB3 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x3)
870 #define PRS0_ASYNCH3_PB4 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x4)
872 #define PRS0_ASYNCH4_PA1 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x1)
880 #define PRS0_ASYNCH4_PB0 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x0)
881 #define PRS0_ASYNCH4_PB1 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x1)
882 #define PRS0_ASYNCH4_PB2 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x2)
883 #define PRS0_ASYNCH4_PB3 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x3)
884 #define PRS0_ASYNCH4_PB4 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x4)
886 #define PRS0_ASYNCH5_PA1 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x1)
894 #define PRS0_ASYNCH5_PB0 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x0)
895 #define PRS0_ASYNCH5_PB1 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x1)
896 #define PRS0_ASYNCH5_PB2 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x2)
897 #define PRS0_ASYNCH5_PB3 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x3)
898 #define PRS0_ASYNCH5_PB4 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x4)
900 #define PRS0_ASYNCH6_PC1 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x1)
908 #define PRS0_ASYNCH6_PD1 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x1)
912 #define PRS0_ASYNCH7_PC1 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x1)
920 #define PRS0_ASYNCH7_PD1 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x1)
924 #define PRS0_ASYNCH8_PC1 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x1)
932 #define PRS0_ASYNCH8_PD1 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x1)
936 #define PRS0_ASYNCH9_PC1 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x1)
944 #define PRS0_ASYNCH9_PD1 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x1)
948 #define PRS0_ASYNCH10_PC1 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x1)
956 #define PRS0_ASYNCH10_PD1 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x1)
960 #define PRS0_ASYNCH11_PC1 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x1)
968 #define PRS0_ASYNCH11_PD1 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x1)
972 #define PRS0_SYNCH0_PA1 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x1)
980 #define PRS0_SYNCH0_PB0 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x0)
981 #define PRS0_SYNCH0_PB1 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x1)
982 #define PRS0_SYNCH0_PB2 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x2)
983 #define PRS0_SYNCH0_PB3 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x3)
984 #define PRS0_SYNCH0_PB4 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x4)
986 #define PRS0_SYNCH0_PC1 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x1)
994 #define PRS0_SYNCH0_PD1 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x1)
998 #define PRS0_SYNCH1_PA1 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x1)
1006 #define PRS0_SYNCH1_PB0 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x0)
1007 #define PRS0_SYNCH1_PB1 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x1)
1008 #define PRS0_SYNCH1_PB2 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x2)
1009 #define PRS0_SYNCH1_PB3 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x3)
1010 #define PRS0_SYNCH1_PB4 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x4)
1012 #define PRS0_SYNCH1_PC1 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x1)
1020 #define PRS0_SYNCH1_PD1 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x1)
1024 #define PRS0_SYNCH2_PA1 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x1)
1032 #define PRS0_SYNCH2_PB0 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x0)
1033 #define PRS0_SYNCH2_PB1 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x1)
1034 #define PRS0_SYNCH2_PB2 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x2)
1035 #define PRS0_SYNCH2_PB3 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x3)
1036 #define PRS0_SYNCH2_PB4 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x4)
1038 #define PRS0_SYNCH2_PC1 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x1)
1046 #define PRS0_SYNCH2_PD1 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x1)
1050 #define PRS0_SYNCH3_PA1 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x1)
1058 #define PRS0_SYNCH3_PB0 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x0)
1059 #define PRS0_SYNCH3_PB1 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x1)
1060 #define PRS0_SYNCH3_PB2 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x2)
1061 #define PRS0_SYNCH3_PB3 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x3)
1062 #define PRS0_SYNCH3_PB4 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x4)
1064 #define PRS0_SYNCH3_PC1 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x1)
1072 #define PRS0_SYNCH3_PD1 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x1)
1077 #define TIMER0_CC0_PA1 SILABS_DBUS_TIMER0_CC0(0x0, 0x1)
1085 #define TIMER0_CC0_PB0 SILABS_DBUS_TIMER0_CC0(0x1, 0x0)
1086 #define TIMER0_CC0_PB1 SILABS_DBUS_TIMER0_CC0(0x1, 0x1)
1087 #define TIMER0_CC0_PB2 SILABS_DBUS_TIMER0_CC0(0x1, 0x2)
1088 #define TIMER0_CC0_PB3 SILABS_DBUS_TIMER0_CC0(0x1, 0x3)
1089 #define TIMER0_CC0_PB4 SILABS_DBUS_TIMER0_CC0(0x1, 0x4)
1091 #define TIMER0_CC0_PC1 SILABS_DBUS_TIMER0_CC0(0x2, 0x1)
1099 #define TIMER0_CC0_PD1 SILABS_DBUS_TIMER0_CC0(0x3, 0x1)
1103 #define TIMER0_CC1_PA1 SILABS_DBUS_TIMER0_CC1(0x0, 0x1)
1111 #define TIMER0_CC1_PB0 SILABS_DBUS_TIMER0_CC1(0x1, 0x0)
1112 #define TIMER0_CC1_PB1 SILABS_DBUS_TIMER0_CC1(0x1, 0x1)
1113 #define TIMER0_CC1_PB2 SILABS_DBUS_TIMER0_CC1(0x1, 0x2)
1114 #define TIMER0_CC1_PB3 SILABS_DBUS_TIMER0_CC1(0x1, 0x3)
1115 #define TIMER0_CC1_PB4 SILABS_DBUS_TIMER0_CC1(0x1, 0x4)
1117 #define TIMER0_CC1_PC1 SILABS_DBUS_TIMER0_CC1(0x2, 0x1)
1125 #define TIMER0_CC1_PD1 SILABS_DBUS_TIMER0_CC1(0x3, 0x1)
1129 #define TIMER0_CC2_PA1 SILABS_DBUS_TIMER0_CC2(0x0, 0x1)
1137 #define TIMER0_CC2_PB0 SILABS_DBUS_TIMER0_CC2(0x1, 0x0)
1138 #define TIMER0_CC2_PB1 SILABS_DBUS_TIMER0_CC2(0x1, 0x1)
1139 #define TIMER0_CC2_PB2 SILABS_DBUS_TIMER0_CC2(0x1, 0x2)
1140 #define TIMER0_CC2_PB3 SILABS_DBUS_TIMER0_CC2(0x1, 0x3)
1141 #define TIMER0_CC2_PB4 SILABS_DBUS_TIMER0_CC2(0x1, 0x4)
1143 #define TIMER0_CC2_PC1 SILABS_DBUS_TIMER0_CC2(0x2, 0x1)
1151 #define TIMER0_CC2_PD1 SILABS_DBUS_TIMER0_CC2(0x3, 0x1)
1155 #define TIMER0_CDTI0_PA1 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x1)
1163 #define TIMER0_CDTI0_PB0 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x0)
1164 #define TIMER0_CDTI0_PB1 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x1)
1165 #define TIMER0_CDTI0_PB2 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x2)
1166 #define TIMER0_CDTI0_PB3 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x3)
1167 #define TIMER0_CDTI0_PB4 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x4)
1169 #define TIMER0_CDTI0_PC1 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x1)
1177 #define TIMER0_CDTI0_PD1 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x1)
1181 #define TIMER0_CDTI1_PA1 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x1)
1189 #define TIMER0_CDTI1_PB0 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x0)
1190 #define TIMER0_CDTI1_PB1 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x1)
1191 #define TIMER0_CDTI1_PB2 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x2)
1192 #define TIMER0_CDTI1_PB3 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x3)
1193 #define TIMER0_CDTI1_PB4 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x4)
1195 #define TIMER0_CDTI1_PC1 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x1)
1203 #define TIMER0_CDTI1_PD1 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x1)
1207 #define TIMER0_CDTI2_PA1 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x1)
1215 #define TIMER0_CDTI2_PB0 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x0)
1216 #define TIMER0_CDTI2_PB1 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x1)
1217 #define TIMER0_CDTI2_PB2 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x2)
1218 #define TIMER0_CDTI2_PB3 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x3)
1219 #define TIMER0_CDTI2_PB4 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x4)
1221 #define TIMER0_CDTI2_PC1 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x1)
1229 #define TIMER0_CDTI2_PD1 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x1)
1234 #define TIMER1_CC0_PA1 SILABS_DBUS_TIMER1_CC0(0x0, 0x1)
1242 #define TIMER1_CC0_PB0 SILABS_DBUS_TIMER1_CC0(0x1, 0x0)
1243 #define TIMER1_CC0_PB1 SILABS_DBUS_TIMER1_CC0(0x1, 0x1)
1244 #define TIMER1_CC0_PB2 SILABS_DBUS_TIMER1_CC0(0x1, 0x2)
1245 #define TIMER1_CC0_PB3 SILABS_DBUS_TIMER1_CC0(0x1, 0x3)
1246 #define TIMER1_CC0_PB4 SILABS_DBUS_TIMER1_CC0(0x1, 0x4)
1248 #define TIMER1_CC0_PC1 SILABS_DBUS_TIMER1_CC0(0x2, 0x1)
1256 #define TIMER1_CC0_PD1 SILABS_DBUS_TIMER1_CC0(0x3, 0x1)
1260 #define TIMER1_CC1_PA1 SILABS_DBUS_TIMER1_CC1(0x0, 0x1)
1268 #define TIMER1_CC1_PB0 SILABS_DBUS_TIMER1_CC1(0x1, 0x0)
1269 #define TIMER1_CC1_PB1 SILABS_DBUS_TIMER1_CC1(0x1, 0x1)
1270 #define TIMER1_CC1_PB2 SILABS_DBUS_TIMER1_CC1(0x1, 0x2)
1271 #define TIMER1_CC1_PB3 SILABS_DBUS_TIMER1_CC1(0x1, 0x3)
1272 #define TIMER1_CC1_PB4 SILABS_DBUS_TIMER1_CC1(0x1, 0x4)
1274 #define TIMER1_CC1_PC1 SILABS_DBUS_TIMER1_CC1(0x2, 0x1)
1282 #define TIMER1_CC1_PD1 SILABS_DBUS_TIMER1_CC1(0x3, 0x1)
1286 #define TIMER1_CC2_PA1 SILABS_DBUS_TIMER1_CC2(0x0, 0x1)
1294 #define TIMER1_CC2_PB0 SILABS_DBUS_TIMER1_CC2(0x1, 0x0)
1295 #define TIMER1_CC2_PB1 SILABS_DBUS_TIMER1_CC2(0x1, 0x1)
1296 #define TIMER1_CC2_PB2 SILABS_DBUS_TIMER1_CC2(0x1, 0x2)
1297 #define TIMER1_CC2_PB3 SILABS_DBUS_TIMER1_CC2(0x1, 0x3)
1298 #define TIMER1_CC2_PB4 SILABS_DBUS_TIMER1_CC2(0x1, 0x4)
1300 #define TIMER1_CC2_PC1 SILABS_DBUS_TIMER1_CC2(0x2, 0x1)
1308 #define TIMER1_CC2_PD1 SILABS_DBUS_TIMER1_CC2(0x3, 0x1)
1312 #define TIMER1_CDTI0_PA1 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x1)
1320 #define TIMER1_CDTI0_PB0 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x0)
1321 #define TIMER1_CDTI0_PB1 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x1)
1322 #define TIMER1_CDTI0_PB2 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x2)
1323 #define TIMER1_CDTI0_PB3 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x3)
1324 #define TIMER1_CDTI0_PB4 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x4)
1326 #define TIMER1_CDTI0_PC1 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x1)
1334 #define TIMER1_CDTI0_PD1 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x1)
1338 #define TIMER1_CDTI1_PA1 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x1)
1346 #define TIMER1_CDTI1_PB0 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x0)
1347 #define TIMER1_CDTI1_PB1 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x1)
1348 #define TIMER1_CDTI1_PB2 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x2)
1349 #define TIMER1_CDTI1_PB3 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x3)
1350 #define TIMER1_CDTI1_PB4 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x4)
1352 #define TIMER1_CDTI1_PC1 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x1)
1360 #define TIMER1_CDTI1_PD1 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x1)
1364 #define TIMER1_CDTI2_PA1 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x1)
1372 #define TIMER1_CDTI2_PB0 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x0)
1373 #define TIMER1_CDTI2_PB1 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x1)
1374 #define TIMER1_CDTI2_PB2 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x2)
1375 #define TIMER1_CDTI2_PB3 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x3)
1376 #define TIMER1_CDTI2_PB4 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x4)
1378 #define TIMER1_CDTI2_PC1 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x1)
1386 #define TIMER1_CDTI2_PD1 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x1)
1391 #define TIMER2_CC0_PA1 SILABS_DBUS_TIMER2_CC0(0x0, 0x1)
1399 #define TIMER2_CC0_PB0 SILABS_DBUS_TIMER2_CC0(0x1, 0x0)
1400 #define TIMER2_CC0_PB1 SILABS_DBUS_TIMER2_CC0(0x1, 0x1)
1401 #define TIMER2_CC0_PB2 SILABS_DBUS_TIMER2_CC0(0x1, 0x2)
1402 #define TIMER2_CC0_PB3 SILABS_DBUS_TIMER2_CC0(0x1, 0x3)
1403 #define TIMER2_CC0_PB4 SILABS_DBUS_TIMER2_CC0(0x1, 0x4)
1405 #define TIMER2_CC1_PA1 SILABS_DBUS_TIMER2_CC1(0x0, 0x1)
1413 #define TIMER2_CC1_PB0 SILABS_DBUS_TIMER2_CC1(0x1, 0x0)
1414 #define TIMER2_CC1_PB1 SILABS_DBUS_TIMER2_CC1(0x1, 0x1)
1415 #define TIMER2_CC1_PB2 SILABS_DBUS_TIMER2_CC1(0x1, 0x2)
1416 #define TIMER2_CC1_PB3 SILABS_DBUS_TIMER2_CC1(0x1, 0x3)
1417 #define TIMER2_CC1_PB4 SILABS_DBUS_TIMER2_CC1(0x1, 0x4)
1419 #define TIMER2_CC2_PA1 SILABS_DBUS_TIMER2_CC2(0x0, 0x1)
1427 #define TIMER2_CC2_PB0 SILABS_DBUS_TIMER2_CC2(0x1, 0x0)
1428 #define TIMER2_CC2_PB1 SILABS_DBUS_TIMER2_CC2(0x1, 0x1)
1429 #define TIMER2_CC2_PB2 SILABS_DBUS_TIMER2_CC2(0x1, 0x2)
1430 #define TIMER2_CC2_PB3 SILABS_DBUS_TIMER2_CC2(0x1, 0x3)
1431 #define TIMER2_CC2_PB4 SILABS_DBUS_TIMER2_CC2(0x1, 0x4)
1433 #define TIMER2_CDTI0_PA1 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x1)
1441 #define TIMER2_CDTI0_PB0 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x0)
1442 #define TIMER2_CDTI0_PB1 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x1)
1443 #define TIMER2_CDTI0_PB2 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x2)
1444 #define TIMER2_CDTI0_PB3 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x3)
1445 #define TIMER2_CDTI0_PB4 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x4)
1447 #define TIMER2_CDTI1_PA1 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x1)
1455 #define TIMER2_CDTI1_PB0 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x0)
1456 #define TIMER2_CDTI1_PB1 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x1)
1457 #define TIMER2_CDTI1_PB2 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x2)
1458 #define TIMER2_CDTI1_PB3 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x3)
1459 #define TIMER2_CDTI1_PB4 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x4)
1461 #define TIMER2_CDTI2_PA1 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x1)
1469 #define TIMER2_CDTI2_PB0 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x0)
1470 #define TIMER2_CDTI2_PB1 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x1)
1471 #define TIMER2_CDTI2_PB2 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x2)
1472 #define TIMER2_CDTI2_PB3 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x3)
1473 #define TIMER2_CDTI2_PB4 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x4)
1476 #define TIMER3_CC0_PC1 SILABS_DBUS_TIMER3_CC0(0x2, 0x1)
1484 #define TIMER3_CC0_PD1 SILABS_DBUS_TIMER3_CC0(0x3, 0x1)
1488 #define TIMER3_CC1_PC1 SILABS_DBUS_TIMER3_CC1(0x2, 0x1)
1496 #define TIMER3_CC1_PD1 SILABS_DBUS_TIMER3_CC1(0x3, 0x1)
1500 #define TIMER3_CC2_PC1 SILABS_DBUS_TIMER3_CC2(0x2, 0x1)
1508 #define TIMER3_CC2_PD1 SILABS_DBUS_TIMER3_CC2(0x3, 0x1)
1512 #define TIMER3_CDTI0_PC1 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x1)
1520 #define TIMER3_CDTI0_PD1 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x1)
1524 #define TIMER3_CDTI1_PC1 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x1)
1532 #define TIMER3_CDTI1_PD1 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x1)
1536 #define TIMER3_CDTI2_PC1 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x1)
1544 #define TIMER3_CDTI2_PD1 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x1)
1549 #define TIMER4_CC0_PA1 SILABS_DBUS_TIMER4_CC0(0x0, 0x1)
1557 #define TIMER4_CC0_PB0 SILABS_DBUS_TIMER4_CC0(0x1, 0x0)
1558 #define TIMER4_CC0_PB1 SILABS_DBUS_TIMER4_CC0(0x1, 0x1)
1559 #define TIMER4_CC0_PB2 SILABS_DBUS_TIMER4_CC0(0x1, 0x2)
1560 #define TIMER4_CC0_PB3 SILABS_DBUS_TIMER4_CC0(0x1, 0x3)
1561 #define TIMER4_CC0_PB4 SILABS_DBUS_TIMER4_CC0(0x1, 0x4)
1563 #define TIMER4_CC1_PA1 SILABS_DBUS_TIMER4_CC1(0x0, 0x1)
1571 #define TIMER4_CC1_PB0 SILABS_DBUS_TIMER4_CC1(0x1, 0x0)
1572 #define TIMER4_CC1_PB1 SILABS_DBUS_TIMER4_CC1(0x1, 0x1)
1573 #define TIMER4_CC1_PB2 SILABS_DBUS_TIMER4_CC1(0x1, 0x2)
1574 #define TIMER4_CC1_PB3 SILABS_DBUS_TIMER4_CC1(0x1, 0x3)
1575 #define TIMER4_CC1_PB4 SILABS_DBUS_TIMER4_CC1(0x1, 0x4)
1577 #define TIMER4_CC2_PA1 SILABS_DBUS_TIMER4_CC2(0x0, 0x1)
1585 #define TIMER4_CC2_PB0 SILABS_DBUS_TIMER4_CC2(0x1, 0x0)
1586 #define TIMER4_CC2_PB1 SILABS_DBUS_TIMER4_CC2(0x1, 0x1)
1587 #define TIMER4_CC2_PB2 SILABS_DBUS_TIMER4_CC2(0x1, 0x2)
1588 #define TIMER4_CC2_PB3 SILABS_DBUS_TIMER4_CC2(0x1, 0x3)
1589 #define TIMER4_CC2_PB4 SILABS_DBUS_TIMER4_CC2(0x1, 0x4)
1591 #define TIMER4_CDTI0_PA1 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x1)
1599 #define TIMER4_CDTI0_PB0 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x0)
1600 #define TIMER4_CDTI0_PB1 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x1)
1601 #define TIMER4_CDTI0_PB2 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x2)
1602 #define TIMER4_CDTI0_PB3 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x3)
1603 #define TIMER4_CDTI0_PB4 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x4)
1605 #define TIMER4_CDTI1_PA1 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x1)
1613 #define TIMER4_CDTI1_PB0 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x0)
1614 #define TIMER4_CDTI1_PB1 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x1)
1615 #define TIMER4_CDTI1_PB2 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x2)
1616 #define TIMER4_CDTI1_PB3 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x3)
1617 #define TIMER4_CDTI1_PB4 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x4)
1619 #define TIMER4_CDTI2_PA1 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x1)
1627 #define TIMER4_CDTI2_PB0 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x0)
1628 #define TIMER4_CDTI2_PB1 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x1)
1629 #define TIMER4_CDTI2_PB2 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x2)
1630 #define TIMER4_CDTI2_PB3 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x3)
1631 #define TIMER4_CDTI2_PB4 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x4)
1634 #define USART0_CS_PA1 SILABS_DBUS_USART0_CS(0x0, 0x1)
1642 #define USART0_CS_PB0 SILABS_DBUS_USART0_CS(0x1, 0x0)
1643 #define USART0_CS_PB1 SILABS_DBUS_USART0_CS(0x1, 0x1)
1644 #define USART0_CS_PB2 SILABS_DBUS_USART0_CS(0x1, 0x2)
1645 #define USART0_CS_PB3 SILABS_DBUS_USART0_CS(0x1, 0x3)
1646 #define USART0_CS_PB4 SILABS_DBUS_USART0_CS(0x1, 0x4)
1648 #define USART0_CS_PC1 SILABS_DBUS_USART0_CS(0x2, 0x1)
1656 #define USART0_CS_PD1 SILABS_DBUS_USART0_CS(0x3, 0x1)
1660 #define USART0_RTS_PA1 SILABS_DBUS_USART0_RTS(0x0, 0x1)
1668 #define USART0_RTS_PB0 SILABS_DBUS_USART0_RTS(0x1, 0x0)
1669 #define USART0_RTS_PB1 SILABS_DBUS_USART0_RTS(0x1, 0x1)
1670 #define USART0_RTS_PB2 SILABS_DBUS_USART0_RTS(0x1, 0x2)
1671 #define USART0_RTS_PB3 SILABS_DBUS_USART0_RTS(0x1, 0x3)
1672 #define USART0_RTS_PB4 SILABS_DBUS_USART0_RTS(0x1, 0x4)
1674 #define USART0_RTS_PC1 SILABS_DBUS_USART0_RTS(0x2, 0x1)
1682 #define USART0_RTS_PD1 SILABS_DBUS_USART0_RTS(0x3, 0x1)
1686 #define USART0_RX_PA1 SILABS_DBUS_USART0_RX(0x0, 0x1)
1694 #define USART0_RX_PB0 SILABS_DBUS_USART0_RX(0x1, 0x0)
1695 #define USART0_RX_PB1 SILABS_DBUS_USART0_RX(0x1, 0x1)
1696 #define USART0_RX_PB2 SILABS_DBUS_USART0_RX(0x1, 0x2)
1697 #define USART0_RX_PB3 SILABS_DBUS_USART0_RX(0x1, 0x3)
1698 #define USART0_RX_PB4 SILABS_DBUS_USART0_RX(0x1, 0x4)
1700 #define USART0_RX_PC1 SILABS_DBUS_USART0_RX(0x2, 0x1)
1708 #define USART0_RX_PD1 SILABS_DBUS_USART0_RX(0x3, 0x1)
1712 #define USART0_CLK_PA1 SILABS_DBUS_USART0_CLK(0x0, 0x1)
1720 #define USART0_CLK_PB0 SILABS_DBUS_USART0_CLK(0x1, 0x0)
1721 #define USART0_CLK_PB1 SILABS_DBUS_USART0_CLK(0x1, 0x1)
1722 #define USART0_CLK_PB2 SILABS_DBUS_USART0_CLK(0x1, 0x2)
1723 #define USART0_CLK_PB3 SILABS_DBUS_USART0_CLK(0x1, 0x3)
1724 #define USART0_CLK_PB4 SILABS_DBUS_USART0_CLK(0x1, 0x4)
1726 #define USART0_CLK_PC1 SILABS_DBUS_USART0_CLK(0x2, 0x1)
1734 #define USART0_CLK_PD1 SILABS_DBUS_USART0_CLK(0x3, 0x1)
1738 #define USART0_TX_PA1 SILABS_DBUS_USART0_TX(0x0, 0x1)
1746 #define USART0_TX_PB0 SILABS_DBUS_USART0_TX(0x1, 0x0)
1747 #define USART0_TX_PB1 SILABS_DBUS_USART0_TX(0x1, 0x1)
1748 #define USART0_TX_PB2 SILABS_DBUS_USART0_TX(0x1, 0x2)
1749 #define USART0_TX_PB3 SILABS_DBUS_USART0_TX(0x1, 0x3)
1750 #define USART0_TX_PB4 SILABS_DBUS_USART0_TX(0x1, 0x4)
1752 #define USART0_TX_PC1 SILABS_DBUS_USART0_TX(0x2, 0x1)
1760 #define USART0_TX_PD1 SILABS_DBUS_USART0_TX(0x3, 0x1)
1764 #define USART0_CTS_PA1 SILABS_DBUS_USART0_CTS(0x0, 0x1)
1772 #define USART0_CTS_PB0 SILABS_DBUS_USART0_CTS(0x1, 0x0)
1773 #define USART0_CTS_PB1 SILABS_DBUS_USART0_CTS(0x1, 0x1)
1774 #define USART0_CTS_PB2 SILABS_DBUS_USART0_CTS(0x1, 0x2)
1775 #define USART0_CTS_PB3 SILABS_DBUS_USART0_CTS(0x1, 0x3)
1776 #define USART0_CTS_PB4 SILABS_DBUS_USART0_CTS(0x1, 0x4)
1778 #define USART0_CTS_PC1 SILABS_DBUS_USART0_CTS(0x2, 0x1)
1786 #define USART0_CTS_PD1 SILABS_DBUS_USART0_CTS(0x3, 0x1)
1791 #define USART1_CS_PA1 SILABS_DBUS_USART1_CS(0x0, 0x1)
1799 #define USART1_CS_PB0 SILABS_DBUS_USART1_CS(0x1, 0x0)
1800 #define USART1_CS_PB1 SILABS_DBUS_USART1_CS(0x1, 0x1)
1801 #define USART1_CS_PB2 SILABS_DBUS_USART1_CS(0x1, 0x2)
1802 #define USART1_CS_PB3 SILABS_DBUS_USART1_CS(0x1, 0x3)
1803 #define USART1_CS_PB4 SILABS_DBUS_USART1_CS(0x1, 0x4)
1805 #define USART1_RTS_PA1 SILABS_DBUS_USART1_RTS(0x0, 0x1)
1813 #define USART1_RTS_PB0 SILABS_DBUS_USART1_RTS(0x1, 0x0)
1814 #define USART1_RTS_PB1 SILABS_DBUS_USART1_RTS(0x1, 0x1)
1815 #define USART1_RTS_PB2 SILABS_DBUS_USART1_RTS(0x1, 0x2)
1816 #define USART1_RTS_PB3 SILABS_DBUS_USART1_RTS(0x1, 0x3)
1817 #define USART1_RTS_PB4 SILABS_DBUS_USART1_RTS(0x1, 0x4)
1819 #define USART1_RX_PA1 SILABS_DBUS_USART1_RX(0x0, 0x1)
1827 #define USART1_RX_PB0 SILABS_DBUS_USART1_RX(0x1, 0x0)
1828 #define USART1_RX_PB1 SILABS_DBUS_USART1_RX(0x1, 0x1)
1829 #define USART1_RX_PB2 SILABS_DBUS_USART1_RX(0x1, 0x2)
1830 #define USART1_RX_PB3 SILABS_DBUS_USART1_RX(0x1, 0x3)
1831 #define USART1_RX_PB4 SILABS_DBUS_USART1_RX(0x1, 0x4)
1833 #define USART1_CLK_PA1 SILABS_DBUS_USART1_CLK(0x0, 0x1)
1841 #define USART1_CLK_PB0 SILABS_DBUS_USART1_CLK(0x1, 0x0)
1842 #define USART1_CLK_PB1 SILABS_DBUS_USART1_CLK(0x1, 0x1)
1843 #define USART1_CLK_PB2 SILABS_DBUS_USART1_CLK(0x1, 0x2)
1844 #define USART1_CLK_PB3 SILABS_DBUS_USART1_CLK(0x1, 0x3)
1845 #define USART1_CLK_PB4 SILABS_DBUS_USART1_CLK(0x1, 0x4)
1847 #define USART1_TX_PA1 SILABS_DBUS_USART1_TX(0x0, 0x1)
1855 #define USART1_TX_PB0 SILABS_DBUS_USART1_TX(0x1, 0x0)
1856 #define USART1_TX_PB1 SILABS_DBUS_USART1_TX(0x1, 0x1)
1857 #define USART1_TX_PB2 SILABS_DBUS_USART1_TX(0x1, 0x2)
1858 #define USART1_TX_PB3 SILABS_DBUS_USART1_TX(0x1, 0x3)
1859 #define USART1_TX_PB4 SILABS_DBUS_USART1_TX(0x1, 0x4)
1861 #define USART1_CTS_PA1 SILABS_DBUS_USART1_CTS(0x0, 0x1)
1869 #define USART1_CTS_PB0 SILABS_DBUS_USART1_CTS(0x1, 0x0)
1870 #define USART1_CTS_PB1 SILABS_DBUS_USART1_CTS(0x1, 0x1)
1871 #define USART1_CTS_PB2 SILABS_DBUS_USART1_CTS(0x1, 0x2)
1872 #define USART1_CTS_PB3 SILABS_DBUS_USART1_CTS(0x1, 0x3)
1873 #define USART1_CTS_PB4 SILABS_DBUS_USART1_CTS(0x1, 0x4)