Lines Matching full:x1
64 mask = (0x1 << (gpio_idx & 0x1F)); in configure_pin_props()
84 ~(0x1 << IOMUX_GET_CTIMER_CLR_OFFSET(gpio_setting)); in select_gpio_mode()
86 ~(0x1 << IOMUX_GET_CTIMER_CLR_OFFSET(gpio_setting)); in select_gpio_mode()
91 ~(0x1 << IOMUX_GET_SCTIMER_IN_CLR_OFFSET(gpio_setting)); in select_gpio_mode()
95 ~(0x1 << (IOMUX_GET_SCTIMER_OUT_CLR_OFFSET(gpio_setting) + 16)); in select_gpio_mode()
98 mci_iomux->S_GPIO &= ~(0x1 << (gpio_idx - 32)); in select_gpio_mode()
125 (0x1 << IOMUX_GET_FLEXCOMM_BIT(pin_mux)); in pinctrl_configure_pins()
129 (0x1 << IOMUX_GET_FSEL_BIT(pin_mux)); in pinctrl_configure_pins()
133 (0x1 << IOMUX_GET_CTIMER_BIT(pin_mux)); in pinctrl_configure_pins()
137 (0x1 << IOMUX_GET_CTIMER_BIT(pin_mux)); in pinctrl_configure_pins()
141 (0x1 << IOMUX_GET_SCTIMER_BIT(pin_mux)); in pinctrl_configure_pins()
145 (0x1 << (IOMUX_GET_SCTIMER_BIT(pin_mux) + 16)); in pinctrl_configure_pins()
148 mci_iomux->S_GPIO |= (0x1 << (gpio_idx - 32)); in pinctrl_configure_pins()
152 mci_iomux->GPIO_GRP1 |= (0x1 << (gpio_idx - 32)); in pinctrl_configure_pins()
154 mci_iomux->GPIO_GRP0 |= (0x1 << gpio_idx); in pinctrl_configure_pins()
171 *iomux_en_reg |= (0x1 << (gpio_idx & 0x1F)); in pinctrl_configure_pins()