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/Zephyr-latest/dts/bindings/mspi/
Dambiq,mspi-device.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "ambiq,mspi-device"
8 include: [mspi-device.yaml, "jedec,jesd216.yaml"]
11 mspi-io-mode:
14 mspi-data-rate:
17 mspi-hardware-ce-num:
25 rx-dummy:
28 tx-dummy:
31 read-command:
34 write-command:
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/Zephyr-latest/drivers/can/
Dcan_mcux_flexcan.c4 * SPDX-License-Identifier: Apache-2.0
47 #define MCUX_FLEXCAN_MAX_TX (MCUX_FLEXCAN_MAX_MB - MCUX_FLEXCAN_MAX_RX)
60 #define TX_MBIDX_TO_ALLOC_IDX(x) (x - MCUX_FLEXCAN_MAX_RX)
116 struct can_timing timing; member
124 const struct mcux_flexcan_config *config = dev->config; in mcux_flexcan_get_core_clock() local
126 return clock_control_get_rate(config->clock_dev, config->clock_subsys, rate); in mcux_flexcan_get_core_clock()
137 const struct can_timing *timing) in mcux_flexcan_set_timing() argument
139 struct mcux_flexcan_data *data = dev->data; in mcux_flexcan_set_timing()
141 if (!timing) { in mcux_flexcan_set_timing()
142 return -EINVAL; in mcux_flexcan_set_timing()
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Dcan_nxp_s32_canxl.c2 * Copyright 2022-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
30 #define RX_MBIDX_TO_ALLOC_IDX(x) (x - CONFIG_CAN_NXP_S32_MAX_TX)
125 struct can_timing timing; member
152 const struct can_nxp_s32_config *config = dev->config; in can_nxp_s32_config_rx_fifo_filter() local
153 struct can_nxp_s32_data *data = dev->data; in can_nxp_s32_config_rx_fifo_filter()
156 (void)config->base_rx_fifo_ctrl->RXFSYSLOCK; in can_nxp_s32_config_rx_fifo_filter()
158 CanXL_ConfigIDFilter(config->base_rx_fifo, in can_nxp_s32_config_rx_fifo_filter()
159 &data->rx_fifo_filter[filter_id], filter_id); in can_nxp_s32_config_rx_fifo_filter()
161 if ((config->base_rx_fifo_ctrl->RXFCSTA & CANXL_RXFIFO_CONTROL_RXFCSTA_SYSLOCK_MASK) in can_nxp_s32_config_rx_fifo_filter()
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Dcan_stm32_bxcan.c5 * SPDX-License-Identifier: Apache-2.0
82 can_tx_callback_t callback = mb->tx_callback; in can_stm32_signal_tx_complete()
85 callback(dev, status, mb->callback_arg); in can_stm32_signal_tx_complete()
86 mb->tx_callback = NULL; in can_stm32_signal_tx_complete()
94 if (mbox->RIR & CAN_RI0R_IDE) { in can_stm32_rx_fifo_pop()
95 frame->id = mbox->RIR >> CAN_RI0R_EXID_Pos; in can_stm32_rx_fifo_pop()
96 frame->flags |= CAN_FRAME_IDE; in can_stm32_rx_fifo_pop()
98 frame->id = mbox->RIR >> CAN_RI0R_STID_Pos; in can_stm32_rx_fifo_pop()
101 if ((mbox->RIR & CAN_RI0R_RTR) != 0) { in can_stm32_rx_fifo_pop()
102 frame->flags |= CAN_FRAME_RTR; in can_stm32_rx_fifo_pop()
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Dcan_rcar.c4 * SPDX-License-Identifier: Apache-2.0
24 #define RCAR_CAN_CTLR_BOM (3 << 11) /* Bus-Off Recovery Mode Bits */
25 #define RCAR_CAN_CTLR_BOM_ENT BIT(11) /* Automatic halt mode entry at bus-off entry */
35 /* Mask Register */
57 /* Mask Invalid Register 0 */
59 /* Mask Invalid Register 1 */
136 #define RCAR_CAN_EIFR_BORIF BIT(4) /* Bus-Off Recovery Detect Flag */
137 #define RCAR_CAN_EIFR_BOEIF BIT(3) /* Bus-Off Entry Detect Flag */
148 * mailbox 60 - 63 - Rx FIFO mailboxes
149 * mailbox 56 - 59 - Tx FIFO mailboxes
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Dcan_mcp251xfd.c5 * SPDX-License-Identifier: Apache-2.0
27 if ((src->flags & CAN_FRAME_IDE) != 0) { in mcp251xfd_canframe_to_txobj()
28 dst->id = FIELD_PREP(MCP251XFD_OBJ_ID_SID_MASK, src->id >> 18); in mcp251xfd_canframe_to_txobj()
29 dst->id |= FIELD_PREP(MCP251XFD_OBJ_ID_EID_MASK, src->id); in mcp251xfd_canframe_to_txobj()
31 dst->flags |= MCP251XFD_OBJ_FLAGS_IDE; in mcp251xfd_canframe_to_txobj()
33 dst->id = FIELD_PREP(MCP251XFD_OBJ_ID_SID_MASK, src->id); in mcp251xfd_canframe_to_txobj()
36 if ((src->flags & CAN_FRAME_BRS) != 0) { in mcp251xfd_canframe_to_txobj()
37 dst->flags |= MCP251XFD_OBJ_FLAGS_BRS; in mcp251xfd_canframe_to_txobj()
40 dst->flags |= FIELD_PREP(MCP251XFD_OBJ_FLAGS_DLC_MASK, src->dlc); in mcp251xfd_canframe_to_txobj()
42 if ((src->flags & CAN_FRAME_FDF) != 0) { in mcp251xfd_canframe_to_txobj()
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Dcan_xmc4xxx.c4 * SPDX-License-Identifier: Apache-2.0
39 #define CAN_XMC4XXX_REG_TO_NODE_IND(reg) (((uint32_t)(reg) - (uint32_t)CAN_NODE0_BASE) / 0x100)
92 struct can_xmc4xxx_data *dev_data = dev->data; in can_xmc4xxx_set_mode()
93 const struct can_xmc4xxx_config *dev_cfg = dev->config; in can_xmc4xxx_set_mode()
95 if (dev_data->common.started) { in can_xmc4xxx_set_mode()
96 return -EBUSY; in can_xmc4xxx_set_mode()
101 return -ENOTSUP; in can_xmc4xxx_set_mode()
105 XMC_CAN_NODE_SetAnalyzerMode(dev_cfg->can); in can_xmc4xxx_set_mode()
107 XMC_CAN_NODE_ReSetAnalyzerMode(dev_cfg->can); in can_xmc4xxx_set_mode()
110 dev_data->common.mode = mode; in can_xmc4xxx_set_mode()
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Dcan_sja1000.c4 * SPDX-License-Identifier: Apache-2.0
24 const struct can_sja1000_config *config = dev->config; in can_sja1000_write_reg() local
26 config->write_reg(dev, reg, val); in can_sja1000_write_reg()
31 const struct can_sja1000_config *config = dev->config; in can_sja1000_read_reg() local
33 return config->read_reg(dev, reg); in can_sja1000_read_reg()
44 if (--retries < 0) { in can_sja1000_enter_reset_mode()
45 return -EIO; in can_sja1000_enter_reset_mode()
72 if (--retries < 0) { in can_sja1000_leave_reset_mode()
73 return -EIO; in can_sja1000_leave_reset_mode()
96 struct can_sja1000_data *data = dev->data; in can_sja1000_tx_done()
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Dcan_mcp2515.c4 * SPDX-License-Identifier: Apache-2.0
28 const struct mcp2515_config *dev_cfg = dev->config; in mcp2515_cmd_soft_reset()
39 return spi_write_dt(&dev_cfg->bus, &tx); in mcp2515_cmd_soft_reset()
43 uint8_t mask, in mcp2515_cmd_bit_modify() argument
46 const struct mcp2515_config *dev_cfg = dev->config; in mcp2515_cmd_bit_modify()
48 uint8_t cmd_buf[] = { MCP2515_OPCODE_BIT_MODIFY, reg_addr, mask, data }; in mcp2515_cmd_bit_modify()
57 return spi_write_dt(&dev_cfg->bus, &tx); in mcp2515_cmd_bit_modify()
63 const struct mcp2515_config *dev_cfg = dev->config; in mcp2515_cmd_write_reg()
75 return spi_write_dt(&dev_cfg->bus, &tx); in mcp2515_cmd_write_reg()
95 const struct mcp2515_config *dev_cfg = dev->config; in mcp2515_cmd_load_tx_buffer()
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Dcan_mcan.c2 * Copyright (c) 2022-2023 Vestas Wind Systems A/S
5 * SPDX-License-Identifier: Apache-2.0
22 const struct can_mcan_config *config = dev->config; in can_mcan_read_reg() local
25 err = config->ops->read_reg(dev, reg, val); in can_mcan_read_reg()
35 const struct can_mcan_config *config = dev->config; in can_mcan_write_reg() local
38 err = config->ops->write_reg(dev, reg, val); in can_mcan_write_reg()
48 struct can_mcan_data *data = dev->data; in can_mcan_exit_sleep_mode()
53 k_mutex_lock(&data->lock, K_FOREVER); in can_mcan_exit_sleep_mode()
75 if (k_cycle_get_32() - start_time > k_ms_to_cyc_ceil32(CAN_INIT_TIMEOUT_MS)) { in can_mcan_exit_sleep_mode()
82 err = -EAGAIN; in can_mcan_exit_sleep_mode()
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Dcan_native_linux.c4 * SPDX-License-Identifier: Apache-2.0
55 struct can_native_linux_data *data = dev->data; in dispatch_frame()
59 k_mutex_lock(&data->filter_mutex, K_FOREVER); in dispatch_frame()
61 for (int filter_id = 0; filter_id < ARRAY_SIZE(data->filters); filter_id++) { in dispatch_frame()
62 if (data->filters[filter_id].rx_cb == NULL) { in dispatch_frame()
66 if (!can_frame_matches_filter(frame, &data->filters[filter_id].filter)) { in dispatch_frame()
73 callback = data->filters[filter_id].rx_cb; in dispatch_frame()
74 callback(dev, &tmp_frame, data->filters[filter_id].cb_arg); in dispatch_frame()
77 k_mutex_unlock(&data->filter_mutex); in dispatch_frame()
83 struct can_native_linux_data *data = dev->data; in rx_thread()
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/Zephyr-latest/samples/drivers/mspi/mspi_flash/boards/
Dapollo3p_evb.overlay4 * SPDX-License-Identifier: Apache-2.0
23 pinctrl-0 = <&mspi1_default>;
24 pinctrl-1 = <&mspi1_sleep>;
25 pinctrl-2 = <&mspi1_psram>;
26 pinctrl-3 = <&mspi1_flash>;
27 pinctrl-names = "default","sleep","psram","flash";
30 ce-gpios = <&gpio64_95 5 GPIO_ACTIVE_LOW>,
33 cmdq-buffer-location = ".mspi_buff";
34 cmdq-buffer-size = <256>;
37 compatible = "ambiq,mspi-device", "mspi-aps6404l";
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/Zephyr-latest/tests/drivers/mspi/flash/boards/
Dapollo3p_evb.overlay3 * SPDX-License-Identifier: Apache-2.0
18 compatible = "ambiq,mspi-controller";
19 pinctrl-0 = <&mspi1_default>;
20 pinctrl-1 = <&mspi1_sleep>;
21 pinctrl-2 = <&mspi1_flash>;
22 pinctrl-names = "default","sleep","flash";
25 ce-gpios = <&gpio32_63 18 GPIO_ACTIVE_LOW>;
27 cmdq-buffer-location = ".mspi_buff";
28 cmdq-buffer-size = <256>;
31 compatible = "ambiq,mspi-device", "mspi-atxp032";
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/Zephyr-latest/samples/drivers/memc/boards/
Dapollo3p_evb.overlay4 * SPDX-License-Identifier: Apache-2.0
23 pinctrl-0 = <&mspi1_default>;
24 pinctrl-1 = <&mspi1_sleep>;
25 pinctrl-2 = <&mspi1_psram>;
26 pinctrl-names = "default","sleep","psram";
29 ce-gpios = <&gpio64_95 5 GPIO_ACTIVE_LOW>,
32 cmdq-buffer-location = ".mspi_buff";
33 cmdq-buffer-size = <256>;
36 compatible = "ambiq,mspi-device", "mspi-aps6404l";
40 mspi-max-frequency = <48000000>;
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/Zephyr-latest/samples/drivers/mspi/mspi_async/boards/
Dapollo3p_evb.overlay4 * SPDX-License-Identifier: Apache-2.0
23 pinctrl-0 = <&mspi1_default>;
24 pinctrl-1 = <&mspi1_sleep>;
25 pinctrl-2 = <&mspi1_psram>;
26 pinctrl-names = "default","sleep","psram";
29 ce-gpios = <&gpio64_95 5 GPIO_ACTIVE_LOW>,
32 cmdq-buffer-location = ".mspi_buff";
33 cmdq-buffer-size = <256>;
36 compatible = "ambiq,mspi-device", "mspi-aps6404l";
40 mspi-max-frequency = <48000000>;
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/Zephyr-latest/drivers/led_strip/
Dtlc5971.c4 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/dt-bindings/led/led.h>
57 /** GS reference clock edge select bit for OUTXn on-off timing control in FC data */
60 /** Constant-current output enable bit in FC data (0 = output control enabled, 1 = blank). */
66 /** Display timing reset mode enable bit in FC data (0 = disabled, 1 = enabled). */
69 /** Bit mask for write cmd in data byte 27 */
72 /** Bit mask for control bits in data byte 27 */
75 /** Bit mask for control bits in data byte 26 */
78 /** Bit mask for global brightness control for color 1 in data byte 26, upper 5 bits of GBC */
81 /** Bit mask for global brightness control for color 1 in data byte 25, lower 2 bits of GBC */
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/Zephyr-latest/drivers/sensor/s11059/
Ds11059.c4 * SPDX-License-Identifier: Apache-2.0
7 * https://datasheetspdf.com/pdf/1323325/Hamamatsu/S11059-02DT/1
33 /* bit mask for control */
83 /* Integration timing in Manual integration mode */
104 const struct s11059_dev_config *cfg = dev->config; in s11059_samples_read()
108 return -EINVAL; in s11059_samples_read()
111 rc = i2c_burst_read_dt(&cfg->bus, addr, (uint8_t *)val, size); in s11059_samples_read()
125 const struct s11059_dev_config *cfg = dev->config; in s11059_control_write()
128 return i2c_write_dt(&cfg->bus, opcode, sizeof(opcode)); in s11059_control_write()
133 const struct s11059_dev_config *cfg = dev->config; in s11059_manual_timing_write()
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/Zephyr-latest/include/zephyr/drivers/
Dcan.h6 * SPDX-License-Identifier: Apache-2.0
45 * @brief Bit mask for a standard (11-bit) CAN identifier.
50 * @brief Bit mask for an extended (29-bit) CAN identifier.
103 /** Controller requires manual recovery after entering bus-off state */
122 /** Error-active state (RX/TX error count < 96). */
124 /** Error-warning state (RX/TX error count < 128). */
126 /** Error-passive state (RX/TX error count < 256). */
128 /** Bus-off state (RX/TX error count >= 256). */
141 /** Frame uses extended (29-bit) CAN ID */
153 /** CAN FD Error State Indicator (ESI). Indicates that the transmitting node is in error-passive
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/Zephyr-latest/drivers/sdhc/
Dsdhc_esp32.c4 * SPDX-License-Identifier: Apache-2.0
48 /* mask for card current state */
81 uint32_t bus_clock; /* Value in Hz. ESP-IDF functions use kHz instead */
84 enum sdhc_timing_mode timing; member
98 * - one is the clock generator which drives SDMMC peripheral,
99 * it can be configured using sdio_hw->clock register. It can generate
101 * - 4 clock dividers inside SDMMC peripheral, which can divide clock
105 * For cards which aren't UHS-1 or UHS-2 cards, which we don't support,
107 * Note: for non-UHS-1 cards, HS mode is optional.
140 sdio_hw->ctrl.dma_enable = 1; in sdmmc_host_dma_init()
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Dimx_usdhc.c4 * SPDX-License-Identifier: Apache-2.0
101 struct usdhc_data *data = dev->data; in transfer_complete_cb()
104 data->transfer_status |= TRANSFER_DATA_FAILED; in transfer_complete_cb()
106 data->transfer_status |= TRANSFER_DATA_COMPLETE; in transfer_complete_cb()
108 data->transfer_status |= TRANSFER_CMD_FAILED; in transfer_complete_cb()
110 data->transfer_status |= TRANSFER_CMD_COMPLETE; in transfer_complete_cb()
112 k_sem_give(&data->transfer_sem); in transfer_complete_cb()
119 struct usdhc_data *data = dev->data; in sdio_interrupt_cb()
121 if (data->sdhc_cb) { in sdio_interrupt_cb()
122 data->sdhc_cb(dev, SDHC_INT_SDIO, data->sdhc_cb_user_data); in sdio_interrupt_cb()
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Drcar_mmc.c4 * SPDX-License-Identifier: Apache-2.0
106 /* cleanup SD card interrupt flag register and mask their interrupts */
109 struct mmc_rcar_data *data = dev->data; in rcar_mmc_reset_and_mask_irqs()
124 k_sem_reset(&data->irq_xref_fin); in rcar_mmc_reset_and_mask_irqs()
138 * @retval -EINVAL: the dev pointer is NULL
145 return -EINVAL; in rcar_mmc_card_busy()
160 * @retval -ETIMEDOUT: timed out while tx/rx
161 * @retval -EIO: I/O error
162 * @retval -EILSEQ: communication out of sync
170 return -ETIMEDOUT; in rcar_mmc_check_errors()
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/Zephyr-latest/kernel/
DKconfig3 # Copyright (c) 2014-2015 Wind River Systems, Inc.
4 # SPDX-License-Identifier: Apache-2.0
9 module-str = kernel
12 config MULTITHREADING
13 bool "Multi-threading" if ARCH_HAS_SINGLE_THREAD_SUPPORT
26 config NUM_COOP_PRIORITIES
35 K_PRIO_COOP(0) to K_PRIO_COOP(CONFIG_NUM_COOP_PRIORITIES - 1)
39 -CONFIG_NUM_COOP_PRIORITIES to -1
51 config NUM_PREEMPT_PRIORITIES
58 to priorities 0 to CONFIG_NUM_PREEMPT_PRIORITIES - 1.
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/Zephyr-latest/tests/drivers/input/kbd_matrix/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
110 switch (evt->code) { in test_cb()
112 col = evt->value; in test_cb()
115 row = evt->value; in test_cb()
118 val = evt->value; in test_cb()
122 if (evt->sync) { in test_cb()
151 const struct input_kbd_matrix_common_config *cfg = test_dev->config; in ZTEST()
156 k_sleep(K_USEC(cfg->debounce_down_us / 2)); in ZTEST()
159 k_sleep(K_USEC(cfg->debounce_down_us)); in ZTEST()
163 k_sleep(K_USEC(cfg->debounce_up_us / 2)); in ZTEST()
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/Zephyr-latest/drivers/sensor/ams/tsl2561/
Dtsl2561.c4 * SPDX-License-Identifier: Apache-2.0
50 /* Timing register fields */
54 /* ID register part number mask */
104 const struct tsl2561_config *config = dev->config; in tsl2561_reg_read() local
107 ret = i2c_write_read_dt(&config->i2c, &cmd, 1U, buf, size); in tsl2561_reg_read()
119 const struct tsl2561_config *config = dev->config; in tsl2561_reg_write() local
125 ret = i2c_write_dt(&config->i2c, buf, 2U); in tsl2561_reg_write()
136 const struct tsl2561_config *config = dev->config; in tsl2561_sample_fetch() local
137 struct tsl2561_data *data = dev->data; in tsl2561_sample_fetch()
143 return -ENOTSUP; in tsl2561_sample_fetch()
[all …]
/Zephyr-latest/drivers/display/
Ddisplay_nrf_led_matrix.c4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/gpio/gpio.h>
31 #if (GROUP_SIZE > DT_PROP(TIMER_NODE, cc_num) - 1) || \
33 #error "Invalid pixel-group-size configured."
40 #error "Invalid length of pixel-mapping."
48 _GET_ROW_IDX(dev_config->pixel_mapping[pixel_idx])
54 _GET_COL_IDX(dev_config->pixel_mapping[pixel_idx])
59 "Invalid row index in pixel-mapping["#idx"]."); \
61 "Invalid column index in pixel-mapping["#idx"].");
77 #error "Invalid pixel period. Change refresh-frequency or pixel-group-size."
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