1/* 2 * Copyright (c) 2024, Ambiq Micro Inc. <www.ambiq.com> 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7/ { 8 aliases { 9 psram0 = &aps6404l; 10 }; 11}; 12 13&gpio64_95 { 14 status = "okay"; 15}; 16 17&gpio32_63 { 18 status = "okay"; 19}; 20 21&mspi1 { 22 23 pinctrl-0 = <&mspi1_default>; 24 pinctrl-1 = <&mspi1_sleep>; 25 pinctrl-2 = <&mspi1_psram>; 26 pinctrl-names = "default","sleep","psram"; 27 status = "okay"; 28 29 ce-gpios = <&gpio64_95 5 GPIO_ACTIVE_LOW>, 30 <&gpio32_63 18 GPIO_ACTIVE_LOW>; 31 32 cmdq-buffer-location = ".mspi_buff"; 33 cmdq-buffer-size = <256>; 34 35 aps6404l: aps6404l@0 { 36 compatible = "ambiq,mspi-device", "mspi-aps6404l"; 37 size = <DT_SIZE_M(64)>; 38 reg = <0>; 39 status = "okay"; 40 mspi-max-frequency = <48000000>; 41 mspi-io-mode = "MSPI_IO_MODE_QUAD"; 42 mspi-data-rate = "MSPI_DATA_RATE_SINGLE"; 43 mspi-hardware-ce-num = <0>; 44 read-command = <0xEB>; 45 write-command = <0x38>; 46 command-length = "INSTR_1_BYTE"; 47 address-length = "ADDR_3_BYTE"; 48 rx-dummy = <6>; 49 tx-dummy = <0>; 50 xip-config = <1 0 0 0>; 51 ce-break-config = <1024 3>; 52 ambiq,timing-config-mask = <3>; 53 ambiq,timing-config = <0 6 0 0 0 0 0 0>; 54 }; 55 56}; 57 58&pinctrl { 59 60 mspi1_sleep: mspi1_sleep{ 61 62 group1 { 63 pinmux = <GPIO_P51>, 64 <GPIO_P52>, 65 <GPIO_P53>, 66 <GPIO_P54>, 67 <GPIO_P55>, 68 <GPIO_P56>, 69 <GPIO_P57>, 70 <GPIO_P58>, 71 <GPIO_P59>, 72 <GPIO_P69>, 73 <GPIO_P50>; 74 }; 75 76 }; 77 78 mspi1_psram: mspi1_psram{ 79 80 group1 { 81 pinmux = <MSPI1_0_P51>, 82 <MSPI1_1_P52>, 83 <MSPI1_2_P53>, 84 <MSPI1_3_P54>, 85 <MSPI1_4_P55>, 86 <MSPI1_5_P56>, 87 <MSPI1_6_P57>, 88 <MSPI1_7_P58>; 89 drive-strength = "0.75"; 90 ambiq,iom-mspi = <0>; 91 ambiq,iom-num = <1>; 92 }; 93 94 group2 { 95 pinmux = <MSPI1_8_P59>; 96 drive-strength = "0.75"; 97 ambiq,iom-mspi = <0>; 98 ambiq,iom-num = <2>; 99 }; 100 101 group3 { 102 pinmux = <NCE69_P69>; 103 drive-strength = "1.0"; 104 ambiq,iom-mspi = <0>; 105 ambiq,iom-num = <1>; 106 }; 107 108 group4 { 109 pinmux = <GPIO_P50>; 110 }; 111 }; 112}; 113