1/*
2 * Copyright (c) 2024 Ambiq Micro Inc. <www.ambiq.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/ {
8	aliases {
9		flash0 = &atxp032;
10	};
11};
12
13&gpio64_95 {
14	status = "okay";
15};
16
17&gpio32_63 {
18	status = "okay";
19};
20
21&mspi1 {
22
23	pinctrl-0 = <&mspi1_default>;
24	pinctrl-1 = <&mspi1_sleep>;
25	pinctrl-2 = <&mspi1_psram>;
26	pinctrl-3 = <&mspi1_flash>;
27	pinctrl-names = "default","sleep","psram","flash";
28	status = "okay";
29
30	ce-gpios = <&gpio64_95 5 GPIO_ACTIVE_LOW>,
31		   <&gpio32_63 18 GPIO_ACTIVE_LOW>;
32
33	cmdq-buffer-location = ".mspi_buff";
34	cmdq-buffer-size = <256>;
35
36	aps6404l: aps6404l@0 {
37		compatible = "ambiq,mspi-device", "mspi-aps6404l";
38		size = <DT_SIZE_M(64)>;
39		reg = <0>;
40		status = "disabled";
41		mspi-max-frequency = <48000000>;
42		mspi-io-mode = "MSPI_IO_MODE_QUAD";
43		mspi-data-rate = "MSPI_DATA_RATE_SINGLE";
44		mspi-hardware-ce-num = <0>;
45		read-command = <0xEB>;
46		write-command = <0x38>;
47		command-length = "INSTR_1_BYTE";
48		address-length = "ADDR_3_BYTE";
49		rx-dummy = <6>;
50		tx-dummy = <0>;
51		xip-config = <1 0 0 0>;
52		ce-break-config = <1024 3>;
53		ambiq,timing-config-mask = <3>;
54		ambiq,timing-config = <0 6 0 0 0 0 0 0>;
55	};
56
57	atxp032: atxp032@1 {
58		compatible = "ambiq,mspi-device", "mspi-atxp032";
59		size = <DT_SIZE_M(32)>;
60		reg = <1>;
61		status = "okay";
62		mspi-max-frequency = <48000000>;
63		mspi-io-mode = "MSPI_IO_MODE_OCTAL";
64		mspi-data-rate = "MSPI_DATA_RATE_SINGLE";
65		mspi-hardware-ce-num = <0>;
66		read-command = <0x0B>;
67		write-command = <0x02>;
68		command-length = "INSTR_1_BYTE";
69		address-length = "ADDR_4_BYTE";
70		rx-dummy = <8>;
71		tx-dummy = <0>;
72		xip-config = <1 0 0 0>;
73		ce-break-config = <0 0>;
74		ambiq,timing-config-mask = <3>;
75		ambiq,timing-config = <0 8 0 0 0 0 0 0>;
76	};
77
78};
79
80&pinctrl {
81
82	mspi1_sleep: mspi1_sleep{
83
84		group1 {
85			pinmux = <GPIO_P51>,
86				 <GPIO_P52>,
87				 <GPIO_P53>,
88				 <GPIO_P54>,
89				 <GPIO_P55>,
90				 <GPIO_P56>,
91				 <GPIO_P57>,
92				 <GPIO_P58>,
93				 <GPIO_P59>,
94				 <GPIO_P69>,
95				 <GPIO_P50>;
96		};
97
98	};
99
100	mspi1_psram: mspi1_psram{
101
102		group1 {
103			pinmux = <MSPI1_0_P51>,
104				 <MSPI1_1_P52>,
105				 <MSPI1_2_P53>,
106				 <MSPI1_3_P54>,
107				 <MSPI1_4_P55>,
108				 <MSPI1_5_P56>,
109				 <MSPI1_6_P57>,
110				 <MSPI1_7_P58>;
111			drive-strength = "0.75";
112			ambiq,iom-mspi = <0>;
113			ambiq,iom-num = <1>;
114		};
115
116		group2 {
117			pinmux = <MSPI1_8_P59>;
118			drive-strength = "0.75";
119			ambiq,iom-mspi = <0>;
120			ambiq,iom-num = <2>;
121		};
122
123		group3 {
124			pinmux = <NCE69_P69>;
125			drive-strength = "1.0";
126			ambiq,iom-mspi = <0>;
127			ambiq,iom-num = <1>;
128		};
129
130		group4 {
131			pinmux = <GPIO_P50>;
132		};
133
134	};
135
136	mspi1_flash: mspi1_flash{
137
138		group1 {
139			pinmux = <MSPI1_0_P51>,
140					<MSPI1_1_P52>,
141					<MSPI1_2_P53>,
142					<MSPI1_3_P54>,
143					<MSPI1_4_P55>,
144					<MSPI1_5_P56>,
145					<MSPI1_6_P57>,
146					<MSPI1_7_P58>;
147			drive-strength = "0.75";
148			ambiq,iom-mspi = <0>;
149			ambiq,iom-num = <1>;
150		};
151
152		group2 {
153			pinmux = <MSPI1_8_P59>;
154			drive-strength = "0.75";
155			ambiq,iom-mspi = <0>;
156			ambiq,iom-num = <2>;
157		};
158
159		group3 {
160			pinmux = <NCE50_P50>;
161			drive-strength = "1.0";
162			ambiq,iom-mspi = <0>;
163			ambiq,iom-num = <1>;
164		};
165
166		group4 {
167			pinmux = <GPIO_P69>;
168		};
169
170	};
171};
172