1/* 2 * Copyright (c) 2024 Ambiq Micro Inc. <www.ambiq.com> 3 * SPDX-License-Identifier: Apache-2.0 4 */ 5 6/ { 7 aliases { 8 mspi0 = &mspi1; 9 }; 10}; 11 12&gpio32_63 { 13 status = "okay"; 14}; 15 16&mspi1 { 17 18 compatible = "ambiq,mspi-controller"; 19 pinctrl-0 = <&mspi1_default>; 20 pinctrl-1 = <&mspi1_sleep>; 21 pinctrl-2 = <&mspi1_flash>; 22 pinctrl-names = "default","sleep","flash"; 23 status = "okay"; 24 25 ce-gpios = <&gpio32_63 18 GPIO_ACTIVE_LOW>; 26 27 cmdq-buffer-location = ".mspi_buff"; 28 cmdq-buffer-size = <256>; 29 30 atxp032: atxp032@0 { 31 compatible = "ambiq,mspi-device", "mspi-atxp032"; 32 size = <DT_SIZE_M(32)>; 33 reg = <0>; 34 status = "okay"; 35 mspi-max-frequency = <48000000>; 36 mspi-io-mode = "MSPI_IO_MODE_OCTAL"; 37 mspi-data-rate = "MSPI_DATA_RATE_SINGLE"; 38 mspi-hardware-ce-num = <0>; 39 read-command = <0x0B>; 40 write-command = <0x02>; 41 command-length = "INSTR_1_BYTE"; 42 address-length = "ADDR_4_BYTE"; 43 rx-dummy = <8>; 44 tx-dummy = <0>; 45 xip-config = <1 0 0 0>; 46 ce-break-config = <0 0>; 47 ambiq,timing-config-mask = <3>; 48 ambiq,timing-config = <0 8 0 0 0 0 0 0>; 49 }; 50 51}; 52 53&pinctrl { 54 55 mspi1_sleep: mspi1_sleep{ 56 group1 { 57 pinmux = <GPIO_P51>, 58 <GPIO_P52>, 59 <GPIO_P53>, 60 <GPIO_P54>, 61 <GPIO_P55>, 62 <GPIO_P56>, 63 <GPIO_P57>, 64 <GPIO_P58>, 65 <GPIO_P59>, 66 <GPIO_P69>, 67 <GPIO_P50>; 68 }; 69 }; 70 71 mspi1_flash: mspi1_flash{ 72 73 group1 { 74 pinmux = <MSPI1_0_P51>, 75 <MSPI1_1_P52>, 76 <MSPI1_2_P53>, 77 <MSPI1_3_P54>, 78 <MSPI1_4_P55>, 79 <MSPI1_5_P56>, 80 <MSPI1_6_P57>, 81 <MSPI1_7_P58>; 82 drive-strength = "0.75"; 83 ambiq,iom-mspi = <0>; 84 ambiq,iom-num = <1>; 85 }; 86 87 group2 { 88 pinmux = <MSPI1_8_P59>; 89 drive-strength = "0.75"; 90 ambiq,iom-mspi = <0>; 91 ambiq,iom-num = <2>; 92 }; 93 94 group3 { 95 pinmux = <NCE50_P50>; 96 drive-strength = "1.0"; 97 ambiq,iom-mspi = <0>; 98 ambiq,iom-num = <1>; 99 }; 100 101 group4 { 102 pinmux = <GPIO_P69>; 103 }; 104 105 }; 106 107}; 108