1 /*
2 * Copyright (c) 2021 IoT.bzh
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT renesas_rcar_can
8
9 #include <zephyr/kernel.h>
10 #include <errno.h>
11 #include <zephyr/drivers/can.h>
12 #include <zephyr/drivers/can/transceiver.h>
13 #include <zephyr/drivers/clock_control.h>
14 #include <zephyr/drivers/clock_control/renesas_cpg_mssr.h>
15 #include <zephyr/drivers/pinctrl.h>
16 #include <zephyr/logging/log.h>
17 #include <zephyr/irq.h>
18
19 LOG_MODULE_REGISTER(can_rcar, CONFIG_CAN_LOG_LEVEL);
20
21 /* Control Register */
22 #define RCAR_CAN_CTLR 0x0840
23 /* Control Register bits */
24 #define RCAR_CAN_CTLR_BOM (3 << 11) /* Bus-Off Recovery Mode Bits */
25 #define RCAR_CAN_CTLR_BOM_ENT BIT(11) /* Automatic halt mode entry at bus-off entry */
26 #define RCAR_CAN_CTLR_SLPM BIT(10)
27 #define RCAR_CAN_CTLR_CANM_HALT BIT(9)
28 #define RCAR_CAN_CTLR_CANM_RESET BIT(8)
29 #define RCAR_CAN_CTLR_CANM_MASK (3 << 8)
30 #define RCAR_CAN_CTLR_MLM BIT(3) /* Message Lost Mode Select */
31 #define RCAR_CAN_CTLR_IDFM (3 << 1) /* ID Format Mode Select Bits */
32 #define RCAR_CAN_CTLR_IDFM_MIXED BIT(2) /* Mixed ID mode */
33 #define RCAR_CAN_CTLR_MBM BIT(0) /* Mailbox Mode select */
34
35 /* Mask Register */
36 #define RCAR_CAN_MKR0 0x0430
37 #define RCAR_CAN_MKR1 0x0434
38 #define RCAR_CAN_MKR2 0x0400
39 #define RCAR_CAN_MKR3 0x0404
40 #define RCAR_CAN_MKR4 0x0408
41 #define RCAR_CAN_MKR5 0x040C
42 #define RCAR_CAN_MKR6 0x0410
43 #define RCAR_CAN_MKR7 0x0414
44 #define RCAR_CAN_MKR8 0x0418
45 #define RCAR_CAN_MKR9 0x041C
46
47 /* FIFO Received ID Compare Register 0 */
48 #define RCAR_CAN_FIDCR0 0x0420
49
50 /* FIFO Received ID Compare Register 1 */
51 #define RCAR_CAN_FIDCR1 0x0424
52
53 /* FIFO Received ID Compare Registers 0 and 1 bits */
54 #define RCAR_CAN_FIDCR_IDE BIT(31) /* ID Extension Bit */
55 #define RCAR_CAN_FIDCR_RTR BIT(30) /* RTR Bit */
56
57 /* Mask Invalid Register 0 */
58 #define RCAR_CAN_MKIVLR0 0x0438
59 /* Mask Invalid Register 1 */
60 #define RCAR_CAN_MKIVLR1 0x0428
61 /* Mailbox Interrupt Enable Registers*/
62 #define RCAR_CAN_MIER0 0x043C
63 #define RCAR_CAN_MIER1 0x042C
64 #define RCAR_CAN_MIER1_RXFIE BIT(28) /* Rx FIFO Interrupt Enable */
65 #define RCAR_CAN_MIER1_TXFIE BIT(24) /* Tx FIFO Interrupt Enable */
66
67 #define RCAR_CAN_STR 0x0842 /* Status Register */
68 #define RCAR_CAN_STR_RSTST BIT(8) /* Reset Status Bit */
69 #define RCAR_CAN_STR_HLTST BIT(9) /* Halt Status Bit */
70 #define RCAR_CAN_STR_SLPST BIT(10) /* Sleep Status Bit */
71 #define MAX_STR_READS 0x100
72
73 /* Bit Configuration Register */
74 #define RCAR_CAN_BCR 0x0844
75
76 /* Clock Select Register */
77 #define RCAR_CAN_CLKR 0x0847
78 #define RCAR_CAN_CLKR_EXT_CLOCK 0x3 /* External input clock */
79 #define RCAR_CAN_CLKR_CLKP2 0x1
80 #define RCAR_CAN_CLKR_CLKP1 0x0
81
82 /* Error Interrupt Enable Register */
83 #define RCAR_CAN_EIER 0x084C
84
85 /* Interrupt Enable Register */
86 #define RCAR_CAN_IER 0x0860
87 #define RCAR_CAN_IER_ERSIE BIT(5) /* Error Interrupt Enable Bit */
88 #define RCAR_CAN_IER_RXFIE BIT(4) /* Rx FIFO Interrupt Enable Bit */
89 #define RCAR_CAN_IER_TXFIE BIT(3) /* Tx FIFO Interrupt Enable Bit */
90
91 /* Interrupt Status Register */
92 #define RCAR_CAN_ISR 0x0861
93 #define RCAR_CAN_ISR_ERSF BIT(5) /* Error (ERS) Interrupt */
94 #define RCAR_CAN_ISR_RXFF BIT(4) /* Reception FIFO Interrupt */
95 #define RCAR_CAN_ISR_TXFF BIT(3) /* Transmission FIFO Interrupt */
96
97 /* Receive FIFO Control Register */
98 #define RCAR_CAN_RFCR 0x0848
99 #define RCAR_CAN_RFCR_RFE BIT(0) /* Receive FIFO Enable */
100 #define RCAR_CAN_RFCR_RFEST BIT(7) /* Receive FIFO Empty Flag */
101
102 /* Receive FIFO Pointer Control Register */
103 #define RCAR_CAN_RFPCR 0x0849
104
105 /* Transmit FIFO Control Register */
106 #define RCAR_CAN_TFCR 0x084A
107 #define RCAR_CAN_TFCR_TFE BIT(0) /* Transmit FIFO Enable */
108 #define RCAR_CAN_TFCR_TFUST (7 << 1) /* Transmit FIFO Unsent Msg Number Status Bits */
109 #define RCAR_CAN_TFCR_TFUST_SHIFT 1 /* Offset of Tx FIFO Unsent */
110
111 /* Transmit FIFO Pointer Control Register */
112 #define RCAR_CAN_TFPCR 0x084B
113
114 /* Error Code Store Register*/
115 #define RCAR_CAN_ECSR 0x0850 /* Error Code Store Register */
116 #define RCAR_CAN_ECSR_EDPM BIT(7) /* Error Display Mode Select */
117 #define RCAR_CAN_ECSR_ADEF BIT(6) /* ACK Delimiter Error Flag */
118 #define RCAR_CAN_ECSR_BE0F BIT(5) /* Bit Error (dominant) Flag */
119 #define RCAR_CAN_ECSR_BE1F BIT(4) /* Bit Error (recessive) Flag */
120 #define RCAR_CAN_ECSR_CEF BIT(3) /* CRC Error Flag */
121 #define RCAR_CAN_ECSR_AEF BIT(2) /* ACK Error Flag */
122 #define RCAR_CAN_ECSR_FEF BIT(1) /* Form Error Flag */
123 #define RCAR_CAN_ECSR_SEF BIT(0) /* Stuff Error Flag */
124
125 /* Test Control Register */
126 #define RCAR_CAN_TCR 0x0858
127 #define RCAR_CAN_TCR_TSTE BIT(0) /* Test Mode Enable Bit*/
128 #define RCAR_CAN_TCR_LISTEN_ONLY BIT(1)
129 #define RCAR_CAN_TCR_INT_LOOP (3 << 1) /* Internal loopback*/
130
131 /* Error Interrupt Factor Judge Register bits */
132 #define RCAR_CAN_EIFR 0x084D
133 #define RCAR_CAN_EIFR_BLIF BIT(7) /* Bus Lock Detect Flag */
134 #define RCAR_CAN_EIFR_OLIF BIT(6) /* Overload Frame Transmission */
135 #define RCAR_CAN_EIFR_ORIF BIT(5) /* Receive Overrun Detect Flag */
136 #define RCAR_CAN_EIFR_BORIF BIT(4) /* Bus-Off Recovery Detect Flag */
137 #define RCAR_CAN_EIFR_BOEIF BIT(3) /* Bus-Off Entry Detect Flag */
138 #define RCAR_CAN_EIFR_EPIF BIT(2) /* Error Passive Detect Flag */
139 #define RCAR_CAN_EIFR_EWIF BIT(1) /* Error Warning Detect Flag */
140 #define RCAR_CAN_EIFR_BEIF BIT(0) /* Bus Error Detect Flag */
141
142 /* Receive Error Count Register */
143 #define RCAR_CAN_RECR 0x084D
144 /* Transmit Error Count Register */
145 #define RCAR_CAN_TECR 0x084F
146
147 /* Mailbox configuration:
148 * mailbox 60 - 63 - Rx FIFO mailboxes
149 * mailbox 56 - 59 - Tx FIFO mailboxes
150 * non-FIFO mailboxes are not used
151 */
152 #define RCAR_CAN_MB_56 0x0380
153 #define RCAR_CAN_MB_60 0x03C0
154 /* DLC must be accessed as a 16 bit register */
155 #define RCAR_CAN_MB_DLC_OFFSET 0x4 /* Data length code */
156 #define RCAR_CAN_MB_DATA_OFFSET 0x6 /* Data section */
157 #define RCAR_CAN_MB_TSH_OFFSET 0x14 /* Timestamp upper byte */
158 #define RCAR_CAN_MB_TSL_OFFSET 0x15 /* Timestamp lower byte */
159 #define RCAR_CAN_FIFO_DEPTH 4
160 #define RCAR_CAN_MB_SID_SHIFT 18
161 #define RCAR_CAN_MB_RTR BIT(30)
162 #define RCAR_CAN_MB_IDE BIT(31)
163 #define RCAR_CAN_MB_SID_MASK 0x1FFC0000
164 #define RCAR_CAN_MB_EID_MASK 0x1FFFFFFF
165
166 typedef void (*init_func_t)(const struct device *dev);
167
168 struct can_rcar_cfg {
169 const struct can_driver_config common;
170 uint32_t reg_addr;
171 int reg_size;
172 init_func_t init_func;
173 const struct device *clock_dev;
174 struct rcar_cpg_clk mod_clk;
175 struct rcar_cpg_clk bus_clk;
176 const struct pinctrl_dev_config *pcfg;
177 };
178
179 struct can_rcar_tx_cb {
180 can_tx_callback_t cb;
181 void *cb_arg;
182 };
183
184 struct can_rcar_data {
185 struct can_driver_data common;
186 struct k_mutex inst_mutex;
187 struct k_sem tx_sem;
188 struct can_rcar_tx_cb tx_cb[RCAR_CAN_FIFO_DEPTH];
189 uint8_t tx_head;
190 uint8_t tx_tail;
191 uint8_t tx_unsent;
192 struct k_mutex rx_mutex;
193 can_rx_callback_t rx_callback[CONFIG_CAN_RCAR_MAX_FILTER];
194 void *rx_callback_arg[CONFIG_CAN_RCAR_MAX_FILTER];
195 struct can_filter filter[CONFIG_CAN_RCAR_MAX_FILTER];
196 enum can_state state;
197 };
198
can_rcar_read16(const struct can_rcar_cfg * config,uint32_t offs)199 static inline uint16_t can_rcar_read16(const struct can_rcar_cfg *config,
200 uint32_t offs)
201 {
202 return sys_read16(config->reg_addr + offs);
203 }
204
can_rcar_write16(const struct can_rcar_cfg * config,uint32_t offs,uint16_t value)205 static inline void can_rcar_write16(const struct can_rcar_cfg *config,
206 uint32_t offs, uint16_t value)
207 {
208 sys_write16(value, config->reg_addr + offs);
209 }
210
can_rcar_tx_done(const struct device * dev,uint8_t err)211 static void can_rcar_tx_done(const struct device *dev, uint8_t err)
212 {
213 struct can_rcar_data *data = dev->data;
214 struct can_rcar_tx_cb *tx_cb;
215
216 tx_cb = &data->tx_cb[data->tx_tail];
217 data->tx_tail++;
218 if (data->tx_tail >= RCAR_CAN_FIFO_DEPTH) {
219 data->tx_tail = 0;
220 }
221
222 data->tx_unsent--;
223 tx_cb->cb(dev, err, tx_cb->cb_arg);
224 k_sem_give(&data->tx_sem);
225 }
226
can_rcar_get_error_count(const struct can_rcar_cfg * config,struct can_bus_err_cnt * err_cnt)227 static void can_rcar_get_error_count(const struct can_rcar_cfg *config,
228 struct can_bus_err_cnt *err_cnt)
229 {
230 err_cnt->tx_err_cnt = sys_read8(config->reg_addr + RCAR_CAN_TECR);
231 err_cnt->rx_err_cnt = sys_read8(config->reg_addr + RCAR_CAN_RECR);
232 }
233
can_rcar_state_change(const struct device * dev,uint32_t newstate)234 static void can_rcar_state_change(const struct device *dev, uint32_t newstate)
235 {
236 const struct can_rcar_cfg *config = dev->config;
237 struct can_rcar_data *data = dev->data;
238 const can_state_change_callback_t cb = data->common.state_change_cb;
239 void *state_change_cb_data = data->common.state_change_cb_user_data;
240 struct can_bus_err_cnt err_cnt;
241
242 if (data->state == newstate) {
243 return;
244 }
245
246 LOG_DBG("Can state change new: %u old:%u\n", newstate, data->state);
247
248 data->state = newstate;
249
250 if (cb == NULL) {
251 return;
252 }
253 can_rcar_get_error_count(config, &err_cnt);
254 cb(dev, newstate, err_cnt, state_change_cb_data);
255 }
256
can_rcar_error(const struct device * dev)257 static void can_rcar_error(const struct device *dev)
258 {
259 const struct can_rcar_cfg *config = dev->config;
260 uint8_t eifr, ecsr;
261
262 eifr = sys_read8(config->reg_addr + RCAR_CAN_EIFR);
263
264 if (eifr & RCAR_CAN_EIFR_BEIF) {
265
266 ecsr = sys_read8(config->reg_addr + RCAR_CAN_ECSR);
267 if (ecsr & RCAR_CAN_ECSR_ADEF) {
268 CAN_STATS_ACK_ERROR_INC(dev);
269 sys_write8((uint8_t)~RCAR_CAN_ECSR_ADEF,
270 config->reg_addr + RCAR_CAN_ECSR);
271 }
272 if (ecsr & RCAR_CAN_ECSR_BE0F) {
273 CAN_STATS_BIT0_ERROR_INC(dev);
274 sys_write8((uint8_t)~RCAR_CAN_ECSR_BE0F,
275 config->reg_addr + RCAR_CAN_ECSR);
276 }
277 if (ecsr & RCAR_CAN_ECSR_BE1F) {
278 CAN_STATS_BIT1_ERROR_INC(dev);
279 sys_write8((uint8_t)~RCAR_CAN_ECSR_BE1F,
280 config->reg_addr + RCAR_CAN_ECSR);
281 }
282 if (ecsr & RCAR_CAN_ECSR_CEF) {
283 CAN_STATS_CRC_ERROR_INC(dev);
284 sys_write8((uint8_t)~RCAR_CAN_ECSR_CEF,
285 config->reg_addr + RCAR_CAN_ECSR);
286 }
287 if (ecsr & RCAR_CAN_ECSR_AEF) {
288 CAN_STATS_ACK_ERROR_INC(dev);
289 sys_write8((uint8_t)~RCAR_CAN_ECSR_AEF,
290 config->reg_addr + RCAR_CAN_ECSR);
291 }
292 if (ecsr & RCAR_CAN_ECSR_FEF) {
293 CAN_STATS_FORM_ERROR_INC(dev);
294 sys_write8((uint8_t)~RCAR_CAN_ECSR_FEF,
295 config->reg_addr + RCAR_CAN_ECSR);
296 }
297 if (ecsr & RCAR_CAN_ECSR_SEF) {
298 CAN_STATS_STUFF_ERROR_INC(dev);
299 sys_write8((uint8_t)~RCAR_CAN_ECSR_SEF,
300 config->reg_addr + RCAR_CAN_ECSR);
301 }
302
303 sys_write8((uint8_t)~RCAR_CAN_EIFR_BEIF,
304 config->reg_addr + RCAR_CAN_EIFR);
305 }
306 if (eifr & RCAR_CAN_EIFR_EWIF) {
307 LOG_DBG("Error warning interrupt\n");
308 /* Clear interrupt condition */
309 sys_write8((uint8_t)~RCAR_CAN_EIFR_EWIF,
310 config->reg_addr + RCAR_CAN_EIFR);
311 can_rcar_state_change(dev, CAN_STATE_ERROR_WARNING);
312 }
313 if (eifr & RCAR_CAN_EIFR_EPIF) {
314 LOG_DBG("Error passive interrupt\n");
315 /* Clear interrupt condition */
316 sys_write8((uint8_t)~RCAR_CAN_EIFR_EPIF,
317 config->reg_addr + RCAR_CAN_EIFR);
318 can_rcar_state_change(dev, CAN_STATE_ERROR_PASSIVE);
319 }
320 if (eifr & RCAR_CAN_EIFR_BORIF) {
321 LOG_DBG("Bus-off recovery interrupt\n");
322 sys_write8(RCAR_CAN_IER_ERSIE, config->reg_addr + RCAR_CAN_IER);
323 /* Clear interrupt condition */
324 sys_write8((uint8_t)~RCAR_CAN_EIFR_BORIF,
325 config->reg_addr + RCAR_CAN_EIFR);
326 can_rcar_state_change(dev, CAN_STATE_BUS_OFF);
327 }
328 if (eifr & RCAR_CAN_EIFR_BOEIF) {
329 LOG_DBG("Bus-off entry interrupt\n");
330 sys_write8(RCAR_CAN_IER_ERSIE, config->reg_addr + RCAR_CAN_IER);
331 /* Clear interrupt condition */
332 sys_write8((uint8_t)~RCAR_CAN_EIFR_BOEIF,
333 config->reg_addr + RCAR_CAN_EIFR);
334 can_rcar_state_change(dev, CAN_STATE_BUS_OFF);
335 }
336 if (eifr & RCAR_CAN_EIFR_ORIF) {
337 LOG_DBG("Receive overrun error interrupt\n");
338 CAN_STATS_RX_OVERRUN_INC(dev);
339 sys_write8((uint8_t)~RCAR_CAN_EIFR_ORIF,
340 config->reg_addr + RCAR_CAN_EIFR);
341 }
342 if (eifr & RCAR_CAN_EIFR_OLIF) {
343 LOG_DBG("Overload Frame Transmission error interrupt\n");
344 sys_write8((uint8_t)~RCAR_CAN_EIFR_OLIF,
345 config->reg_addr + RCAR_CAN_EIFR);
346 }
347 if (eifr & RCAR_CAN_EIFR_BLIF) {
348 LOG_DBG("Bus lock detected interrupt\n");
349 sys_write8((uint8_t)~RCAR_CAN_EIFR_BLIF,
350 config->reg_addr + RCAR_CAN_EIFR);
351 }
352 }
353
can_rcar_rx_filter_isr(const struct device * dev,struct can_rcar_data * data,const struct can_frame * frame)354 static void can_rcar_rx_filter_isr(const struct device *dev,
355 struct can_rcar_data *data,
356 const struct can_frame *frame)
357 {
358 struct can_frame tmp_frame;
359 uint8_t i;
360
361 #ifndef CONFIG_CAN_ACCEPT_RTR
362 if ((frame->flags & CAN_FRAME_RTR) != 0U) {
363 return;
364 }
365 #endif /* !CONFIG_CAN_ACCEPT_RTR */
366
367 for (i = 0; i < CONFIG_CAN_RCAR_MAX_FILTER; i++) {
368 if (data->rx_callback[i] == NULL) {
369 continue;
370 }
371
372 if (!can_frame_matches_filter(frame, &data->filter[i])) {
373 continue; /* filter did not match */
374 }
375 /* Make a temporary copy in case the user
376 * modifies the message.
377 */
378 tmp_frame = *frame;
379 data->rx_callback[i](dev, &tmp_frame, data->rx_callback_arg[i]);
380 }
381 }
382
can_rcar_rx_isr(const struct device * dev)383 static void can_rcar_rx_isr(const struct device *dev)
384 {
385 const struct can_rcar_cfg *config = dev->config;
386 struct can_rcar_data *data = dev->data;
387 struct can_frame frame = {0};
388 uint32_t val;
389 int i;
390
391 val = sys_read32(config->reg_addr + RCAR_CAN_MB_60);
392 if (val & RCAR_CAN_MB_IDE) {
393 frame.flags |= CAN_FRAME_IDE;
394 frame.id = val & RCAR_CAN_MB_EID_MASK;
395 } else {
396 frame.id = (val & RCAR_CAN_MB_SID_MASK) >> RCAR_CAN_MB_SID_SHIFT;
397 }
398
399 frame.dlc = sys_read16(config->reg_addr +
400 RCAR_CAN_MB_60 + RCAR_CAN_MB_DLC_OFFSET) & 0xF;
401
402 /* Be paranoid doc states that any value greater than 8
403 * should be considered as 8 bytes.
404 */
405 if (frame.dlc > CAN_MAX_DLC) {
406 frame.dlc = CAN_MAX_DLC;
407 }
408
409 if (val & RCAR_CAN_MB_RTR) {
410 frame.flags |= CAN_FRAME_RTR;
411 } else {
412 for (i = 0; i < frame.dlc; i++) {
413 frame.data[i] = sys_read8(config->reg_addr +
414 RCAR_CAN_MB_60 + RCAR_CAN_MB_DATA_OFFSET + i);
415 }
416 }
417 #if defined(CONFIG_CAN_RX_TIMESTAMP)
418 /* read upper byte */
419 frame.timestamp = sys_read8(config->reg_addr +
420 RCAR_CAN_MB_60 + RCAR_CAN_MB_TSH_OFFSET) << 8;
421 /* and then read lower byte */
422 frame.timestamp |= sys_read8(config->reg_addr +
423 RCAR_CAN_MB_60 + RCAR_CAN_MB_TSL_OFFSET);
424 #endif
425 /* Increment CPU side pointer */
426 sys_write8(0xff, config->reg_addr + RCAR_CAN_RFPCR);
427
428 can_rcar_rx_filter_isr(dev, data, &frame);
429 }
430
can_rcar_isr(const struct device * dev)431 static void can_rcar_isr(const struct device *dev)
432 {
433 const struct can_rcar_cfg *config = dev->config;
434 struct can_rcar_data *data = dev->data;
435 uint8_t isr, unsent;
436
437 isr = sys_read8(config->reg_addr + RCAR_CAN_ISR);
438 if (isr & RCAR_CAN_ISR_ERSF) {
439 /* Clear the Error interrupt */
440 isr &= ~RCAR_CAN_ISR_ERSF;
441 sys_write8(isr, config->reg_addr + RCAR_CAN_ISR);
442 can_rcar_error(dev);
443 }
444 if (isr & RCAR_CAN_ISR_TXFF) {
445 /* Check for sent messages */
446 while (1) {
447 unsent = sys_read8(config->reg_addr + RCAR_CAN_TFCR);
448 unsent = (unsent & RCAR_CAN_TFCR_TFUST) >>
449 RCAR_CAN_TFCR_TFUST_SHIFT;
450 if (data->tx_unsent <= unsent) {
451 break;
452 }
453 can_rcar_tx_done(dev, 0);
454 }
455
456 /* Clear the Tx interrupt */
457 isr = sys_read8(config->reg_addr + RCAR_CAN_ISR);
458 isr &= ~RCAR_CAN_ISR_TXFF;
459 sys_write8(isr, config->reg_addr + RCAR_CAN_ISR);
460 }
461 if (isr & RCAR_CAN_ISR_RXFF) {
462 /* while there is unread messages */
463 while (!(sys_read8(config->reg_addr + RCAR_CAN_RFCR)
464 & RCAR_CAN_RFCR_RFEST)) {
465 can_rcar_rx_isr(dev);
466 }
467 /* Clear the Rx interrupt */
468 isr = sys_read8(config->reg_addr + RCAR_CAN_ISR);
469 isr &= ~RCAR_CAN_ISR_RXFF;
470 sys_write8(isr, config->reg_addr + RCAR_CAN_ISR);
471 }
472 }
473
can_rcar_leave_sleep_mode(const struct can_rcar_cfg * config)474 static int can_rcar_leave_sleep_mode(const struct can_rcar_cfg *config)
475 {
476 uint16_t ctlr, str;
477 int i;
478
479 ctlr = can_rcar_read16(config, RCAR_CAN_CTLR);
480 ctlr &= ~RCAR_CAN_CTLR_SLPM;
481 can_rcar_write16(config, RCAR_CAN_CTLR, ctlr);
482 for (i = 0; i < MAX_STR_READS; i++) {
483 str = can_rcar_read16(config, RCAR_CAN_STR);
484 if (!(str & RCAR_CAN_STR_SLPST)) {
485 return 0;
486 }
487 }
488 return -EAGAIN;
489 }
490
can_rcar_enter_reset_mode(const struct can_rcar_cfg * config,bool force)491 static int can_rcar_enter_reset_mode(const struct can_rcar_cfg *config, bool force)
492 {
493 uint16_t ctlr;
494 int i;
495
496 ctlr = can_rcar_read16(config, RCAR_CAN_CTLR);
497 ctlr &= ~RCAR_CAN_CTLR_CANM_MASK;
498 ctlr |= RCAR_CAN_CTLR_CANM_RESET;
499 if (force) {
500 ctlr |= RCAR_CAN_CTLR_CANM_HALT;
501 }
502 can_rcar_write16(config, RCAR_CAN_CTLR, ctlr);
503 for (i = 0; i < MAX_STR_READS; i++) {
504 if (can_rcar_read16(config, RCAR_CAN_STR) & RCAR_CAN_STR_RSTST) {
505 return 0;
506 }
507 }
508 return -EAGAIN;
509 }
510
can_rcar_enter_halt_mode(const struct can_rcar_cfg * config)511 static int can_rcar_enter_halt_mode(const struct can_rcar_cfg *config)
512 {
513 uint16_t ctlr;
514 int i;
515
516 ctlr = can_rcar_read16(config, RCAR_CAN_CTLR);
517 ctlr &= ~RCAR_CAN_CTLR_CANM_MASK;
518 ctlr |= RCAR_CAN_CTLR_CANM_HALT;
519 can_rcar_write16(config, RCAR_CAN_CTLR, ctlr);
520
521 /* Wait for controller to apply high bit timing settings */
522 k_usleep(1);
523
524 for (i = 0; i < MAX_STR_READS; i++) {
525 if (can_rcar_read16(config, RCAR_CAN_STR) & RCAR_CAN_STR_HLTST) {
526 return 0;
527 }
528 }
529
530 return -EAGAIN;
531 }
532
can_rcar_enter_operation_mode(const struct can_rcar_cfg * config)533 static int can_rcar_enter_operation_mode(const struct can_rcar_cfg *config)
534 {
535 uint16_t ctlr, str;
536 int i;
537
538 ctlr = can_rcar_read16(config, RCAR_CAN_CTLR);
539 ctlr &= ~RCAR_CAN_CTLR_CANM_MASK;
540 can_rcar_write16(config, RCAR_CAN_CTLR, ctlr);
541
542 /* Wait for controller to apply high bit timing settings */
543 k_usleep(1);
544
545 for (i = 0; i < MAX_STR_READS; i++) {
546 str = can_rcar_read16(config, RCAR_CAN_STR);
547 if (!(str & RCAR_CAN_CTLR_CANM_MASK)) {
548 break;
549 }
550 }
551
552 if (i == MAX_STR_READS) {
553 return -EAGAIN;
554 }
555
556 /* Enable Rx and Tx FIFO */
557 sys_write8(RCAR_CAN_RFCR_RFE, config->reg_addr + RCAR_CAN_RFCR);
558 sys_write8(RCAR_CAN_TFCR_TFE, config->reg_addr + RCAR_CAN_TFCR);
559
560 return 0;
561 }
562
can_rcar_get_capabilities(const struct device * dev,can_mode_t * cap)563 static int can_rcar_get_capabilities(const struct device *dev, can_mode_t *cap)
564 {
565 ARG_UNUSED(dev);
566
567 *cap = CAN_MODE_NORMAL | CAN_MODE_LOOPBACK | CAN_MODE_LISTENONLY;
568
569 return 0;
570 }
571
can_rcar_start(const struct device * dev)572 static int can_rcar_start(const struct device *dev)
573 {
574 const struct can_rcar_cfg *config = dev->config;
575 struct can_rcar_data *data = dev->data;
576 int ret;
577
578 if (data->common.started) {
579 return -EALREADY;
580 }
581
582 if (config->common.phy != NULL) {
583 ret = can_transceiver_enable(config->common.phy, data->common.mode);
584 if (ret != 0) {
585 LOG_ERR("failed to enable CAN transceiver (err %d)", ret);
586 return ret;
587 }
588 }
589
590 k_mutex_lock(&data->inst_mutex, K_FOREVER);
591
592 CAN_STATS_RESET(dev);
593
594 ret = can_rcar_enter_operation_mode(config);
595 if (ret != 0) {
596 LOG_ERR("failed to enter operation mode (err %d)", ret);
597
598 if (config->common.phy != NULL) {
599 /* Attempt to disable the CAN transceiver in case of error */
600 (void)can_transceiver_disable(config->common.phy);
601 }
602 } else {
603 data->common.started = true;
604 }
605
606 k_mutex_unlock(&data->inst_mutex);
607
608 return ret;
609 }
610
can_rcar_stop(const struct device * dev)611 static int can_rcar_stop(const struct device *dev)
612 {
613 const struct can_rcar_cfg *config = dev->config;
614 struct can_rcar_data *data = dev->data;
615 int ret;
616
617 if (!data->common.started) {
618 return -EALREADY;
619 }
620
621 k_mutex_lock(&data->inst_mutex, K_FOREVER);
622
623 ret = can_rcar_enter_halt_mode(config);
624 if (ret != 0) {
625 LOG_ERR("failed to enter halt mode (err %d)", ret);
626 k_mutex_unlock(&data->inst_mutex);
627 return ret;
628 }
629
630 data->common.started = false;
631
632 k_mutex_unlock(&data->inst_mutex);
633
634 if (config->common.phy != NULL) {
635 ret = can_transceiver_disable(config->common.phy);
636 if (ret != 0) {
637 LOG_ERR("failed to disable CAN transceiver (err %d)", ret);
638 return ret;
639 }
640 }
641
642 /* Resetting TX FIFO, emptying it */
643 sys_write8((uint8_t)~RCAR_CAN_TFCR_TFE, config->reg_addr + RCAR_CAN_TFCR);
644 sys_write8(RCAR_CAN_TFCR_TFE, config->reg_addr + RCAR_CAN_TFCR);
645
646 /* Empty TX msgq, returning an error for each message */
647 while (data->tx_unsent) {
648 can_rcar_tx_done(dev, -ENETDOWN);
649 }
650
651 return 0;
652 }
653
can_rcar_set_mode(const struct device * dev,can_mode_t mode)654 static int can_rcar_set_mode(const struct device *dev, can_mode_t mode)
655 {
656 can_mode_t supported = CAN_MODE_LOOPBACK | CAN_MODE_LISTENONLY;
657 const struct can_rcar_cfg *config = dev->config;
658 struct can_rcar_data *data = dev->data;
659 uint8_t tcr = 0;
660 int ret = 0;
661
662 if (IS_ENABLED(CONFIG_CAN_MANUAL_RECOVERY_MODE)) {
663 supported |= CAN_MODE_MANUAL_RECOVERY;
664 }
665
666 if ((mode & ~(supported)) != 0) {
667 LOG_ERR("Unsupported mode: 0x%08x", mode);
668 return -ENOTSUP;
669 }
670
671 if (data->common.started) {
672 return -EBUSY;
673 }
674
675 k_mutex_lock(&data->inst_mutex, K_FOREVER);
676
677 if ((mode & (CAN_MODE_LOOPBACK | CAN_MODE_LISTENONLY)) ==
678 (CAN_MODE_LOOPBACK | CAN_MODE_LISTENONLY)) {
679 LOG_ERR("Combination of loopback and listenonly modes not supported");
680 ret = -ENOTSUP;
681 goto unlock;
682 } else if ((mode & CAN_MODE_LOOPBACK) != 0) {
683 /* Loopback mode */
684 tcr = RCAR_CAN_TCR_INT_LOOP | RCAR_CAN_TCR_TSTE;
685 } else if ((mode & CAN_MODE_LISTENONLY) != 0) {
686 /* Listen-only mode */
687 tcr = RCAR_CAN_TCR_LISTEN_ONLY | RCAR_CAN_TCR_TSTE;
688 } else {
689 /* Normal mode */
690 tcr = 0;
691 }
692
693 sys_write8(tcr, config->reg_addr + RCAR_CAN_TCR);
694
695 if (IS_ENABLED(CONFIG_CAN_MANUAL_RECOVERY_MODE)) {
696 uint16_t ctlr = can_rcar_read16(config, RCAR_CAN_CTLR);
697
698 if ((mode & CAN_MODE_MANUAL_RECOVERY) != 0U) {
699 /* Set entry to halt automatically at bus-off */
700 ctlr |= RCAR_CAN_CTLR_BOM_ENT;
701 } else {
702 /* Clear entry to halt automatically at bus-off */
703 ctlr &= ~RCAR_CAN_CTLR_BOM_ENT;
704 }
705
706 can_rcar_write16(config, RCAR_CAN_CTLR, ctlr);
707 }
708
709 data->common.mode = mode;
710
711 unlock:
712 k_mutex_unlock(&data->inst_mutex);
713
714 return ret;
715 }
716
717 /* Bit Configuration Register settings */
718 #define RCAR_CAN_BCR_TSEG1(x) (((x) & 0x0f) << 20)
719 #define RCAR_CAN_BCR_BPR(x) (((x) & 0x3ff) << 8)
720 #define RCAR_CAN_BCR_SJW(x) (((x) & 0x3) << 4)
721 #define RCAR_CAN_BCR_TSEG2(x) ((x) & 0x07)
722
can_rcar_set_bittiming(const struct can_rcar_cfg * config,const struct can_timing * timing)723 static void can_rcar_set_bittiming(const struct can_rcar_cfg *config,
724 const struct can_timing *timing)
725 {
726 uint32_t bcr;
727
728 bcr = RCAR_CAN_BCR_TSEG1(timing->phase_seg1 + timing->prop_seg - 1) |
729 RCAR_CAN_BCR_BPR(timing->prescaler - 1) |
730 RCAR_CAN_BCR_SJW(timing->sjw - 1) |
731 RCAR_CAN_BCR_TSEG2(timing->phase_seg2 - 1);
732
733 /* Don't overwrite CLKR with 32-bit BCR access; CLKR has 8-bit access.
734 * All the registers are big-endian but they get byte-swapped on 32-bit
735 * read/write (but not on 8-bit, contrary to the manuals)...
736 */
737 sys_write32((bcr << 8) | RCAR_CAN_CLKR_CLKP2,
738 config->reg_addr + RCAR_CAN_BCR);
739 }
740
can_rcar_set_timing(const struct device * dev,const struct can_timing * timing)741 static int can_rcar_set_timing(const struct device *dev,
742 const struct can_timing *timing)
743 {
744 const struct can_rcar_cfg *config = dev->config;
745 struct can_rcar_data *data = dev->data;
746 int ret = 0;
747
748 struct reg_backup {
749 uint32_t address;
750 uint8_t value;
751 };
752
753 struct reg_backup regs[3] = { { RCAR_CAN_TCR, 0 }, { RCAR_CAN_TFCR, 0 }
754 , { RCAR_CAN_RFCR, 0 } };
755
756 if (data->common.started) {
757 return -EBUSY;
758 }
759
760 k_mutex_lock(&data->inst_mutex, K_FOREVER);
761
762 /* Changing bittiming should be done in reset mode.
763 * Switching to reset mode is resetting loopback mode (TCR),
764 * transmit and receive FIFOs (TFCR and RFCR).
765 * Storing these reg values to restore them once back in halt mode.
766 */
767 for (int i = 0; i < 3; i++) {
768 regs[i].value = sys_read8(config->reg_addr + regs[i].address);
769 }
770
771 /* Switching to reset mode */
772 ret = can_rcar_enter_reset_mode(config, true);
773 if (ret != 0) {
774 goto unlock;
775 }
776
777 /* Setting bit timing */
778 can_rcar_set_bittiming(config, timing);
779
780 /* Restoring registers must be done in halt mode */
781 ret = can_rcar_enter_halt_mode(config);
782 if (ret) {
783 goto unlock;
784 }
785
786 /* Restoring registers */
787 for (int i = 0; i < 3; i++) {
788 sys_write8(regs[i].value, config->reg_addr + regs[i].address);
789 }
790
791 unlock:
792 k_mutex_unlock(&data->inst_mutex);
793 return ret;
794 }
795
can_rcar_set_state_change_callback(const struct device * dev,can_state_change_callback_t cb,void * user_data)796 static void can_rcar_set_state_change_callback(const struct device *dev,
797 can_state_change_callback_t cb,
798 void *user_data)
799 {
800 struct can_rcar_data *data = dev->data;
801
802 data->common.state_change_cb = cb;
803 data->common.state_change_cb_user_data = user_data;
804 }
805
can_rcar_get_state(const struct device * dev,enum can_state * state,struct can_bus_err_cnt * err_cnt)806 static int can_rcar_get_state(const struct device *dev, enum can_state *state,
807 struct can_bus_err_cnt *err_cnt)
808 {
809 const struct can_rcar_cfg *config = dev->config;
810 struct can_rcar_data *data = dev->data;
811
812 if (state != NULL) {
813 if (!data->common.started) {
814 *state = CAN_STATE_STOPPED;
815 } else {
816 *state = data->state;
817 }
818 }
819
820 if (err_cnt != NULL) {
821 can_rcar_get_error_count(config, err_cnt);
822 }
823
824 return 0;
825 }
826
827 #ifdef CONFIG_CAN_MANUAL_RECOVERY_MODE
can_rcar_recover(const struct device * dev,k_timeout_t timeout)828 static int can_rcar_recover(const struct device *dev, k_timeout_t timeout)
829 {
830 const struct can_rcar_cfg *config = dev->config;
831 struct can_rcar_data *data = dev->data;
832 int64_t start_time;
833 int ret;
834
835 if (!data->common.started) {
836 return -ENETDOWN;
837 }
838
839 if ((data->common.mode & CAN_MODE_MANUAL_RECOVERY) == 0U) {
840 return -ENOTSUP;
841 }
842
843 if (data->state != CAN_STATE_BUS_OFF) {
844 return 0;
845 }
846
847 if (k_mutex_lock(&data->inst_mutex, K_FOREVER)) {
848 return -EAGAIN;
849 }
850
851 start_time = k_uptime_ticks();
852 while (data->state == CAN_STATE_BUS_OFF) {
853 ret = can_rcar_enter_operation_mode(config);
854 if (ret != 0) {
855 goto done;
856 }
857
858 if (!K_TIMEOUT_EQ(timeout, K_FOREVER) &&
859 k_uptime_ticks() - start_time >= timeout.ticks) {
860 ret = -EAGAIN;
861 goto done;
862 }
863 }
864
865 done:
866 k_mutex_unlock(&data->inst_mutex);
867 return ret;
868 }
869 #endif /* CONFIG_CAN_MANUAL_RECOVERY_MODE */
870
can_rcar_send(const struct device * dev,const struct can_frame * frame,k_timeout_t timeout,can_tx_callback_t callback,void * user_data)871 static int can_rcar_send(const struct device *dev, const struct can_frame *frame,
872 k_timeout_t timeout, can_tx_callback_t callback,
873 void *user_data)
874 {
875 const struct can_rcar_cfg *config = dev->config;
876 struct can_rcar_data *data = dev->data;
877 struct can_rcar_tx_cb *tx_cb;
878 uint32_t identifier;
879 int i;
880
881 LOG_DBG("Sending %d bytes on %s. "
882 "Id: 0x%x, "
883 "ID type: %s, "
884 "Remote Frame: %s"
885 , frame->dlc, dev->name
886 , frame->id
887 , (frame->flags & CAN_FRAME_IDE) != 0 ?
888 "extended" : "standard"
889 , (frame->flags & CAN_FRAME_RTR) != 0 ? "yes" : "no");
890
891 if (frame->dlc > CAN_MAX_DLC) {
892 LOG_ERR("DLC of %d exceeds maximum (%d)",
893 frame->dlc, CAN_MAX_DLC);
894 return -EINVAL;
895 }
896
897 if ((frame->flags & ~(CAN_FRAME_IDE | CAN_FRAME_RTR)) != 0) {
898 LOG_ERR("unsupported CAN frame flags 0x%02x", frame->flags);
899 return -ENOTSUP;
900 }
901
902 if (!data->common.started) {
903 return -ENETDOWN;
904 }
905
906 /* Wait for a slot into the tx FIFO */
907 if (k_sem_take(&data->tx_sem, timeout) != 0) {
908 return -EAGAIN;
909 }
910
911 k_mutex_lock(&data->inst_mutex, K_FOREVER);
912 tx_cb = &data->tx_cb[data->tx_head];
913 tx_cb->cb = callback;
914 tx_cb->cb_arg = user_data;
915
916 data->tx_head++;
917 if (data->tx_head >= RCAR_CAN_FIFO_DEPTH) {
918 data->tx_head = 0;
919 }
920
921 if ((frame->flags & CAN_FRAME_IDE) != 0) {
922 identifier = frame->id | RCAR_CAN_MB_IDE;
923 } else {
924 identifier = frame->id << RCAR_CAN_MB_SID_SHIFT;
925 }
926
927 if ((frame->flags & CAN_FRAME_RTR) != 0) {
928 identifier |= RCAR_CAN_MB_RTR;
929 }
930
931 sys_write32(identifier, config->reg_addr + RCAR_CAN_MB_56);
932
933 sys_write16(frame->dlc, config->reg_addr
934 + RCAR_CAN_MB_56 + RCAR_CAN_MB_DLC_OFFSET);
935
936 if ((frame->flags & CAN_FRAME_RTR) == 0) {
937 for (i = 0; i < frame->dlc; i++) {
938 sys_write8(frame->data[i], config->reg_addr
939 + RCAR_CAN_MB_56 + RCAR_CAN_MB_DATA_OFFSET + i);
940 }
941 }
942
943 compiler_barrier();
944 data->tx_unsent++;
945 /* Start Tx: increment the CPU-side pointer for the transmit FIFO
946 * to the next mailbox location
947 */
948 sys_write8(0xff, config->reg_addr + RCAR_CAN_TFPCR);
949
950 k_mutex_unlock(&data->inst_mutex);
951
952 return 0;
953 }
954
can_rcar_add_rx_filter_unlocked(const struct device * dev,can_rx_callback_t cb,void * cb_arg,const struct can_filter * filter)955 static inline int can_rcar_add_rx_filter_unlocked(const struct device *dev,
956 can_rx_callback_t cb,
957 void *cb_arg,
958 const struct can_filter *filter)
959 {
960 struct can_rcar_data *data = dev->data;
961 int i;
962
963 for (i = 0; i < CONFIG_CAN_RCAR_MAX_FILTER; i++) {
964 if (data->rx_callback[i] == NULL) {
965 data->rx_callback_arg[i] = cb_arg;
966 data->filter[i] = *filter;
967 compiler_barrier();
968 data->rx_callback[i] = cb;
969 return i;
970 }
971 }
972
973 return -ENOSPC;
974 }
975
can_rcar_add_rx_filter(const struct device * dev,can_rx_callback_t cb,void * cb_arg,const struct can_filter * filter)976 static int can_rcar_add_rx_filter(const struct device *dev, can_rx_callback_t cb,
977 void *cb_arg, const struct can_filter *filter)
978 {
979 struct can_rcar_data *data = dev->data;
980 int filter_id;
981
982 if ((filter->flags & ~(CAN_FILTER_IDE)) != 0) {
983 LOG_ERR("unsupported CAN filter flags 0x%02x", filter->flags);
984 return -ENOTSUP;
985 }
986
987 k_mutex_lock(&data->rx_mutex, K_FOREVER);
988 filter_id = can_rcar_add_rx_filter_unlocked(dev, cb, cb_arg, filter);
989 k_mutex_unlock(&data->rx_mutex);
990 return filter_id;
991 }
992
can_rcar_remove_rx_filter(const struct device * dev,int filter_id)993 static void can_rcar_remove_rx_filter(const struct device *dev, int filter_id)
994 {
995 struct can_rcar_data *data = dev->data;
996
997 if (filter_id < 0 || filter_id >= CONFIG_CAN_RCAR_MAX_FILTER) {
998 LOG_ERR("filter ID %d out of bounds", filter_id);
999 return;
1000 }
1001
1002 k_mutex_lock(&data->rx_mutex, K_FOREVER);
1003 compiler_barrier();
1004 data->rx_callback[filter_id] = NULL;
1005 k_mutex_unlock(&data->rx_mutex);
1006 }
1007
can_rcar_init(const struct device * dev)1008 static int can_rcar_init(const struct device *dev)
1009 {
1010 const struct can_rcar_cfg *config = dev->config;
1011 struct can_rcar_data *data = dev->data;
1012 struct can_timing timing = { 0 };
1013 int ret;
1014 uint16_t ctlr;
1015
1016 k_mutex_init(&data->inst_mutex);
1017 k_mutex_init(&data->rx_mutex);
1018 k_sem_init(&data->tx_sem, RCAR_CAN_FIFO_DEPTH, RCAR_CAN_FIFO_DEPTH);
1019
1020 data->tx_head = 0;
1021 data->tx_tail = 0;
1022 data->tx_unsent = 0;
1023
1024 memset(data->rx_callback, 0, sizeof(data->rx_callback));
1025 data->state = CAN_STATE_ERROR_ACTIVE;
1026 data->common.state_change_cb = NULL;
1027 data->common.state_change_cb_user_data = NULL;
1028
1029 if (config->common.phy != NULL) {
1030 if (!device_is_ready(config->common.phy)) {
1031 LOG_ERR("CAN transceiver not ready");
1032 return -ENODEV;
1033 }
1034 }
1035
1036 if (!device_is_ready(config->clock_dev)) {
1037 LOG_ERR("clock control device not ready");
1038 return -ENODEV;
1039 }
1040
1041 /* Configure dt provided device signals when available */
1042 ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
1043 if (ret < 0) {
1044 return ret;
1045 }
1046
1047 /* reset the registers */
1048 ret = clock_control_off(config->clock_dev,
1049 (clock_control_subsys_t)&config->mod_clk);
1050 if (ret < 0) {
1051 return ret;
1052 }
1053
1054 ret = clock_control_on(config->clock_dev,
1055 (clock_control_subsys_t)&config->mod_clk);
1056 if (ret < 0) {
1057 return ret;
1058 }
1059
1060 ret = clock_control_on(config->clock_dev,
1061 (clock_control_subsys_t)&config->bus_clk);
1062 if (ret < 0) {
1063 return ret;
1064 }
1065
1066 ret = can_rcar_enter_reset_mode(config, false);
1067 __ASSERT(!ret, "Fail to set CAN controller to reset mode");
1068 if (ret) {
1069 return ret;
1070 }
1071
1072 ret = can_rcar_leave_sleep_mode(config);
1073 __ASSERT(!ret, "Fail to leave CAN controller from sleep mode");
1074 if (ret) {
1075 return ret;
1076 }
1077
1078 ret = can_calc_timing(dev, &timing, config->common.bitrate,
1079 config->common.sample_point);
1080 if (ret == -EINVAL) {
1081 LOG_ERR("Can't find timing for given param");
1082 return -EIO;
1083 }
1084
1085 LOG_DBG("Presc: %d, TS1: %d, TS2: %d",
1086 timing.prescaler, timing.phase_seg1, timing.phase_seg2);
1087 LOG_DBG("Sample-point err : %d", ret);
1088
1089 ret = can_set_timing(dev, &timing);
1090 if (ret) {
1091 return ret;
1092 }
1093
1094 ret = can_rcar_set_mode(dev, CAN_MODE_NORMAL);
1095 if (ret) {
1096 return ret;
1097 }
1098
1099 ctlr = can_rcar_read16(config, RCAR_CAN_CTLR);
1100 ctlr |= RCAR_CAN_CTLR_IDFM_MIXED; /* Select mixed ID mode */
1101 ctlr &= ~RCAR_CAN_CTLR_BOM_ENT; /* Clear entry to halt automatically at bus-off */
1102 ctlr |= RCAR_CAN_CTLR_MBM; /* Select FIFO mailbox mode */
1103 ctlr |= RCAR_CAN_CTLR_MLM; /* Overrun mode */
1104 ctlr &= ~RCAR_CAN_CTLR_SLPM; /* Clear CAN Sleep mode */
1105 can_rcar_write16(config, RCAR_CAN_CTLR, ctlr);
1106
1107 /* Accept all SID and EID */
1108 sys_write32(0, config->reg_addr + RCAR_CAN_MKR8);
1109 sys_write32(0, config->reg_addr + RCAR_CAN_MKR9);
1110 /* In FIFO mailbox mode, write "0" to bits 24 to 31 */
1111 sys_write32(0, config->reg_addr + RCAR_CAN_MKIVLR0);
1112 sys_write32(0, config->reg_addr + RCAR_CAN_MKIVLR1);
1113 /* Accept standard and extended ID frames, but not
1114 * remote frame.
1115 */
1116 sys_write32(0, config->reg_addr + RCAR_CAN_FIDCR0);
1117 sys_write32(RCAR_CAN_FIDCR_IDE,
1118 config->reg_addr + RCAR_CAN_FIDCR1);
1119
1120 /* Enable and configure FIFO mailbox interrupts Rx and Tx */
1121 sys_write32(RCAR_CAN_MIER1_RXFIE | RCAR_CAN_MIER1_TXFIE,
1122 config->reg_addr + RCAR_CAN_MIER1);
1123
1124 sys_write8(RCAR_CAN_IER_ERSIE | RCAR_CAN_IER_RXFIE | RCAR_CAN_IER_TXFIE,
1125 config->reg_addr + RCAR_CAN_IER);
1126
1127 /* Accumulate error codes */
1128 sys_write8(RCAR_CAN_ECSR_EDPM, config->reg_addr + RCAR_CAN_ECSR);
1129
1130 /* Enable interrupts for all type of errors */
1131 sys_write8(0xFF, config->reg_addr + RCAR_CAN_EIER);
1132
1133 config->init_func(dev);
1134
1135 return 0;
1136 }
1137
can_rcar_get_core_clock(const struct device * dev,uint32_t * rate)1138 static int can_rcar_get_core_clock(const struct device *dev, uint32_t *rate)
1139 {
1140 const struct can_rcar_cfg *config = dev->config;
1141
1142 *rate = config->bus_clk.rate;
1143 return 0;
1144 }
1145
can_rcar_get_max_filters(const struct device * dev,bool ide)1146 static int can_rcar_get_max_filters(const struct device *dev, bool ide)
1147 {
1148 ARG_UNUSED(ide);
1149
1150 return CONFIG_CAN_RCAR_MAX_FILTER;
1151 }
1152
1153 static DEVICE_API(can, can_rcar_driver_api) = {
1154 .get_capabilities = can_rcar_get_capabilities,
1155 .start = can_rcar_start,
1156 .stop = can_rcar_stop,
1157 .set_mode = can_rcar_set_mode,
1158 .set_timing = can_rcar_set_timing,
1159 .send = can_rcar_send,
1160 .add_rx_filter = can_rcar_add_rx_filter,
1161 .remove_rx_filter = can_rcar_remove_rx_filter,
1162 .get_state = can_rcar_get_state,
1163 #ifdef CONFIG_CAN_MANUAL_RECOVERY_MODE
1164 .recover = can_rcar_recover,
1165 #endif /* CONFIG_CAN_MANUAL_RECOVERY_MODE */
1166 .set_state_change_callback = can_rcar_set_state_change_callback,
1167 .get_core_clock = can_rcar_get_core_clock,
1168 .get_max_filters = can_rcar_get_max_filters,
1169 .timing_min = {
1170 .sjw = 0x1,
1171 .prop_seg = 0x00,
1172 .phase_seg1 = 0x04,
1173 .phase_seg2 = 0x02,
1174 .prescaler = 0x01
1175 },
1176 .timing_max = {
1177 .sjw = 0x4,
1178 .prop_seg = 0x00,
1179 .phase_seg1 = 0x10,
1180 .phase_seg2 = 0x08,
1181 .prescaler = 0x400
1182 }
1183 };
1184
1185 /* Device Instantiation */
1186 #define CAN_RCAR_INIT(n) \
1187 PINCTRL_DT_INST_DEFINE(n); \
1188 static void can_rcar_##n##_init(const struct device *dev); \
1189 static const struct can_rcar_cfg can_rcar_cfg_##n = { \
1190 .common = CAN_DT_DRIVER_CONFIG_INST_GET(n, 0, 1000000), \
1191 .reg_addr = DT_INST_REG_ADDR(n), \
1192 .reg_size = DT_INST_REG_SIZE(n), \
1193 .init_func = can_rcar_##n##_init, \
1194 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
1195 .mod_clk.module = \
1196 DT_INST_CLOCKS_CELL_BY_IDX(n, 0, module), \
1197 .mod_clk.domain = \
1198 DT_INST_CLOCKS_CELL_BY_IDX(n, 0, domain), \
1199 .bus_clk.module = \
1200 DT_INST_CLOCKS_CELL_BY_IDX(n, 1, module), \
1201 .bus_clk.domain = \
1202 DT_INST_CLOCKS_CELL_BY_IDX(n, 1, domain), \
1203 .bus_clk.rate = 40000000, \
1204 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
1205 }; \
1206 static struct can_rcar_data can_rcar_data_##n; \
1207 \
1208 CAN_DEVICE_DT_INST_DEFINE(n, can_rcar_init, \
1209 NULL, \
1210 &can_rcar_data_##n, \
1211 &can_rcar_cfg_##n, \
1212 POST_KERNEL, \
1213 CONFIG_CAN_INIT_PRIORITY, \
1214 &can_rcar_driver_api \
1215 ); \
1216 static void can_rcar_##n##_init(const struct device *dev) \
1217 { \
1218 IRQ_CONNECT(DT_INST_IRQN(n), \
1219 0, \
1220 can_rcar_isr, \
1221 DEVICE_DT_INST_GET(n), 0); \
1222 \
1223 irq_enable(DT_INST_IRQN(n)); \
1224 }
1225
1226 DT_INST_FOREACH_STATUS_OKAY(CAN_RCAR_INIT)
1227
