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/Zephyr-latest/drivers/memc/
DKconfig1 # Memory controller configuration options
4 # SPDX-License-Identifier: Apache-2.0
7 bool "Memory controller drivers [EXPERIMENTAL]"
10 Add support for memory controllers
19 Memory controllers initialization priority.
21 source "drivers/memc/Kconfig.stm32"
23 source "drivers/memc/Kconfig.mcux"
25 source "drivers/memc/Kconfig.sam"
27 source "drivers/memc/Kconfig.sifive"
29 source "drivers/memc/Kconfig.nxp_s32"
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/Zephyr-latest/drivers/usb/udc/
DKconfig1 # Copyright (c) 2021-2022 Nordic Semiconductor ASA
2 # SPDX-License-Identifier: Apache-2.0
22 int "Memory available for requests"
26 Total amount of memory available for UDC requests.
29 bool "Place the buffer pools in the nocache memory region"
32 Place the buffer pools in the nocache memory region if the driver
33 cannot handle buffers in cached memory.
54 module-str = usb drv
55 source "subsys/logging/Kconfig.template.log_config"
57 source "drivers/usb/udc/Kconfig.dwc2"
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/Zephyr-latest/drivers/retained_mem/
DKconfig2 # SPDX-License-Identifier: Apache-2.0
5 bool "Retained memory drivers"
13 int "Retained memory devices init priority"
16 Retained memory devices initialization priority,
25 bool "Disable retained memory mutex support"
29 memory access. This option should only be enabled when retained
30 memory access is required in an ISR or for special use cases.
33 module-str = retained_mem
34 source "subsys/logging/Kconfig.template.log_config"
36 source "drivers/retained_mem/Kconfig.nrf"
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/Zephyr-latest/subsys/bindesc/
DKconfig2 # SPDX-License-Identifier: Apache-2.0
8 Binary Descriptors - constant data accessible outside of the executable image
19 source "subsys/bindesc/Kconfig.version"
20 source "subsys/bindesc/Kconfig.build_time"
21 source "subsys/bindesc/Kconfig.host_info"
42 module-str = Binary Descriptor read
43 source "subsys/logging/Kconfig.template.log_config"
51 bool "Bindesc read from memory mapped flash"
53 Enable reading and parsing binary descriptors from memory mapped flash.
58 Enable reading and parsing binary descriptors from non memory mapped flash
/Zephyr-latest/drivers/usb/uhc/
DKconfig2 # SPDX-License-Identifier: Apache-2.0
29 int "Memory available for buffers"
33 Total amount of memory available for UHC buffers.
36 module-str = uhc drv
37 source "subsys/logging/Kconfig.template.log_config"
39 source "drivers/usb/uhc/Kconfig.max3421e"
40 source "drivers/usb/uhc/Kconfig.virtual"
/Zephyr-latest/dts/arm/adi/max32/
Dmax32666.dtsi2 * Copyright (c) 2023-2024 Analog Devices, Inc.
4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
11 clock-frequency = <DT_FREQ_M(96)>;
15 /delete-property/ clock-source;
19 /delete-property/ clock-source;
23 /delete-property/ clock-source;
29 sram1: memory@20008000 {
30 compatible = "mmio-sram";
34 sram2: memory@20010000 {
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Dmax32670.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/dma/max32670_dma.h>
20 clock-frequency = <DT_FREQ_K(80)>;
26 sram1: memory@20004000 {
27 compatible = "mmio-sram";
31 sram2: memory@20008000 {
32 compatible = "mmio-sram";
36 sram3: memory@20010000 {
37 compatible = "mmio-sram";
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Dmax32672.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/dma/max32672_dma.h>
16 clock-frequency = <DT_FREQ_K(80)>;
23 /delete-node/ &clk_iso;
26 compatible = "adi,max32-adc-sar", "adi,max32-adc";
27 clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
28 clock-divider = <16>;
29 channel-count = <16>;
30 track-count = <4>;
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Dmax78002.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/dma/max78002_dma.h>
12 clock-frequency = <DT_FREQ_M(120)>;
16 clock-frequency = <DT_FREQ_K(30)>;
19 /delete-node/ &clk_erfo;
25 compatible = "fixed-clock";
26 #clock-cells = <0>;
27 clock-frequency = <DT_FREQ_M(100)>;
32 compatible = "fixed-clock";
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Dmax32690.dtsi2 * Copyright (c) 2023-2024 Analog Devices, Inc.
4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/dma/max32690_dma.h>
12 clock-frequency = <DT_FREQ_M(120)>;
21 erase-block-size = <16384>;
29 compatible = "adi,max32-gpio";
30 gpio-controller;
31 #gpio-cells = <2>;
39 compatible = "adi,max32-gpio";
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/Zephyr-latest/tests/drivers/display/display_read_write/
DKconfig2 # SPDX-License-Identifier: Apache-2.0
6 source "Kconfig.zephyr"
9 bool "Place the display buffer in a specific memory section"
11 Place the display buffer in a specific memory section.
14 int "Display buffer memory alignment"
22 string "Memory section to place Display Buffer"
24 Specific memory section to place the display buffer.
/Zephyr-latest/drivers/mipi_dsi/
DKconfig1 # Memory controller configuration options
4 # SPDX-License-Identifier: Apache-2.0
7 bool "MIPI-DSI Host Controller drivers [EXPERIMENTAL]"
10 Add support for MIPI-DSI host controllers
15 module-str = mipi_dsi
16 source "subsys/logging/Kconfig.template.log_config"
22 MIPI-DSI Host Controllers initialization priority.
24 source "drivers/mipi_dsi/Kconfig.mcux"
25 source "drivers/mipi_dsi/Kconfig.stm32"
26 source "drivers/mipi_dsi/Kconfig.test"
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/Zephyr-latest/dts/bindings/riscv/
Dnordic,nrf-vpr-coprocessor.yaml2 # SPDX-License-Identifier: Apache-2.0
4 compatible: "nordic,nrf-vpr-coprocessor"
9 VPR is a RISC-V CPU implementation. VPR instances are exposed to other CPUs as
15 execution-memory:
19 Memory area from which the VPR core will execute.
21 source-memory:
24 Memory area or partition from which the VPR code will be loaded.
/Zephyr-latest/drivers/flash/
DKconfig4 # SPDX-License-Identifier: Apache-2.0
23 Device does not do erase-on-write (erase-on-program, auto-erase
26 some other value, as program can only change bits from erased-value
29 been separated from write, EEPROM has erase-on-write, giving
31 Note that explicit-erase capability does not warrants that
42 optimized-out by compiler in case where there is no such device in
51 Note that the device may have erase-on-write (auto-erase),
62 such devices, and could be optimized-out by compiler in
74 retrieving the layout of flash memory pages.
79 Selected by drivers that support JESD216-compatible flash
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/Zephyr-latest/dts/arm/nxp/
Dnxp_lpc55S1x_common.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv8-m.dtsi>
8 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
13 #include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h>
17 #address-cells = <1>;
18 #size-cells = <0>;
21 compatible = "arm,cortex-m33f";
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/Zephyr-latest/subsys/canbus/isotp/
DKconfig1 # ISO-TP configuration options
4 # SPDX-License-Identifier: Apache-2.0
7 bool "ISO-TP Transport [EXPERIMENTAL]"
18 module-str = ISOTP
19 source "subsys/logging/Kconfig.template.log_config"
34 Timeout for the reception of the next FC frame. ISO 15765-2: 1000ms
42 ISO 15765-2: 1000ms
50 ISO 15765-2: 1000ms
83 CAN_MAX_DLEN - 1 (for classic CAN : 8 - 1 = 7, for CAN FD : 64 - 1 = 63).
92 Each buffer will occupy CAN_MAX_DLEN - 1 byte + header (sizeof(struct net_buf))
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/Zephyr-latest/tests/boards/nrf/nrf70/bustest/
DKconfig4 # SPDX-License-Identifier: Apache-2.0
6 source "Kconfig.zephyr"
11 int "Memory test length"
14 This option sets the default length for the memory test.
/Zephyr-latest/boards/nxp/lpcxpresso11u68/support/
Dopenocd.cfg5 # https://www.embeddedartists.com/products/lpc11u68-lpcxpresso/
9 # The on-board LPC-Link2 debug probe (based on a NXP LPC43xx MCU) provides
10 # either a CMSIS-DAP or a J-Link interface. It depends on the version of the
12 source [find interface/cmsis-dap.cfg]
13 # source [find interface/jlink.cfg]
15 # NXP LPC11U68 Cortex-M0 with 256kB flash and 32kB + 4kB SRAM.
18 source [find target/lpc11xx.cfg]
20 # This ensures that the interrupt vectors (0x0000-0x0200) are re-mapped to
24 # Table 8. System memory remap register (SYSMEMREMAP, address 0x40048000) bit
27 # 1:0 MAP System memory remap
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/Zephyr-latest/snippets/nordic-flpr-xip/soc/
Dnrf54h20_cpuapp.overlay3 * SPDX-License-Identifier: Apache-2.0
7 execution-memory = <&cpuflpr_code_partition>;
8 /delete-property/ source-memory;
13 interrupt-parent = <&cpuflpr_clic>;
/Zephyr-latest/snippets/nordic-ppr-xip/soc/
Dnrf54h20_cpuapp.overlay3 * SPDX-License-Identifier: Apache-2.0
11 execution-memory = <&cpuppr_code_partition>;
12 /delete-property/ source-memory;
Dnrf9280_cpuapp.overlay3 * SPDX-License-Identifier: Apache-2.0
11 execution-memory = <&cpuppr_code_partition>;
12 /delete-property/ source-memory;
/Zephyr-latest/include/zephyr/arch/x86/
Dmemmap.h3 * SPDX-License-Identifier: Apache-2.0
12 * The "source" of the memory map refers to where we got the data to fill in
14 * numerically HIGHEST source wins, a manually-provided map being the "best".
27 * For simplicity, we maintain a fixed-sized array of memory regions.
29 * We don't only track available RAM -- we track unavailable regions, too:
39 * that partially-initialized arrays behave as expected.
46 X86_MEMMAP_ENTRY_DEFECTIVE, /* bad memory modules */
59 * We keep track of kernel memory areas (text, data, etc.) in a table for
/Zephyr-latest/drivers/dma/
DKconfig4 # SPDX-License-Identifier: Apache-2.0
10 bool "Direct Memory Access (DMA) drivers"
16 When this option is true, 64 bit source and dest
26 module-str = dma
27 source "subsys/logging/Kconfig.template.log_config"
29 source "drivers/dma/Kconfig.stm32"
31 source "drivers/dma/Kconfig.sam_xdmac"
33 source "drivers/dma/Kconfig.dw"
35 source "drivers/dma/Kconfig.nios2_msgdma"
37 source "drivers/dma/Kconfig.sam0"
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/Zephyr-latest/snippets/nordic-flpr/soc/
Dnrf54l15_cpuapp.overlay3 * SPDX-License-Identifier: Apache-2.0
8 reserved-memory {
9 #address-cells = <1>;
10 #size-cells = <1>;
17 cpuflpr_sram_code_data: memory@20028000 {
18 compatible = "mmio-sram";
20 #address-cells = <1>;
21 #size-cells = <1>;
37 execution-memory = <&cpuflpr_sram_code_data>;
38 source-memory = <&cpuflpr_code_partition>;
/Zephyr-latest/boards/seagate/faze/support/
Dopenocd.cfg5 # An external debug probe must be connected to the SWD port (4-pins J2 header).
6 # Here we assume that a ST-LINK in-circuit debugger/programmer is used. You may
8 source [find interface/stlink.cfg]
10 # NXP LPC11U24 Cortex-M0 with 128KB Flash and 20KB + 4KB SRAM
15 source [find target/lpc11xx.cfg]
17 # This ensures that the interrupt vectors (0x0000-0x0200) are re-mapped to
21 # Table 8. System memory remap register (SYSMEMREMAP, address 0x40048000) bit
24 # 1:0 MAP System memory remap
25 # 0x0 Boot Loader Mode. Interrupt vectors are re-mapped to
27 # 0x1 User RAM Mode. Interrupt vectors are re-mapped to
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