1/*
2 * Copyright (c) 2023-2024 Analog Devices, Inc.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <arm/armv7-m.dtsi>
8#include <adi/max32/max32xxx.dtsi>
9
10&clk_ipo {
11	clock-frequency = <DT_FREQ_M(96)>;
12};
13
14&uart0 {
15	/delete-property/ clock-source;
16};
17
18&uart1 {
19	/delete-property/ clock-source;
20};
21
22&uart2 {
23	/delete-property/ clock-source;
24};
25
26/* MAX32666 extra peripherals. */
27/ {
28	soc {
29		sram1: memory@20008000 {
30			compatible = "mmio-sram";
31			reg = <0x20008000 DT_SIZE_K(32)>;
32		};
33
34		sram2: memory@20010000 {
35			compatible = "mmio-sram";
36			reg = <0x20010000 DT_SIZE_K(64)>;
37		};
38
39		sram3: memory@20020000 {
40			compatible = "mmio-sram";
41			reg = <0x20020000 DT_SIZE_K(64)>;
42		};
43
44		sram4: memory@20030000 {
45			compatible = "mmio-sram";
46			reg = <0x20030000 DT_SIZE_K(128)>;
47		};
48
49		sram5: memory@20050000 {
50			compatible = "mmio-sram";
51			reg = <0x20050000 DT_SIZE_K(128)>;
52		};
53
54		sram6: memory@20070000 {
55			compatible = "mmio-sram";
56			reg = <0x20070000 DT_SIZE_K(8)>;
57		};
58
59		sram7: memory@20072000 {
60			compatible = "mmio-sram";
61			reg = <0x20072000 DT_SIZE_K(8)>;
62		};
63
64		sram8: memory@20074000 {
65			compatible = "mmio-sram";
66			reg = <0x20074000 DT_SIZE_K(16)>;
67		};
68
69		sram9: memory@20078000 {
70			compatible = "mmio-sram";
71			reg = <0x20078000 DT_SIZE_K(16)>;
72		};
73
74		sram10: memory@2007c000 {
75			compatible = "mmio-sram";
76			reg = <0x2007c000 DT_SIZE_K(32)>;
77		};
78
79		sram11: memory@20084000 {
80			compatible = "mmio-sram";
81			reg = <0x20084000 DT_SIZE_K(32)>;
82		};
83
84		flc1: flash_controller@40029400 {
85			compatible = "adi,max32-flash-controller";
86			reg = <0x40029400 0x400>;
87
88			#address-cells = <1>;
89			#size-cells = <1>;
90			status = "okay";
91
92			flash1: flash@10080000 {
93				compatible = "soc-nv-flash";
94				reg = <0x10080000 DT_SIZE_K(512)>;
95				write-block-size = <16>;
96				erase-block-size = <8192>;
97			};
98		};
99
100		dma0: dma@40028000 {
101			compatible = "adi,max32-dma";
102			reg = <0x40028000 0x1000>;
103			clocks = <&gcr ADI_MAX32_CLOCK_BUS0 5>;
104			interrupts = <28 0>, <29 0>, <30 0>, <31 0>, <68 0>, <69 0>, <70 0>, <71 0>;
105			dma-channels = <8>;
106			status = "disabled";
107			#dma-cells = <2>;
108		};
109
110		dma1: dma@40035000 {
111			compatible = "adi,max32-dma";
112			reg = <0x40035000 0x1000>;
113			clocks = <&gcr ADI_MAX32_CLOCK_BUS1 21>;
114			interrupts = <72 0>, <73 0>, <74 0>, <75 0>, <76 0>, <77 0>, <78 0>, <79 0>;
115			dma-channels = <8>;
116			status = "disabled";
117			#dma-cells = <2>;
118		};
119
120		spi0: spi@400be000 {
121			compatible = "adi,max32-spi";
122			reg = <0x400be000 0x1000>;
123			#address-cells = <1>;
124			#size-cells = <0>;
125			clocks = <&gcr ADI_MAX32_CLOCK_BUS1 14>;
126			interrupts = <56 0>;
127			status = "disabled";
128		};
129
130		spi1: spi@40046000 {
131			compatible = "adi,max32-spi";
132			reg = <0x40046000 0x1000>;
133			#address-cells = <1>;
134			#size-cells = <0>;
135			clocks = <&gcr ADI_MAX32_CLOCK_BUS0 6>;
136			interrupts = <16 0>;
137			status = "disabled";
138		};
139
140		spi2: spi@40047000 {
141			compatible = "adi,max32-spi";
142			reg = <0x40047000 0x1000>;
143			#address-cells = <1>;
144			#size-cells = <0>;
145			clocks = <&gcr ADI_MAX32_CLOCK_BUS0 7>;
146			interrupts = <17 0>;
147			status = "disabled";
148		};
149
150		timer4: timer@40014000 {
151			compatible = "adi,max32-timer";
152			reg = <0x40014000 0x1000>;
153			interrupts = <9 0>;
154			status = "disabled";
155			clocks = <&gcr ADI_MAX32_CLOCK_BUS0 19>;
156			clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
157			prescaler = <1>;
158		};
159
160		timer5: timer@40015000 {
161			compatible = "adi,max32-timer";
162			reg = <0x40015000 0x1000>;
163			interrupts = <10 0>;
164			status = "disabled";
165			clocks = <&gcr ADI_MAX32_CLOCK_BUS0 20>;
166			clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
167			prescaler = <1>;
168		};
169
170		w1: w1@4003d000 {
171			compatible = "adi,max32-w1";
172			reg = <0x4003d000 0x1000>;
173			clocks = <&gcr ADI_MAX32_CLOCK_BUS1 13>;
174			interrupts = <67 0>;
175			status = "disabled";
176		};
177	};
178};
179