1/*
2 * Copyright (c) 2024 Nordic Semiconductor
3 * SPDX-License-Identifier: Apache-2.0
4 */
5
6/ {
7	soc {
8		reserved-memory {
9			#address-cells = <1>;
10			#size-cells = <1>;
11			cpuflpr_code_partition: image@165000 {
12				/* FLPR core code partition */
13				reg = <0x165000 DT_SIZE_K(96)>;
14			};
15		};
16
17		cpuflpr_sram_code_data: memory@20028000 {
18			compatible = "mmio-sram";
19			reg = <0x20028000 DT_SIZE_K(96)>;
20			#address-cells = <1>;
21			#size-cells = <1>;
22			ranges = <0x0 0x20028000 0x18000>;
23		};
24	};
25};
26
27&uart30 {
28	status = "reserved";
29};
30
31&cpuapp_sram {
32	reg = <0x20000000 DT_SIZE_K(160)>;
33	ranges = <0x0 0x20000000 0x28000>;
34};
35
36&cpuflpr_vpr {
37	execution-memory = <&cpuflpr_sram_code_data>;
38	source-memory = <&cpuflpr_code_partition>;
39};
40
41&cpuapp_vevif_tx {
42	status = "okay";
43};
44