Lines Matching +full:source +full:- +full:memory

4  * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/dma/max32672_dma.h>
16 	clock-frequency = <DT_FREQ_K(80)>;
23 /delete-node/ &clk_iso;
26 	compatible = "adi,max32-adc-sar", "adi,max32-adc";
27 	clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
28 	clock-divider = <16>;
29 	channel-count = <16>;
30 	track-count = <4>;
31 	idle-count = <0>;
32 	vref-mv = <1250>;
39 		sram1: memory@20004000 {
40 			compatible = "mmio-sram";
44 		sram2: memory@20008000 {
45 			compatible = "mmio-sram";
49 		sram3: memory@20018000 {
50 			compatible = "mmio-sram";
54 		sram4: memory@20028000 {
55 			compatible = "mmio-sram";
59 		sram5: memory@20029000 {
60 			compatible = "mmio-sram";
64 		sram6: memory@2002a000 {
65 			compatible = "mmio-sram";
69 		sram7: memory@2002e000 {
70 			compatible = "mmio-sram";
75 			compatible = "adi,max32-flash-controller";
78 			#address-cells = <1>;
79 			#size-cells = <1>;
83 				compatible = "soc-nv-flash";
85 				write-block-size = <16>;
86 				erase-block-size = <8192>;
91 			compatible = "adi,max32-uart";
94 			clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
100 			compatible = "adi,max32-dma";
105 			dma-channels = <12>;
107 			#dma-cells = <2>;
111 			compatible = "adi,max32-watchdog";
115 			clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
120 			compatible = "adi,max32-spi";
122 			#address-cells = <1>;
123 			#size-cells = <0>;
130 			compatible = "adi,max32-spi";
132 			#address-cells = <1>;
133 			#size-cells = <0>;
140 			compatible = "adi,max32-spi";
142 			#address-cells = <1>;
143 			#size-cells = <0>;
150 			compatible = "adi,max32-timer";
155 			clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
158 				compatible = "adi,max32-counter";
164 			compatible = "adi,max32-timer";
169 			clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
172 				compatible = "adi,max32-counter";