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/Zephyr-latest/boards/pjrc/teensy4/
Dteensy4-pinctrl.dtsi4 * SPDX-License-Identifier: Apache-2.0
10 #include <nxp/nxp_imx/rt/mimxrt1062dvl6a-pinctrl.dtsi>
17 bias-disable;
18 drive-strength = "r0-6";
19 slew-rate = "slow";
20 nxp,speed = "100-mhz";
21 input-enable;
31 drive-strength = "r0-5";
32 bias-pull-up;
33 bias-pull-up-value = "100k";
[all …]
/Zephyr-latest/boards/nxp/mimxrt1015_evk/
Dmimxrt1015_evk-pinctrl.dtsi3 * SPDX-License-Identifier: Apache-2.0
9 #include <nxp/nxp_imx/rt/mimxrt1015daf5a-pinctrl.dtsi>
17 drive-strength = "r0-6";
18 slew-rate = "slow";
19 nxp,speed = "100-mhz";
27 drive-strength = "r0-6";
28 drive-open-drain;
29 slew-rate = "slow";
30 nxp,speed = "100-mhz";
31 input-enable;
[all …]
/Zephyr-latest/boards/nxp/mimxrt1064_evk/
Dmimxrt1064_evk-pinctrl.dtsi3 * SPDX-License-Identifier: Apache-2.0
9 #include <nxp/nxp_imx/rt/mimxrt1064dvl6a-pinctrl.dtsi>
17 bias-disable;
18 drive-strength = "r0-6";
19 slew-rate = "slow";
20 nxp,speed = "100-mhz";
28 drive-strength = "r0-6";
29 bias-pull-down;
30 bias-pull-down-value = "100k";
31 slew-rate = "slow";
[all …]
/Zephyr-latest/boards/nxp/mimxrt1024_evk/
Dmimxrt1024_evk-pinctrl.dtsi3 * SPDX-License-Identifier: Apache-2.0
9 #include <nxp/nxp_imx/rt/mimxrt1024dag5a-pinctrl.dtsi>
17 drive-strength = "r0-6";
18 slew-rate = "slow";
19 nxp,speed = "100-mhz";
26 bias-disable;
27 drive-strength = "r0-6";
28 slew-rate = "fast";
29 nxp,speed = "50-mhz";
30 input-enable;
[all …]
/Zephyr-latest/boards/nxp/mimxrt1020_evk/
Dmimxrt1020_evk-pinctrl.dtsi3 * SPDX-License-Identifier: Apache-2.0
9 #include <nxp/nxp_imx/rt/mimxrt1021dag5a-pinctrl.dtsi>
17 drive-strength = "r0-6";
18 slew-rate = "slow";
19 nxp,speed = "100-mhz";
27 bias-disable;
28 drive-strength = "r0-6";
29 slew-rate = "fast";
30 nxp,speed = "50-mhz";
31 input-enable;
[all …]
/Zephyr-latest/boards/nxp/mimxrt1050_evk/
Dmimxrt1050_evk-pinctrl.dtsi3 * SPDX-License-Identifier: Apache-2.0
9 #include <nxp/nxp_imx/rt/mimxrt1052dvl6b-pinctrl.dtsi>
17 bias-disable;
18 drive-strength = "r0-6";
19 slew-rate = "slow";
20 nxp,speed = "100-mhz";
28 drive-strength = "r0-6";
29 bias-pull-down;
30 bias-pull-down-value = "100k";
31 slew-rate = "slow";
[all …]
/Zephyr-latest/boards/nxp/mimxrt1062_fmurt6/
Dmimxrt1062_fmurt6-pinctrl.dtsi2 * SPDX-License-Identifier: Apache-2.0
7 #include <nxp/nxp_imx/rt/mimxrt1062dvl6a-pinctrl.dtsi>
16 bias-disable;
17 drive-strength = "r0-6";
18 slew-rate = "slow";
19 nxp,speed = "100-mhz";
26 drive-strength = "r0-6";
27 slew-rate = "fast";
28 nxp,speed = "50-mhz";
29 bias-pull-down-value = "100k";
[all …]
/Zephyr-latest/boards/nxp/mimxrt1060_evk/
Dmimxrt1060_evk-pinctrl.dtsi3 * SPDX-License-Identifier: Apache-2.0
9 #include <nxp/nxp_imx/rt/mimxrt1062dvl6a-pinctrl.dtsi>
17 bias-disable;
18 drive-strength = "r0-6";
19 slew-rate = "slow";
20 nxp,speed = "100-mhz";
28 drive-strength = "r0-6";
29 bias-pull-down;
30 bias-pull-down-value = "100k";
31 slew-rate = "slow";
[all …]
/Zephyr-latest/boards/nxp/mimxrt1040_evk/
Dmimxrt1040_evk-pinctrl.dtsi3 * SPDX-License-Identifier: Apache-2.0
9 #include <nxp/nxp_imx/rt/mimxrt1042xjm5b-pinctrl.dtsi>
17 drive-strength = "r0-6";
18 slew-rate = "slow";
19 nxp,speed = "100-mhz";
23 /* Route PWM1 A3 to J16, pin 6 on arduino header */
27 drive-strength = "r0-6";
28 slew-rate = "fast";
29 nxp,speed = "100-mhz";
38 drive-strength = "r0-6";
[all …]
/Zephyr-latest/boards/madmachine/mm_swiftio/
Dmm_swiftio-pinctrl.dtsi3 * SPDX-License-Identifier: Apache-2.0
9 #include <nxp/nxp_imx/rt/mimxrt1052dvl6b-pinctrl.dtsi>
26 drive-strength = "r0-6";
27 slew-rate = "slow";
28 nxp,speed = "100-mhz";
36 drive-strength = "r0-6";
37 drive-open-drain;
38 slew-rate = "slow";
39 nxp,speed = "100-mhz";
40 input-enable;
[all …]
/Zephyr-latest/boards/madmachine/mm_feather/
Dmm_feather-pinctrl.dtsi3 * SPDX-License-Identifier: Apache-2.0
9 #include <nxp/nxp_imx/rt/mimxrt1062dvl6a-pinctrl.dtsi>
16 drive-strength = "r0-6";
17 drive-open-drain;
18 slew-rate = "slow";
19 nxp,speed = "100-mhz";
20 input-enable;
28 drive-strength = "r0-6";
29 drive-open-drain;
30 slew-rate = "slow";
[all …]
/Zephyr-latest/soc/ti/lm3s6965/
Dreboot.S2 * Copyright (c) 2013-2014 Wind River Systems, Inc.
4 * SPDX-License-Identifier: Apache-2.0
19 eors r0, r0
23 str r0, [r1, #0xd08] /* VTOR */
25 ldr r0, [r0, #4]
26 bx r0
32 ldr r0, =_SCS_ICSR_RETTOBASE
35 ands.w r0, r1
38 * If Z flag is set, we are nested, so un-nest one level and get
52 str r2, [ip, #(6 * 4)]
/Zephyr-latest/dts/bindings/pinctrl/
Dnxp,mcux-rt-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
15 drive-strength = "r0-6";
16 slew-rate = "slow";
17 nxp,speed = "100-mhz";
21 Both pins will be configured with a weak latch, drive strength of "r0-6",
26 input-schmitt-enable: HYS=1
27 drive-open-drain: ODE=1
28 input-enable: SION=1 (in SW_MUX_CTL_PAD register)
29 bias-pull-down: PUE=1, PUS=<bias-pull-down-value>
30 bias-pull-up: PUE=1, PUS=<bias-pull-up-value>
[all …]
/Zephyr-latest/tests/drivers/spi/spi_loopback/
Doverlay-mcux-flexio-spi.overlay4 * SPDX-License-Identifier: Apache-2.0
15 drive-strength = "r0-6";
16 slew-rate = "slow";
17 nxp,speed = "150-mhz";
27 drive-strength = "r0-6";
28 slew-rate = "slow";
29 nxp,speed = "150-mhz";
37 compatible = "nxp,flexio-spi";
39 #address-cells = <1>;
40 #size-cells = <0>;
[all …]
/Zephyr-latest/tests/arch/arm/arm_interrupt/src/
Darm_interrupt.c4 * SPDX-License-Identifier: Apache-2.0
13 static volatile int expected_reason = -1;
31 (pEsf->basic.r0 == 0) && in check_esf_matches_expectations()
32 (pEsf->basic.r1 == 1) && in check_esf_matches_expectations()
33 (pEsf->basic.r2 == 2) && in check_esf_matches_expectations()
34 (pEsf->basic.r3 == 3) && in check_esf_matches_expectations()
35 (pEsf->basic.lr == 15) && in check_esf_matches_expectations()
36 (*(uint16_t *)pEsf->basic.pc == expected_fault_instruction); in check_esf_matches_expectations()
39 return -1; in check_esf_matches_expectations()
43 const struct _callee_saved *callee_regs = pEsf->extra_info.callee; in check_esf_matches_expectations()
[all …]
/Zephyr-latest/boards/udoo/udoo_neo_full/
Dudoo_neo_full-pinctrl.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <nxp/nxp_imx/mimx6sx-pinctrl.dtsi>
14 input-schmitt-enable;
15 slew-rate = "fast";
16 drive-strength = "r0-6";
17 nxp,speed = "150-mhz";
18 bias-pull-up;
19 bias-pull-up-value="100k";
/Zephyr-latest/dts/bindings/gpio/
Dadi,adp5585-gpio.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "adi,adp5585-gpio"
8 include: gpio-controller.yaml
11 "#gpio-cells":
19 gpio-reserved-ranges:
25 5, 6, 7 is reserved. That's to say, GPIO R0~R4 occupy line
28 gpio-cells:
29 - pin
30 - flags
/Zephyr-latest/include/zephyr/arch/arm/cortex_a_r/
Dlib_helpers.h4 * SPDX-License-Identifier: Apache-2.0
6 * Armv8-R AArch32 architecture helpers.
34 __asm__ volatile ("mrrc p15, " #op1 ", %Q0, %R0, c" \
41 __asm__ volatile ("mcrr p15, " #op1 ", %Q0, %R0, c" \
68 MAKE_REG_HELPER(prselr, 0, 6, 2, 1);
69 MAKE_REG_HELPER(prbar, 0, 6, 3, 0);
70 MAKE_REG_HELPER(prlar, 0, 6, 3, 1);
89 MAKE_REG_HELPER(ICC_PMR_EL1, 0, 4, 6, 0);
/Zephyr-latest/scripts/coredump/gdbstubs/arch/
Darm_cortex_m.py5 # SPDX-License-Identifier: Apache-2.0
19 R0 = 0 variable in RegNum
25 R6 = 6
64 self.registers[RegNum.R0] = tu[0]
70 self.registers[RegNum.PC] = tu[6]
95 # Register not in coredump -> unknown value
146 thread_registers[RegNum.R0] = tu[0]
152 thread_registers[RegNum.PC] = tu[6]
/Zephyr-latest/tests/drivers/i2c/i2c_target_api/boards/
Dmimxrt1060_evk_mimxrt1062_qspi.overlay4 * SPDX-License-Identifier: Apache-2.0
12 drive-strength = "r0-6";
13 drive-open-drain;
14 slew-rate = "slow";
15 nxp,speed = "100-mhz";
16 input-enable;
21 /* To test this sample, connect J22.2 <-> J24.9 and J22.1 <-> J24.10 */
26 compatible = "zephyr,i2c-target-eeprom";
34 pinctrl-0 = <&pinmux_lpi2c3>;
35 pinctrl-names = "default";
[all …]
/Zephyr-latest/samples/subsys/llext/shell_loader/
DREADME.rst1 .. zephyr:code-sample:: llext-shell-loader
3 :relevant-api: llext_apis
21 .. zephyr-app-commands::
22 :zephyr-app: samples/subsys/llext/shell_loader
33 All the llext system related commands are available as sub-commands of llext
36 .. code-block:: console
39 llext - Loadable extension commands
61 .. code-block:: console
63 …$ arm-zephyr-eabi-gcc -mlong-calls -mthumb -c -o hello_world.elf tests/subsys/llext/hello_world/he…
64 $ arm-zephyr-eabi-objdump -r -d -x hello_world.elf
[all …]
/Zephyr-latest/samples/net/sockets/echo_client/boards/
Dmimxrt1020_evk.overlay5 * SPDX-License-Identifier: Apache-2.0
9 * imxrt1020_evk -> HOST
10 * nRF21540-DK -> RCP (nrf/samples/openthread/coprocessor)
12 * nRF21540 (P6) P0.08 RXD -> IMXRT1020-EVK (J17) D1 (GPIO B1 08) (TXD)
13 * nRF21540 (P6) P0.07 CTS -> IMXRT1020-EVK (J19) D8 (GPIO B1 07) (RTS)
14 * nRF21540 (P6) P0.06 TXD -> IMXRT1020-EVK (J17) D0 (GPIO B1 09) (RXD)
15 * nRF21540 (P6) P0.05 RTS -> IMXRT1020-EVK (J17) D7 (GPIO B1 06) (CTS)
25 zephyr,hdlc-rcp-if = &hdlc_rcp_if;
26 zephyr,ot-uart = &lpuart2;
30 compatible = "uart,hdlc-rcp-if";
[all …]
/Zephyr-latest/arch/arm/core/
Dgdbstub.c4 * SPDX-License-Identifier: Apache-2.0
12 /* Position of each register in the packet - n-th register in the ctx.registers array needs to be
13 * the packet_pos[n]-th byte of the g (read all registers) packet. See struct arm_register_names in
14 * GDB file gdb/arm-tdep.c, which defines these positions.
16 static const int packet_pos[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 41};
30 int ist = ((ctx.registers[SPSR] & BIT(SPSR_J)) >> (SPSR_J - 1)) | in is_bkpt()
52 ctx.registers[R0] = esf->basic.r0; in z_gdb_entry()
53 ctx.registers[R1] = esf->basic.r1; in z_gdb_entry()
54 ctx.registers[R2] = esf->basic.r2; in z_gdb_entry()
55 ctx.registers[R3] = esf->basic.r3; in z_gdb_entry()
[all …]
/Zephyr-latest/arch/arc/core/
Dfault.c4 * SPDX-License-Identifier: Apache-2.0
66 if ((thread->base.user_options & K_USER) != 0) { in z_check_thread_stack_fail()
75 guard_end = thread->stack_info.start; in z_check_thread_stack_fail()
76 guard_start = (uint32_t)thread->stack_obj; in z_check_thread_stack_fail()
82 guard_end = thread->arch.priv_stack_start; in z_check_thread_stack_fail()
83 guard_start = guard_end - Z_ARC_STACK_GUARD_SIZE; in z_check_thread_stack_fail()
89 guard_end = thread->stack_info.start; in z_check_thread_stack_fail()
90 guard_start = guard_end - Z_ARC_STACK_GUARD_SIZE; in z_check_thread_stack_fail()
95 * (like enter_s {r13-r26, fp, blink}) push a collection of in z_check_thread_stack_fail()
113 * the technical manual, just switch on the values in Table 6-5
[all …]
/Zephyr-latest/include/zephyr/xen/public/
Darch-arm.h1 /* SPDX-License-Identifier: MIT */
4 * arch-arm.h
40 * registers, the first argument in x0/r0 (for arm64/arm32 guests
42 * 32- or 64-bit), the second argument in x1/r1, the third in x2/r2,
47 * is an inter-procedure-call scratch register (e.g. for use in linker
52 * The return value is in x0/r0.
55 * by that hypercall (except r0 which is the return value) i.e. in
61 * EABI) and Procedure Call Standard for the ARM 64-bit Architecture
62 * (AAPCS64). Where there is a conflict the 64-bit standard should be
68 * which is mapped as Normal Inner Write-Back Outer Write-Back Inner-Shareable.
[all …]

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