Searched +full:pwm +full:- +full:3 (Results 1 – 25 of 730) sorted by relevance
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| /Zephyr-latest/dts/arm/ene/ |
| D | kb1200.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-m.dtsi>
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-m4";
24 clock-frequency = <DT_FREQ_M(48)>;
29 compatible = "mmio-sram";
34 flash-controller@50100000 {
35 compatible = "ene,kb1200-flash-controller";
37 #address-cells = <1>;
[all …]
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| /Zephyr-latest/dts/arm/gd/gd32e50x/ |
| D | gd32e507xe.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
13 compatible = "gd,gd32-timer";
16 interrupt-names = "brk", "up", "trgcom", "cc";
19 is-advanced;
23 pwm {
24 compatible = "gd,gd32-pwm";
26 #pwm-cells = <3>;
31 compatible = "gd,gd32-timer";
34 interrupt-names = "global";
40 pwm {
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| /Zephyr-latest/dts/bindings/pwm/ |
| D | ite,it8xxx2-pwm.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 description: ITE, it8xxx2 Pulse Width Modulator (PWM) node
6 compatible: "ite,it8xxx2-pwm"
8 include: [pwm-controller.yaml, base.yaml, pinctrl-device.yaml]
18 - 0
19 - 1
20 - 2
21 - 3
22 - 4
23 - 5
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| D | infineon,xmc4xxx-ccu8-pwm.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 Infineon XMC4XXX PWM Capture Compare Unit 8 (CCU8) module
7 The PWM CCU8 module can automatically generate a high-side
8 and a low-side PWM signal, where the two signals are complementary
11 The module supports adding a dead time between the high-side and
12 low-side PWM signals.
14 The dead time ensures that there is a delay before the PWM state
15 transitions from 0 to 1, preventing the high-side and low-side
20 two channels. A channel consists of a corresponding high-side
21 and low-side PWM signal.
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| D | telink,b91-pwm.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 description: Telink B91 PWM
7 include: [pwm-controller.yaml, pinctrl-device.yaml, base.yaml]
9 compatible: "telink,b91-pwm"
13 pinctrl-0:
16 clock-frequency:
19 description: Default PWM Peripheral Clock frequency in Hz (is used if 32K Clock is disabled)
21 clk32k-ch0-enable:
23 description: Enable 32K Source Clock for PWM Channel 0
25 clk32k-ch1-enable:
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| D | ite,it8801-pwm.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 description: ITE IT8801 I2C-based PWM device driver
6 compatible: "ite,it8801-pwm"
8 include: [base.yaml, pinctrl-device.yaml, pwm-controller.yaml]
18 Switching the pin to PWM alternate function.
24 - 1
25 - 2
26 - 3
27 - 4
28 - 7
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| D | raspberrypi,pico-pwm.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 description: Raspberry Pi Pico PWM
6 compatible: "raspberrypi,pico-pwm"
8 include: [pwm-controller.yaml, pinctrl-device.yaml, reset-device.yaml, base.yaml]
17 divider-int-0:
20 The integral part of the divider for pwm slice 0.
24 the number of cycles to PWM, a division ratio appropriate to that value is set.
26 divider-frac-0:
29 The fractional part of the divider for pwm slice 0.
30 This number should be in the range 0 - 15.
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| D | nxp,s32-emios-pwm.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 NXP S32 eMIOS PWM node for S32 SoCs. Each channel in eMIOS can be configured
6 to use for PWM operation. There are several PWM modes supported by this module,
11 - Channel 0 for mode OPWFMB
12 - Channel 1 for mode OPWMB
13 - Channel 2 for mode OPWMCB with deadtime inserted at leading edge
14 - Channel 3 for mode SAIC, use internal timebase with input filter = 2 eMIOS clock
16 emios0_pwm: pwm {
19 pwm-mode = "OPWFMB";
22 duty-cycle = <32768>;
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| /Zephyr-latest/tests/drivers/pwm/pwm_api/ |
| D | testcase.yaml | 2 drivers.pwm:
4 - drivers
5 - pwm
6 - userspace
7 filter: dt_alias_exists("pwm-0") or dt_alias_exists("pwm-1") or dt_alias_exists("pwm-2")
8 or dt_alias_exists("pwm-3") or dt_compat_enabled("st,stm32-pwm")
9 or dt_compat_enabled("intel,blinky-pwm") or dt_compat_enabled("nordic,nrf-pwm")
10 depends_on: pwm
11 drivers.pwm.ke1xz_pwm_flexio:
13 - drivers
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| /Zephyr-latest/dts/arm/microchip/mec5/ |
| D | mec5_pkg176_pwms.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
7 /* So far all Microchip MEC5 family of SoC's so add three more PWM's
8 * in the 176-pin (LJ) package.
11 pwm9: pwm@40005890 {
14 #pwm-cells = <3>;
16 pwm10: pwm@400058a0 {
19 #pwm-cells = <3>;
21 pwm11: pwm@400058b0 {
24 #pwm-cells = <3>;
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| /Zephyr-latest/dts/arm/st/f1/ |
| D | stm32f103Xg.dtsi | 1 /* SPDX-License-Identifier: Apache-2.0
18 flash-controller@40022000 {
22 * This matters if you're doing in-application
24 * read-while-write capabilities, but is
25 * otherwise a non-issue.
28 erase-block-size = <DT_SIZE_K(2)>;
33 compatible = "st,stm32-timers";
42 pwm {
43 compatible = "st,stm32-pwm";
45 #pwm-cells = <3>;
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| /Zephyr-latest/dts/riscv/ite/ |
| D | it8801-common-cfg.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
7 #include <ite/it8801-mfd-map.dtsi>
10 #address-cells = <1>;
11 #size-cells = <1>;
15 compatible = "ite,it8801-gpio";
21 gpio-controller;
22 #gpio-cells = <2>;
24 pin-mask = <0xdb>;
28 compatible = "ite,it8801-gpio";
34 gpio-controller;
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| /Zephyr-latest/dts/arm/st/f3/ |
| D | stm32f373.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/adc/stm32f1_adc.h>
12 compatible = "st,stm32f373", "st,stm32f3", "simple-bus";
19 compatible = "st,stm32f1-rcc";
22 pinctrl: pin-controller@48000000 {
24 compatible = "st,stm32-gpio";
25 gpio-controller;
26 #gpio-cells = <2>;
33 compatible = "st,stm32-i2c-v2";
34 clock-frequency = <I2C_BITRATE_STANDARD>;
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| /Zephyr-latest/dts/arm/microchip/ |
| D | mec172xnlj.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/gpio/microchip-xec-gpio.h>
13 #include <zephyr/dt-bindings/i2c/i2c.h>
14 #include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
18 #include "mec172x/mec172x-vw-routing.dtsi"
22 #address-cells = <1>;
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| D | mec1501hsz.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
8 #include <zephyr/dt-bindings/adc/adc.h>
9 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/gpio/microchip-xec-gpio.h>
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-m4";
[all …]
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| /Zephyr-latest/dts/arm/infineon/cat1b/cyw20829/ |
| D | cyw20829.dtsi | 5 * SPDX-License-Identifier: Apache-2.0
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "arm,cortex-m33";
19 cpu-power-states = <&idle &suspend_to_ram>;
22 power-states {
24 compatible = "zephyr,power-state";
25 power-state-name = "suspend-to-idle";
26 min-residency-us = <1000000>;
30 compatible = "zephyr,power-state";
[all …]
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| /Zephyr-latest/samples/drivers/led/pwm/boards/ |
| D | mec172xevb_assy6906.overlay | 4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/pwm/pwm.h>
10 * BBLED controller 0 uses GPIO156/LED1 connected to JP71-11
11 * BBLED controller 1 uses GPIO157/LED2 connected to JP71-13
12 * BBLED controller 2 uses GPIO153/LED3 connected to JP71-5
13 * BBLED controller 3 uses GPIO035/PWM8 connected to JP67-19
17 * and implements duty cycle for blink mode as an 8-bit value where 0 is off and
18 * 255 full on. BBLED PWM is 8-bit.
19 * BBLED-PWM driver get cycles API reports 32KHz/256 or 48M/256.
20 * Due to all the above we use 50 ms for DT PWM period.
[all …]
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| D | mec15xxevb_assy6853.overlay | 4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/pwm/pwm.h>
10 * BBLED controller 0 uses GPIO156/LED0 connected to JP31-13
11 * BBLED controller 1 uses GPIO157/LED1 connected to JP31-15
12 * BBLED controller 2 uses GPIO153/LED2 connected to JP31-17
15 * and implements duty cycle for blink mode as an 8-bit value where 0 is off and
16 * 255 full on. BBLED PWM is 8-bit.
17 * BBLED-PWM driver get cycles API reports 32KHz/256 or 48M/256.
18 * Due to all the above we use 50 ms for DT PWM period.
24 compatible = "pwm-leds";
[all …]
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| /Zephyr-latest/dts/arm/nuvoton/npcx/ |
| D | npcx.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
10 #include <zephyr/dt-bindings/adc/adc.h>
11 #include <zephyr/dt-bindings/clock/npcx_clock.h>
12 #include <zephyr/dt-bindings/flash_controller/npcx_fiu_qspi.h>
13 #include <zephyr/dt-bindings/gpio/gpio.h>
14 #include <zephyr/dt-bindings/i2c/i2c.h>
15 #include <zephyr/dt-bindings/pinctrl/npcx-pinctrl.h>
16 #include <zephyr/dt-bindings/pwm/pwm.h>
17 #include <zephyr/dt-bindings/sensor/npcx_tach.h>
[all …]
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| /Zephyr-latest/tests/drivers/pwm/pwm_loopback/boards/ |
| D | ek_ra2a1.overlay | 4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/pwm/pwm.h>
8 #include <zephyr/dt-bindings/pwm/ra_pwm.h>
12 compatible = "test-pwm-loopback";
13 /* first index must be a 32-Bit timer */
23 psels = <RA_PSEL(RA_PSEL_GPT1, 3, 4)>,
24 <RA_PSEL(RA_PSEL_GPT1, 3, 3)>;
30 pinctrl-0 = <&pwm6_default>;
31 pinctrl-names = "default";
33 interrupt-names = "gtioca", "overflow";
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| D | ek_ra6e2.overlay | 4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/pwm/pwm.h>
8 #include <zephyr/dt-bindings/pwm/ra_pwm.h>
12 compatible = "test-pwm-loopback";
22 psels = <RA_PSEL(RA_PSEL_GPT1, 3, 2)>,
23 <RA_PSEL(RA_PSEL_GPT1, 3, 1)>;
29 pinctrl-0 = <&pwm4_default>;
30 pinctrl-names = "default";
32 interrupt-names = "gtioca", "overflow";
|
| D | ek_ra4e2.overlay | 4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/pwm/pwm.h>
8 #include <zephyr/dt-bindings/pwm/ra_pwm.h>
12 compatible = "test-pwm-loopback";
22 psels = <RA_PSEL(RA_PSEL_GPT1, 3, 2)>,
23 <RA_PSEL(RA_PSEL_GPT1, 3, 1)>;
29 pinctrl-0 = <&pwm4_default>;
30 pinctrl-names = "default";
32 interrupt-names = "gtioca", "overflow";
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| /Zephyr-latest/dts/arm/gd/gd32e10x/ |
| D | gd32e10x.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/pwm/pwm.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/clock/gd32e10x-clocks.h>
13 #include <zephyr/dt-bindings/reset/gd32e10x.h>
17 #address-cells = <1>;
18 #size-cells = <0>;
21 clock-frequency = <DT_FREQ_M(120)>;
[all …]
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| /Zephyr-latest/dts/arm/nxp/ |
| D | nxp_rt118x.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
7 #include <dt-bindings/clock/imx_ccm_rev2.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/i2c/i2c.h>
10 #include <zephyr/dt-bindings/adc/adc.h>
11 #include <zephyr/dt-bindings/pwm/pwm.h>
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "arm,cortex-m33f";
23 #address-cells = <1>;
[all …]
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| /Zephyr-latest/tests/drivers/pwm/pwm_api/boards/ |
| D | frdm_ke1xz_flexio_pwm.overlay | 4 * SPDX-License-Identifier: Apache-2.0
9 pwm-0 = &flexio0_pwm;
17 compatible = "nxp,flexio-pwm";
18 #pwm-cells = <3>;
20 pinctrl-0 = <&flexio_pwm_default>;
21 pinctrl-names = "default";
24 pin-id = <3>;
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