Searched +full:power +full:- +full:domain +full:- +full:cells (Results 1 – 25 of 44) sorted by relevance
12
| /Zephyr-latest/tests/subsys/pm/device_driver_init/ |
| D | app.overlay | 3 compatible = "power-domain-gpio";
4 enable-gpios = <&gpio0 0 0>;
5 #power-domain-cells = <0>;
9 compatible = "power-domain-gpio";
10 enable-gpios = <&gpio0 1 0>;
11 power-domains = <&test_reg>;
12 #power-domain-cells = <0>;
16 compatible = "power-domain-gpio";
17 enable-gpios = <&gpio0 2 0>;
18 power-domains = <&test_reg>;
[all …]
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| /Zephyr-latest/tests/subsys/pm/device_power_domains/ |
| D | app.overlay | 3 compatible = "power-domain-gpio";
4 enable-gpios = <&gpio0 0 0>;
5 #power-domain-cells = <0>;
9 compatible = "power-domain-gpio";
10 enable-gpios = <&gpio0 1 0>;
11 #power-domain-cells = <0>;
15 compatible = "power-domain-gpio";
16 enable-gpios = <&gpio0 2 0>;
17 power-domains = <&test_reg_0>;
18 #power-domain-cells = <0>;
[all …]
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| /Zephyr-latest/tests/drivers/build_all/power_domain/ |
| D | app.overlay | 3 * SPDX-License-Identifier: Apache-2.0
8 #address-cells = <1>;
9 #size-cells = <1>;
13 gpio-controller;
15 #gpio-cells = <0x2>;
20 compatible = "power-domain-gpio";
21 enable-gpios = <&test_gpio 0 0>;
22 #power-domain-cells = <0>;
23 zephyr,pm-device-runtime-auto;
27 compatible = "power-domain-gpio-monitor";
[all …]
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| /Zephyr-latest/tests/subsys/pm/power_domain/ |
| D | app.overlay | 4 * SPDX-License-Identifier: Apache-2.0
9 compatible = "power-domain";
11 #power-domain-cells = <0>;
15 compatible = "test-device-pm";
17 power-domains = <&test_domain>;
21 compatible = "test-device-pm";
23 power-domains = <&test_domain>;
27 compatible = "power-domain";
29 #power-domain-cells = <0>;
33 compatible = "test-device-pm";
[all …]
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| /Zephyr-latest/dts/xtensa/nxp/ |
| D | nxp_imx8.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/clock/imx_ccm.h>
10 #include <zephyr/dt-bindings/dai/esai.h>
11 #include <zephyr/dt-bindings/power/imx_scu_rsrc.h>
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "cdns,tensilica-xtensa-lx6";
23 #address-cells = <1>;
24 #size-cells = <0>;
26 clic: interrupt-controller@0 {
[all …]
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| /Zephyr-latest/dts/bindings/power-domain/ |
| D | power-domain-gpio-monitor.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 Simple monitorig power domain
7 This power domain monitors the state of a GPIO pin to detect whether a power
8 rail is on/off. Therefore, performing resume/suspend on power domain won't
9 change physical state of power rails and that action won't be triggered on
11 pending transaction won't be interrupted by power state change.
13 compatible: "power-domain-gpio-monitor"
15 include: power-domain.yaml
19 type: phandle-array
24 "#power-domain-cells":
|
| D | intel,adsp-power-domain.yaml | 3 # SPDX-License-Identifier: Apache-2.0
5 description: Power domains for intel ADSP
7 compatible: "intel,adsp-power-domain"
9 include: power-domain.yaml
12 bit-position:
17 read_address (PWRSTS) to set power active or confirm power active
18 for a desired domain.
21 "#power-domain-cells":
|
| D | nxp,scu-pd.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 description: NXP SCU-managed power domain
6 compatible: "nxp,scu-pd"
8 include: power-domain.yaml
11 nxp,resource-id:
16 the resource on which the PD-related operations are to be
19 "#power-domain-cells":
|
| D | power-domain-gpio.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 description: Simple GPIO controlled power domain
6 compatible: "power-domain-gpio"
8 include: power-domain.yaml
11 enable-gpios:
12 type: phandle-array
18 provide the GPIO polarity and open-drain status in the phandle
19 selector. The Linux enable-active-high and gpio-open-drain
22 startup-delay-us:
27 off-on-delay-us:
[all …]
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| D | power-domain.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 description: Properties for power domains
6 compatible: "power-domain"
11 "#power-domain-cells":
|
| /Zephyr-latest/dts/bindings/base/ |
| D | base.yaml | 10 - "ok" # Deprecated form
11 - "okay"
12 - "disabled"
13 - "reserved"
14 - "fail"
15 - "fail-sss"
18 type: string-array
26 reg-names:
27 type: string-array
34 # Does not follow the 'type: phandle-array' scheme, but gets type-checked
[all …]
|
| /Zephyr-latest/tests/kernel/device/ |
| D | app.overlay | 5 * SPDX-License-Identifier: Apache-2.0
12 * with real-world devicetree nodes, to allow these tests to run on
17 #address-cells = <1>;
18 #size-cells = <1>;
50 reg-names = "chip",
59 zephyr,deferred-init;
66 zephyr,deferred-init;
72 power-domains = <&fakedomain_2>;
73 #power-domain-cells = <0>;
79 power-domains = <&fakedomain_0>;
[all …]
|
| /Zephyr-latest/dts/xtensa/intel/ |
| D | intel_adsp_ace15_mtpm.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "cdns,tensilica-xtensa-lx7";
19 cpu-power-states = <&d0i3 &d3>;
20 i-cache-line-size = <64>;
21 d-cache-line-size = <64>;
26 compatible = "cdns,tensilica-xtensa-lx7";
28 cpu-power-states = <&d3>;
33 compatible = "cdns,tensilica-xtensa-lx7";
[all …]
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| D | intel_adsp_ace20_lnl.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "cdns,tensilica-xtensa-lx7";
19 cpu-power-states = <&d0i3 &d3>;
20 i-cache-line-size = <64>;
21 d-cache-line-size = <64>;
26 compatible = "cdns,tensilica-xtensa-lx7";
28 cpu-power-states = <&d0i3 &d3>;
33 compatible = "cdns,tensilica-xtensa-lx7";
[all …]
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| D | intel_adsp_ace30_ptl.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "cdns,tensilica-xtensa-lx7";
19 cpu-power-states = <&d0i3 &d3>;
20 i-cache-line-size = <64>;
21 d-cache-line-size = <64>;
26 compatible = "cdns,tensilica-xtensa-lx7";
28 cpu-power-states = <&d0i3 &d3>;
33 compatible = "cdns,tensilica-xtensa-lx7";
[all …]
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| D | intel_adsp_ace30.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "cdns,tensilica-xtensa-lx7";
19 cpu-power-states = <&d0i3 &d3>;
20 i-cache-line-size = <64>;
21 d-cache-line-size = <64>;
26 compatible = "cdns,tensilica-xtensa-lx7";
28 cpu-power-states = <&d0i3 &d3>;
33 compatible = "cdns,tensilica-xtensa-lx7";
[all …]
|
| /Zephyr-latest/dts/bindings/power/ |
| D | nordic,nrf-gpd.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 description: Nordic nRF Global Power Domain
6 compatible: "nordic,nrf-gpd"
10 power-domain-cells:
11 - id
|
| D | atmel,sam-supc.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 Atmel SAM SUPC (Supply-Controller) controller
7 The supply controller manages the voltage reference, power supply and supply
8 monitoring of the device. It have a special feature that it can wake-up the
9 device from a low-power state using special peripherals as wake-up sources.
11 The dedicated peripherals that can wake-up the core supply domain are: RTC,
13 inform the wakeup-source-id property on their respective nodes.
17 wakeup-source-id = <&supc SUPC_WAKEUP_SOURCE_RTC>;
21 The special peripheral will wake-up the device only when the standard property
22 wakeup-source is defined, e.g.:
[all …]
|
| /Zephyr-latest/tests/kernel/device/boards/ |
| D | hifive_unmatched_fu740_s7.overlay | 5 * SPDX-License-Identifier: Apache-2.0
12 * with real-world devicetree nodes, to allow these tests to run on
47 reg-names = "chip",
56 zephyr,deferred-init;
63 zephyr,deferred-init;
69 #power-domain-cells = <0>;
70 power-domains = <&fakedomain_2>;
76 #power-domain-cells = <0>;
77 power-domains = <&fakedomain_0>;
83 #power-domain-cells = <0>;
|
| D | hifive_unmatched_fu740_u74.overlay | 5 * SPDX-License-Identifier: Apache-2.0
12 * with real-world devicetree nodes, to allow these tests to run on
47 reg-names = "chip",
56 zephyr,deferred-init;
63 zephyr,deferred-init;
69 #power-domain-cells = <0>;
70 power-domains = <&fakedomain_2>;
76 #power-domain-cells = <0>;
77 power-domains = <&fakedomain_0>;
83 #power-domain-cells = <0>;
|
| /Zephyr-latest/dts/bindings/pwm/ |
| D | microchip,xec-pwmbbled.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 include: [pwm-controller.yaml, base.yaml, pinctrl-device.yaml]
8 compatible: "microchip,xec-pwmbbled"
27 clock-select:
32 - PWM_BBLED_CLK_AHB: Clock source is the PLL based AHB clock
33 - PWM_BBLED_CLK_32K: Clock source is the 32KHz domain
35 - "PWM_BBLED_CLK_32K"
36 - "PWM_BBLED_CLK_48M"
38 pinctrl-0:
41 pinctrl-names:
[all …]
|
| /Zephyr-latest/dts/bindings/clock/ |
| D | microchip,xec-pcr.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 description: Microchip XEC Power Clock Reset and VBAT register (PCR)
6 compatible: "microchip,xec-pcr"
8 include: [clock-controller.yaml, pinctrl-device.yaml, base.yaml]
14 core-clock-div:
17 description: Divide 96 MHz PLL clock to produce Cortex-M4 core clock
19 slow-clock-div:
22 PWM and TACH clock domain divided down from 48 MHz AHB clock. The
25 pll-32k-src:
30 periph-32k-src:
[all …]
|
| /Zephyr-latest/dts/common/nordic/ |
| D | nrf54h20.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/dt-bindings/adc/nrf-saadc.h>
11 #include <zephyr/dt-bindings/misc/nordic-nrf-ficr-nrf54h20.h>
12 #include <zephyr/dt-bindings/misc/nordic-domain-id-nrf54h20.h>
13 #include <zephyr/dt-bindings/misc/nordic-owner-id-nrf54h20.h>
14 #include <zephyr/dt-bindings/misc/nordic-tddconf.h>
15 #include <zephyr/dt-bindings/reserved-memory/nordic-owned-memory.h>
16 #include <zephyr/dt-bindings/power/nordic-nrf-gpd.h>
18 /delete-node/ &sw_pwm;
21 #address-cells = <1>;
[all …]
|
| /Zephyr-latest/dts/arm/nuvoton/npcm/ |
| D | npcm.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
10 #include <zephyr/dt-bindings/clock/npcm_clock.h>
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "arm,cortex-m4";
29 reg-io-width = <1>;
35 reg-io-width = <2>;
38 pcc: clock-controller@4000d000 {
39 compatible = "nuvoton,npcm-pcc";
[all …]
|
| /Zephyr-latest/dts/bindings/dac/ |
| D | espressif,esp32-dac.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 is part of the RTC low-power domain and belongs to the SENSE
13 - GPIO25 as DAC channel 1
14 - GPIO26 as DAC channel 2
16 ESP32-S2 pads
17 - GPIO17 as DAC channel 1
18 - GPIO18 as DAC channel 2
28 properties 'dac-channel-id', which uses zero based channel index.
29 Variable 'dac-resolution' must be also specified, although ESP32
35 dac-channel-id = <0>;
[all …]
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