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/Zephyr-latest/drivers/espi/
DKconfig4 # SPDX-License-Identifier: Apache-2.0
7 bool "Enhanced Serial Peripheral Interface (eSPI) bus drivers"
22 module-str = espi
38 bool "eSPI peripheral channel"
41 eSPI Controller supports peripheral channel.
66 If this is disabled, it means the app wants to be give the opportunity
67 to prepare for either HOST suspend or reset.
76 completed by sending a virtual wire message to the eSPI master.
82 bool "eSPI Out-of-band channel"
94 bool "UART peripheral"
[all …]
DKconfig.xec4 # SPDX-License-Identifier: Apache-2.0
48 This tells the driver to which SoC UART to direct the UART traffic
56 Use minimum RAM buffer size by default but allow applications to
66 to override if eSPI host doesn't support it.
89 int "Host I/O peripheral port size for shared memory in MEC172X series"
93 This is the port size used by the Host and EC to communicate over
94 the shared memory region to return the ACPI response data.
97 int "Host I/O peripheral port size for ec host command in MEC172X series"
101 This is the port size used by the Host and EC to communicate over
102 the shared memory region to return the host command parameter data.
[all …]
DKconfig.npcx4 # SPDX-License-Identifier: Apache-2.0
13 This option enables the Intel Enhanced Serial Peripheral Interface
17 int "Host I/O peripheral port size for shared memory in npcx series"
21 This is the port size used by the Host and EC to communicate over
22 the shared memory region to return the ACPI response data. Please
27 int "Host I/O peripheral port size for ec host command in npcx series"
31 This is the port size used by the Host and EC to communicate over
32 the shared memory region to return the host command parameter data.
43 (with low probability) cause the eSPI_SIF module to transition to
60 The size of the ring buffer in byte used by the Port80 ISR to store
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/Zephyr-latest/dts/bindings/dma/
Dgd,gd32-dma.yaml2 # SPDX-License-Identifier: Apache-2.0
10 - bit 6-7: Direction (see dma.h)
11 - 0x0: MEMORY to MEMORY
12 - 0x1: MEMORY to PERIPH
13 - 0x2: PERIPH to MEMORY
14 - 0x3: reserved for PERIPH to PERIPH
16 - bit 9: Peripheral address increase
17 - 0x0: no address increment between transfers
18 - 0x1: increment address between transfers
20 - bit 10: Memory address increase
[all …]
Dgd,gd32-dma-v1.yaml2 # SPDX-License-Identifier: Apache-2.0
9 slot: Select peripheral to connect DMA
12 - bit 6-7: Direction (see dma.h)
13 - 0x0: MEMORY to MEMORY
14 - 0x1: MEMORY to PERIPH
15 - 0x2: PERIPH to MEMORY
16 - 0x3: reserved for PERIPH to PERIPH
18 - bit 9: Peripheral address increase
19 - 0x0: no address increment between transfers
20 - 0x1: increment address between transfers
[all …]
Dst,stm32-bdma.yaml2 # SPDX-License-Identifier: Apache-2.0
7 The STM32 BDMA is a general-purpose direct memory access controller
9 Each channel can have up to 8 requests.
10 BDMA clients connected to the STM32 BDMA controller must use the format
11 described in the dma.txt file, using a four-cell specifier for each
12 channel: a phandle to the BDMA controller plus the following four integer cells:
13 1. channel: the bdma stream from 0 to <bdma-requests>
15 3. channel-config: A 32bit mask specifying the BDMA channel configuration
17 -bit 6-7 : Direction (see dma.h)
18 0x0: MEM to MEM
[all …]
Despressif,esp32-gdma.yaml2 # SPDX-License-Identifier: Apache-2.0
5 Espressif's GDMA (General Direct Memory Access) Node
7 General Direct Memory Access (GDMA) is a feature that allows
8 peripheral-to-memory, memory-to-peripheral, and memory-to-memory
11 The GDMA controller in ESP32-C3 has six independent channels,
14 Every channel can be connected to different peripherals.
24 The GDMA controller in ESP32-S3 has ten independent channels,
40 compatible: "espressif,esp32-gdma"
42 include: dma-controller.yaml
45 "#dma-cells":
[all …]
Dst,stm32-dma-v1.yaml2 # SPDX-License-Identifier: Apache-2.0
9 DMA clients connected to the STM32 DMA controller must use the format
10 described in the dma.txt file, using a four-cell specifier for each
11 channel: a phandle to the DMA controller plus the following four integer cells:
12 1. channel: the dma stream from 0 to <dma-requests>
14 this value is 0 for Memory-to-memory transfers
15 or a value between <1> .. <dma-generators> (not supported yet)
16 or a value between <dma-generators>+1 .. <dma-generators>+<dma-requests>
17 3. channel-config: A 32bit mask specifying the DMA channel configuration
19 -bit 6-7 : Direction (see dma.h)
[all …]
Dst,stm32-dmamux.yaml2 # SPDX-License-Identifier: Apache-2.0
7 The STM32 DMAMUX is a direct memory access multiplexer
9 DMAMUX clients connected to the STM32 DMA ultiplexer must use a two-cell specifier
10 for each dmamux channel: a phandle to the DMA multiplexer plus the following 2 integer cells:
11 1. channel: the mux channel from 0 to <dma-channels> - 1
13 3. channel-config: A 32bit mask specifying the DMA channel configuration
15 -bit 6-7 : Direction (see dma.h)
16 0x0: MEM to MEM
17 0x1: MEM to PERIPH
18 0x2: PERIPH to MEM
[all …]
Dst,stm32-dma-v2.yaml2 # SPDX-License-Identifier: Apache-2.0
9 DMA clients connected to the STM32 DMA controller must use the format
10 described in the dma.txt file, using a four-cell specifier for each
12 DMA clients connected to the STM32 DMA controller must use the format
13 described in the dma.txt file, using a 3-cell specifier for each
14 channel: a phandle to the DMA controller plus the following four integer cells:
15 1. channel: the dma stream from 1 to <dma-requests>
17 this value is 0 for Memory-to-memory transfers
18 or a value between <1> .. <dma-generators> (not supported yet)
19 or a value between <dma-generators>+1 .. <dma-generators>+<dma-requests>
[all …]
Dandestech,atcdmac300.yaml4 # SPDX-License-Identifier: Apache-2.0
8 include: dma-controller.yaml
17 chain-transfer:
20 "#dma-cells":
23 dma-cells:
24 - channel
25 - slot
26 - channel-config
30 channel: a phandle to the DMA controller plus the following four integer cells:
32 2. slot: DMA peripheral request ID
[all …]
Dst,stm32-dma-v2bis.yaml2 # SPDX-License-Identifier: Apache-2.0
10 DMA clients connected to the STM32 DMA controller must use the format
11 described in the dma.txt file, using a 2-cell specifier for each
12 channel: a phandle to the DMA controller plus the following four integer cells:
13 1. channel: the dma stream from 1 to <dma-requests>
14 2. channel-config: A 32bit mask specifying the DMA channel configuration
17 -bit 5 : DMA cyclic mode config
20 -bit 6-7 : Direction (see dma.h)
21 0x0: STM32_DMA_MEMORY_TO_MEMORY: MEM to MEM
22 0x1: STM32_DMA_MEMORY_TO_PERIPH: MEM to PERIPH
[all …]
Dst,stm32u5-dma.yaml2 # SPDX-License-Identifier: Apache-2.0
9 DMA clients connected to the STM32 DMA controller must use a three-cell
17 dma-names = "tx", "rx";
19 It is a phandle to the DMA controller plus the following three integer cells
20 1. channel: the stream or channel from 0 to (<dma-channels> - 1).
22 the slot is a value between <0> .. (<dma-requests> - 1).
23 3. channel-config: A 32bit mask specifying the DMA channel configuration
25 -bit 6-7 : Direction (see dma.h)
26 0x0: MEM to MEM
27 0x1: MEM to PERIPH
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/dma/
Ddma_smartbond.h4 * SPDX-License-Identifier: Apache-2.0
11 * @brief Vendror-specific DMA peripheral triggering sources.
14 * is configured for peripheral to peripheral or memory to peripheral
/Zephyr-latest/include/zephyr/drivers/dma/
Ddma_smartbond.h4 * SPDX-License-Identifier: Apache-2.0
11 * @brief Vendror-specific DMA peripheral triggering sources.
14 * is configured for peripheral to peripheral or memory to peripheral
/Zephyr-latest/dts/bindings/flash_controller/
Dnordic,nrf-qspi.yaml2 # SPDX-License-Identifier: Apache-2.0
5 Properties defining the interface for the Nordic QSPI peripheral.
7 The reg property describes two register blocks: one for the memory
8 corresponding to the QSPI peripheral registers, and another for
9 the memory mapped XIP area:
12 compatible = "nordic,nrf-qspi";
14 reg-names = "qspi", "qspi_mm";
19 "qspi" are the QSPI peripheral registers. The register block with
22 compatible: "nordic,nrf-qspi"
24 include: [flash-controller.yaml, pinctrl-device.yaml]
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/Zephyr-latest/dts/x86/intel/
Dintel_ish5.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <dt-bindings/interrupt-controller/intel-ioapic.h>
9 #include <dt-bindings/i2c/i2c.h>
13 power-states {
15 compatible = "zephyr,power-state";
16 power-state-name = "runtime-idle";
17 min-residency-us = <500>;
18 substate-id = <1>;
22 compatible = "zephyr,power-state";
23 power-state-name = "suspend-to-ram";
[all …]
/Zephyr-latest/dts/bindings/mtd/
Dst,stm32-nv-flash.yaml2 STM32 flash memory. This binding is for the flash memory itself, not
3 the flash controller peripheral. For that, see the
4 "st,stm32-flash-controller" binding.
6 include: soc-nv-flash.yaml
8 compatible: st,stm32-nv-flash
11 max-erase-time:
13 description: max erase time(millisecond) of a flash sector or page or half-page
15 bank2-flash-size:
18 Embedded flash memory bank 2 size in KBytes.
19 Used by CM4 CPU because it cannot access flash controller register to read size.
[all …]
/Zephyr-latest/subsys/emul/espi/
DKconfig4 # SPDX-License-Identifier: Apache-2.0
10 - virtual wires and writing to port 80. It can be extended. Note: Because this emulator is
11 not tied to a particular DT node, it does not make use of the DT_HAS_<compat>_ENABLED
17 int "Host I/O peripheral port size for shared memory in emulator"
21 This is the port size used to mimic the Host and EC communication
22 over the shared memory region which returns the ACPI response data.
/Zephyr-latest/dts/bindings/memory-controllers/
Dst,stm32-fmc.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32 Flexible Memory Controller (FMC).
7 The FMC allows to interface with static-memory mapped external devices such as
12 The FMC performs only one access at a time to an external device.
14 The flexible memory controller includes three memory controllers:
16 - NOR/PSRAM memory controller
17 - NAND memory controller (some devices also support PC Card)
18 - Synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) controller
20 Each memory controller is defined below the FMC DeviceTree node and is managed
22 device handles the signals and the peripheral clocks. FMC can be enabled
[all …]
Dst,stm32h7-fmc.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32 Flexible Memory Controller (FMC).
7 The FMC allows to interface with static-memory mapped external devices such as
12 The FMC performs only one access at a time to an external device.
14 The flexible memory controller includes three memory controllers:
16 - NOR/PSRAM memory controller
17 - NAND memory controller (some devices also support PC Card)
18 - Synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) controller
20 Each memory controller is defined below the FMC DeviceTree node and is managed
22 device handles the signals and the peripheral clocks. FMC can be enabled
[all …]
/Zephyr-latest/dts/bindings/i2c/
Dnordic,nrf-twis.yaml2 # SPDX-License-Identifier: Apache-2.0
7 The TWIS peripheral is an I2C controller which supports the I2C
8 peripheral role, and EasyDMA. TWIS shares resources with TWIM and TWI,
9 only one of them can be enabled for each peripheral instance.
10 Overwrite the compatible of the i2c node to select between TWIM/TWI
11 and TWIS, along with the pinctrl instances to select between TWIM/TWI
21 bias-pull-up;
29 low-power-enable;
35 compatible = "nordic,nrf-twis";
36 pinctrl-0 = <&i2c2_default>;
[all …]
Dnordic,nrf-twi.yaml2 # SPDX-License-Identifier: Apache-2.0
8 peripherals. When a single SoC peripheral ID corresponds to multiple
10 nodes must be set up to select TWI before use.
12 To select TWI, set the node's "compatible" to "nordic,nrf-twi" and
13 its "status" to "okay", e.g. using an overlay file like this:
15 /* This is for TWI0 -- change to "i2c1" for TWI1. */
17 compatible = "nordic,nrf-twi";
22 You can use either of these options to check TWI availability on
25 1. Check the peripheral Instantiation table in the Memory
41 this binding. See the "nordic,nrf-twim" binding instead.
[all …]
/Zephyr-latest/doc/hardware/peripherals/
Ddma.rst3 Direct Memory Access (DMA)
9 Direct Memory Access (Controller) is a commonly provided type of co-processor that can typically
10 offload transferring data to and from peripherals and memory.
12 The DMA API is not a portable API and really cannot be as each DMA has unique memory requirements,
13 peripheral interactions, and features. The API in effect provides a union of all useful DMA
15 peripheral devices for vendors where the DMA IP might be very similar but have slight variances.
17 The DMA drivers in general do not handle cache coherency; this is left up to the developer as
27 From an API point of view, a DMA channel is a single-owner object, meaning the drivers should not
28 attempt to wrap a channel with kernel synchronization primitives such as mutexes or semaphores. If
32 This enables the entire API to be low-cost and callable from any call context, including ISRs where
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/Zephyr-latest/dts/bindings/audio/
Dnordic,nrf-pdm.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nordic,nrf-pdm"
8 include: ["base.yaml", "pinctrl-device.yaml", "memory-region.yaml", "nordic-clockpin.yaml"]
17 pinctrl-0:
20 pinctrl-names:
23 clock-source:
27 Clock source to be used by the PDM peripheral. The following options
29 - "PCLK32M": 32 MHz peripheral clock, synchronous to HFCLK
30 - "PCLK32M_HFXO": PCLK32M running off the 32 MHz crystal oscillator
32 - "ACLK": Audio PLL clock with configurable frequency (frequency for
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