1# Microchip XEC ESPI configuration options
2
3# Copyright (c) 2019 Intel Corporation
4# SPDX-License-Identifier: Apache-2.0
5
6config ESPI_XEC
7	bool "XEC Microchip ESPI driver"
8	default y
9	depends on DT_HAS_MICROCHIP_XEC_ESPI_ENABLED
10	select PINCTRL
11	help
12	  Enable the Microchip XEC ESPI driver for MEC15xx family.
13
14config ESPI_XEC_V2
15	bool "XEC Microchip ESPI V2 driver"
16	default y
17	depends on DT_HAS_MICROCHIP_XEC_ESPI_V2_ENABLED
18	select PINCTRL
19	help
20	  Enable the Microchip XEC ESPI driver for MEC172x series.
21
22if ESPI_XEC || ESPI_XEC_V2
23
24config ESPI_OOB_CHANNEL
25	default y
26
27config ESPI_FLASH_CHANNEL
28	default y
29
30config ESPI_PERIPHERAL_HOST_IO
31	default  y
32
33config ESPI_PERIPHERAL_HOST_IO_PVT
34	default  y
35
36config ESPI_PERIPHERAL_DEBUG_PORT_80
37	default y
38
39config ESPI_PERIPHERAL_UART
40	default y
41
42config ESPI_PERIPHERAL_UART_SOC_MAPPING
43	int "SoC port exposed as logical eSPI UART"
44	default 2 if SOC_SERIES_MEC15XX
45	default 1 if SOC_SERIES_MEC172X
46	depends on ESPI_PERIPHERAL_UART
47	help
48	  This tells the driver to which SoC UART to direct the UART traffic
49	  send over eSPI from host.
50
51config ESPI_OOB_BUFFER_SIZE
52	int "eSPI OOB channel buffer size in bytes"
53	default 128
54	depends on ESPI_OOB_CHANNEL
55	help
56	  Use minimum RAM buffer size by default but allow applications to
57	  override the value.
58	  Maximum OOB payload is 73 bytes.
59
60config ESPI_FLASH_BUFFER_SIZE
61	int "eSPI Flash channel buffer size in bytes"
62	default 256
63	depends on ESPI_FLASH_CHANNEL
64	help
65	  Use maximum RAM buffer size defined by spec but allow applications
66	  to override if eSPI host doesn't support it.
67
68config ESPI_TAF_XEC
69	bool "XEC Microchip ESPI TAF driver"
70	default y
71	depends on SOC_SERIES_MEC15XX
72	depends on DT_HAS_MICROCHIP_XEC_ESPI_SAF_ENABLED
73	help
74	  Enable the Microchip XEC TAF ESPI driver for MEC15xx family.
75
76config ESPI_TAF_XEC_V2
77	bool "XEC Microchip ESPI TAF V2 driver"
78	default y
79	depends on SOC_SERIES_MEC172X
80	depends on DT_HAS_MICROCHIP_XEC_ESPI_SAF_V2_ENABLED
81	help
82	  Enable the Microchip XEC TAF ESPI driver for MEC172x series.
83
84endif #ESPI_XEC
85
86if ESPI_XEC_V2
87
88config ESPI_XEC_PERIPHERAL_ACPI_SHD_MEM_SIZE
89	int "Host I/O peripheral port size for shared memory in MEC172X series"
90	depends on ESPI_XEC_V2 || ESPI_PERIPHERAL_ACPI_SHM_REGION
91	default 256
92	help
93	  This is the port size used by the Host and EC to communicate over
94	  the shared memory region to return the ACPI response data.
95
96config ESPI_XEC_PERIPHERAL_HOST_CMD_PARAM_SIZE
97	int "Host I/O peripheral port size for ec host command in MEC172X series"
98	depends on ESPI_XEC_V2 || ESPI_PERIPHERAL_EC_HOST_CMD
99	default 256
100	help
101	  This is the port size used by the Host and EC to communicate over
102	  the shared memory region to return the host command parameter data.
103
104config ESPI_PERIPHERAL_8042_KBC
105	default y
106
107if ESPI_PERIPHERAL_CHANNEL
108
109config ESPI_PERIPHERAL_XEC_MAILBOX
110	bool "SoC Mailbox over eSPI"
111	help
112	  Enable a 32 byte mailbox interface accessible via Host I/O over the
113	  ESPI Peripheral Channel.
114
115config ESPI_PERIPHERAL_XEC_ACPI_EC2
116	bool "SoC ACPI EC 2 over eSPI"
117	help
118	  Enable ACPI EC2 interface accessible via Host I/O over the
119	  ESPI Peripheral Channel.
120
121config ESPI_PERIPHERAL_XEC_ACPI_EC3
122	bool "SoC ACPI EC 3 over eSPI"
123	help
124	  Enable ACPI EC3 interface accessible via Host I/O over the
125	  ESPI Peripheral Channel.
126
127config ESPI_PERIPHERAL_XEC_ACPI_EC4
128	bool "SoC ACPI EC 4 over eSPI"
129	help
130	  Enable ACPI EC4 interface accessible via Host I/O over the
131	  ESPI Peripheral Channel.
132
133config ESPI_PERIPHERAL_XEC_ACPI_PM1
134	bool "SoC ACPI PM1 over eSPI"
135	help
136	  Enable ACPI PM1 interface accessible via Host I/O over the
137	  ESPI Peripheral Channel.
138
139config ESPI_PERIPHERAL_XEC_EMI0
140	bool "SoC EMI 0 over eSPI"
141	help
142	  Enable EMI 0 interface accessible via Host I/O over the
143	  ESPI Peripheral Channel.
144
145config ESPI_PERIPHERAL_XEC_EMI1
146	bool "SoC EMI 1 over eSPI"
147	help
148	  Enable EMI 1 interface accessible via Host I/O over the
149	  ESPI Peripheral Channel.
150
151config ESPI_PERIPHERAL_XEC_EMI2
152	bool "SoC EMI 2 over eSPI"
153	help
154	  Enable EMI 2 interface accessible via Host I/O over the
155	  ESPI Peripheral Channel.
156
157endif #ESPI_PERIPHERAL_CHANNEL
158
159config ESPI_TAF
160	bool "XEC Microchip ESPI TAF driver"
161	depends on ESPI_FLASH_CHANNEL
162	help
163	  Enable Target Attached Flash eSPI driver. TAF depends upon ESPI XEC driver
164	  and flash channel.
165
166config ESPI_TAF_INIT_PRIORITY
167	int "ESPI TAF driver initialization priority"
168	depends on ESPI_TAF
169	default 4
170	help
171	  Driver initialization priority for ESPI TAF driver.
172
173config ESPI_PERIPHERAL_ACPI_EC_IBF_EVT_DATA
174	bool "Read ACPI EC Event Data in IBF ISR"
175	depends on ESPI_PERIPHERAL_CHANNEL
176	help
177	  Enable reading event data in ACPI EC IBF ISR. This is used in OS
178	  environment where application expects IBF ISR to read data and pass
179	  to callback.
180
181endif #ESPI_XEC_V2
182
183if ESPI_XEC_V2 && ESPI_PERIPHERAL_8042_KBC
184
185config ESPI_PERIPHERAL_KBC_IBF_EVT_DATA
186	bool "KBC event data format in IBF"
187	help
188	  Enable espi_evt_data_kbc format for encoding event in KBC IBF ISR
189
190config ESPI_PERIPHERAL_KBC_OBE_CBK
191	bool "KBC OBE Callback"
192	help
193	  Enable KBC OBE callback from OBE ISR
194
195endif #ESPI_XEC_V2 && ESPI_PERIPHERAL_8042_KBC
196