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/Zephyr-latest/dts/bindings/dai/
Dnxp,dai-sai.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,dai-sai"
8 include: [base.yaml, pinctrl-device.yaml]
13 mclk-is-output:
16 Use this property to set the SAI MCLK as output or as input.
17 By default, if this property is not specified, MCLK will be
18 set as input. Setting the MCLK as output for SAIs which don't
19 support MCLK configuration will result in a BUILD_ASSERT()
21 rx-fifo-watermark:
28 tx-fifo-watermark:
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/Zephyr-latest/dts/bindings/clock/
Dnuvoton,npcm-pcc.yaml2 # SPDX-License-Identifier: Apache-2.0
6 Besides power management, this node is also in charge of configuring the
7 Oscillator Frequency Multiplier Clock (OFMCLK), which is derived from
8 High-Frequency Clock Generator (HFCG), is the source clock of Cortex-M4 core
11 Here is an example of configuring OFMCLK and the other clock sources derived
14 clock-frequency = <DT_FREQ_M(96)>; /* OFMCLK runs at 96MHz */
15 core-prescaler = <1>; /* CORE_CLK runs at 96MHz */
16 apb1-prescaler = <8>; /* APB1_CLK runs at 12MHz */
17 apb2-prescaler = <1>; /* APB2_CLK runs at 96MHz */
18 apb3-prescaler = <1>; /* APB3_CLK runs at 96MHz */
[all …]
Dnuvoton,npcx-pcc.yaml2 # SPDX-License-Identifier: Apache-2.0
6 Besides power management, this node is also in charge of configuring the
7 Oscillator Frequency Multiplier Clock (OFMCLK), which is derived from
8 High-Frequency Clock Generator (HFCG), is the source clock of Cortex-M4 core
11 Here is an example of configuring OFMCLK and the other clock sources derived
14 clock-frequency = <DT_FREQ_M(100)>; /* OFMCLK runs at 100MHz */
15 core-prescaler = <5>; /* CORE_CLK runs at 20MHz */
16 apb1-prescaler = <5>; /* APB1_CLK runs at 20MHz */
17 apb2-prescaler = <5>; /* APB2_CLK runs at 20MHz */
18 apb3-prescaler = <5>; /* APB3_CLK runs at 20MHz */
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/Zephyr-latest/drivers/dai/nxp/sai/
DKconfig.sai2 # SPDX-License-Identifier: Apache-2.0
15 bool "Set if SAI has MCLK configuration options"
21 setting the signal as input or output or dividing
22 the master clock output.
32 bool "Set if your SAI IP version is affected by i.MX93's ERRATA 051421"
35 Select this if your SAI ip version is affected by
37 the SAI is FSYNC/BCLK master, one of the directions
38 is SYNC with the other, and the ASYNC direction has
/Zephyr-latest/dts/xtensa/nxp/
Dnxp_imx8m.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/clock/imx_ccm.h>
13 #address-cells = <1>;
14 #size-cells = <0>;
18 compatible = "cdns,tensilica-xtensa-lx6";
21 #address-cells = <1>;
22 #size-cells = <0>;
24 clic: interrupt-controller@0 {
25 compatible = "cdns,xtensa-core-intc";
27 interrupt-controller;
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/Zephyr-latest/drivers/dai/intel/ssp/
Ddai-params-intel-ipc4.h4 * SPDX-License-Identifier: Apache-2.0
19 /**< HD/A host output (-> DSP). */
21 /**< HD/A host input (<- DSP). */
23 /**< HD/A host input/output (rsvd for future use). */
26 /**< HD/A link output (DSP ->). */
28 /**< HD/A link input (DSP <-). */
30 /**< HD/A link input/output (rsvd for future use). */
33 /**< DMIC link input (DSP <-). */
36 /**< I2S link output (DSP ->). */
38 /**< I2S link input (DSP <-). */
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Dssp_regs_v1.h4 * SPDX-License-Identifier: Apache-2.0
30 #define SSCR0_DSIZE(x) DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1)
45 #define SSCR0_FRDC(x) DAI_INTEL_SSP_SET_BITS(26, 24, (x) - 1)
58 #define SSCR1_TFT(x) DAI_INTEL_SSP_SET_BITS(9, 6, (x) - 1)
60 #define SSCR1_RFT(x) DAI_INTEL_SSP_SET_BITS(13, 10, (x) - 1)
109 #define SSPSP_DMYSTOP_MASK DAI_INTEL_SSP_MASK(SSPSP_DMYSTOP_BITS - 1, 0)
148 #define SSCR5_FRM_ASRT_CLOCKS(x) (((x) - 1) << 1)
152 #define SFIFOTT_TX(x) ((x) - 1)
153 #define SFIFOTT_RX(x) (((x) - 1) << 16)
166 #define SSCR3_TX(x) DAI_INTEL_SSP_SET_BITS(21, 16, (x) - 1)
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Dssp_regs_v2.h4 * SPDX-License-Identifier: Apache-2.0
31 #define SSCR0_DSIZE(x) DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1)
46 #define SSCR0_FRDC(x) DAI_INTEL_SSP_SET_BITS(26, 24, (x) - 1)
59 #define SSCR1_TFT(x) DAI_INTEL_SSP_SET_BITS(9, 6, (x) - 1)
61 #define SSCR1_RFT(x) DAI_INTEL_SSP_SET_BITS(13, 10, (x) - 1)
110 #define SSPSP_DMYSTOP_MASK DAI_INTEL_SSP_MASK(SSPSP_DMYSTOP_BITS - 1, 0)
149 #define SSCR5_FRM_ASRT_CLOCKS(x) (((x) - 1) << 1)
153 #define SFIFOTT_TX(x) ((x) - 1)
154 #define SFIFOTT_RX(x) (((x) - 1) << 16)
167 #define SSCR3_TX(x) DAI_INTEL_SSP_SET_BITS(21, 16, (x) - 1)
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Dssp_regs_v3.h4 * SPDX-License-Identifier: Apache-2.0
38 #define SSCR0_DSIZE(x) DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1)
53 #define SSCR0_FRDC(x) DAI_INTEL_SSP_SET_BITS(26, 24, (x) - 1)
104 #define SSPSP_DMYSTOP_MASK DAI_INTEL_SSP_MASK(SSPSP_DMYSTOP_BITS - 1, 0)
147 #define SSCR5_FRM_ASRT_CLOCKS(x) (((x) - 1) << 1)
151 #define SFIFOTT_TX(x) ((x) - 1)
152 #define SFIFOTT_RX(x) (((x) - 1) << 16)
165 #define SSCR3_TX(x) DAI_INTEL_SSP_SET_BITS(21, 16, (x) - 1)
166 #define SSCR3_RX(x) DAI_INTEL_SSP_SET_BITS(29, 24, (x) - 1)
201 /* For 8000 Hz rate one sample is transmitted within 125us */
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Dssp.c4 * SPDX-License-Identifier: Apache-2.0
22 #define dai_set_drvdata(dai, data) (dai->priv_data = data)
23 #define dai_get_drvdata(dai) dai->priv_data
24 #define dai_get_plat_data(dai) dai->ssp_plat_data
25 #define dai_get_mn(dai) dai->ssp_plat_data->mn_inst
26 #define dai_get_ftable(dai) dai->ssp_plat_data->ftable
27 #define dai_get_fsources(dai) dai->ssp_plat_data->fsources
28 #define dai_mn_base(dai) dai->ssp_plat_data->mn_inst->base
29 #define dai_base(dai) dai->ssp_plat_data->base
30 #define dai_ip_base(dai) dai->ssp_plat_data->ip_base
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/Zephyr-latest/drivers/i2s/
Di2s_mcux_sai.c2 * Copyright 2021,2023-2024 NXP Semiconductor INC.
5 * SPDX-License-Identifier: Apache-2.0
22 #include <zephyr/dt-bindings/clock/imx_ccm.h>
56 * application provided buffer is queued to in_queue until loaded to DMA.
57 * when DMA channel is idle, buffer is retrieved from in_queue and loaded
58 * to DMA and queued to out_queue. when DMA completes, buffer is retrieved
62 * driver allocates buffer from slab and loads DMA buffer is queued to
63 * in_queue when DMA completes, buffer is retrieved from in_queue
64 * and queued to out_queue when application reads, buffer is read
124 while (k_msgq_get(&strm->in_queue, &buffer, K_NO_WAIT) == 0) { in i2s_purge_stream_buffers()
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/Zephyr-latest/drivers/spi/
Dspi_sam0.c4 * SPDX-License-Identifier: Apache-2.0
30 #ifdef MCLK
31 volatile uint32_t *mclk; member
59 /* SYNCBUSY is a register */ in wait_synchronization()
60 while ((regs->SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_MASK) != 0) { in wait_synchronization()
63 /* SYNCBUSY is a bit */ in wait_synchronization()
64 while ((regs->STATUS.reg & SERCOM_SPI_STATUS_SYNCBUSY) != 0) { in wait_synchronization()
74 const struct spi_sam0_config *cfg = dev->config; in spi_sam0_configure()
75 struct spi_sam0_data *data = dev->data; in spi_sam0_configure()
76 SercomSpi *regs = cfg->regs; in spi_sam0_configure()
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/Zephyr-latest/drivers/audio/
Dtlv320dac310x.c4 * SPDX-License-Identifier: Apache-2.0
25 #define CODEC_OUTPUT_VOLUME_MIN (-78 * 2)
66 const struct codec_driver_config *const dev_cfg = dev->config; in codec_initialize()
68 if (!device_is_ready(dev_cfg->bus.bus)) { in codec_initialize()
70 return -ENODEV; in codec_initialize()
73 if (!gpio_is_ready_dt(&dev_cfg->reset_gpio)) { in codec_initialize()
75 return -ENODEV; in codec_initialize()
84 const struct codec_driver_config *const dev_cfg = dev->config; in codec_configure()
87 if (cfg->dai_type != AUDIO_DAI_TYPE_I2S) { in codec_configure()
89 return -EINVAL; in codec_configure()
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Dwm8904.c4 * SPDX-License-Identifier: Apache-2.0
28 #define DEV_CFG(dev) ((const struct wm8904_driver_config *const)dev->config)
60 return -EINVAL; in wm8904_protocol_config()
69 static int wm8904_audio_fmt_config(const struct device *dev, audio_dai_cfg_t *cfg, uint32_t mclk) in wm8904_audio_fmt_config() argument
75 uint16_t word_size = cfg->i2s.word_size; in wm8904_audio_fmt_config()
77 switch (cfg->i2s.frame_clk_freq) { in wm8904_audio_fmt_config()
106 LOG_WRN("Invalid codec sample rate: %d", cfg->i2s.frame_clk_freq); in wm8904_audio_fmt_config()
107 return -EINVAL; in wm8904_audio_fmt_config()
111 fs = (mclk >> (mclkDiv & 0x1U)) / cfg->i2s.frame_clk_freq; in wm8904_audio_fmt_config()
146 return -EINVAL; in wm8904_audio_fmt_config()
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/Zephyr-latest/include/zephyr/audio/
Dcodec.h4 * SPDX-License-Identifier: Apache-2.0
53 AUDIO_PCM_WIDTH_16_BITS = 16, /**< 16-bit sample width */
54 AUDIO_PCM_WIDTH_20_BITS = 20, /**< 20-bit sample width */
55 AUDIO_PCM_WIDTH_24_BITS = 24, /**< 24-bit sample width */
56 AUDIO_PCM_WIDTH_32_BITS = 32, /**< 32-bit sample width */
75 AUDIO_PROPERTY_OUTPUT_VOLUME, /**< Output volume */
76 AUDIO_PROPERTY_OUTPUT_MUTE, /**< Output mute/unmute */
102 * Configuration is dependent on DAI type
123 uint32_t mclk_freq; /**< MCLK input frequency in Hz */
133 int vol; /**< Volume level (codec-specific) */
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/Zephyr-latest/boards/ti/msp_exp432p401r_launchxl/doc/
Dindex.rst6 The SimpleLink MSP‐EXP432P401R LaunchPad development kit is an easy-to-use evaluation
8 developing on the SimpleLink MSP432 low-power + performance ARM |reg| 32-bit Cortex |reg|-M4F
14 * Low-power ARM Cortex-M4F MSP432P401R
15 * 40-pin LaunchPad development kit standard that leverages the BoosterPack plug-in module ecosystem
16 * XDS110-ET, an open-source onboard debug probe featuring EnergyTrace+ technology and application
21 Details on the MSP-EXP432P401R LaunchXL development board can be found in the
22 MSP-EXP432P401R LaunchXL User's Guide.
27 * The on-board 32-kHz crystal allows for lower LPM3 sleep currents and a higher-precision clock sou…
28 …default internal 32-kHz REFOCLK. Therefore, the presence of the crystal allows the full range of l…
30 * The on-board 48-MHz crystal allows the device to run at its maximum operating speed for MCLK and …
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/Zephyr-latest/soc/nxp/imxrt/imxrt5xx/cm33/
Dsoc.c2 * Copyright 2022-2023, NXP
4 * SPDX-License-Identifier: Apache-2.0
11 * This module provides routines to initialize and support board-level
51 /* Numerator of the SYSPLL0 fractional loop divider is 0 */
53 /* Denominator of the SYSPLL0 fractional loop divider is 1 */
61 /* Numerator of the Audio PLL fractional loop divider is 0 */
63 /* Denominator of the Audio PLL fractional loop divider is 1 */
159 /* enable USB PHY PLL clock, the phy bus clock (480MHz) source is same with USB IP */ in usb_device_clock_init()
176 /* Wait until host_needclk de-asserts */ in usb_device_clock_init()
177 while (SYSCTL0->USB0CLKSTAT & SYSCTL0_USB0CLKSTAT_HOST_NEED_CLKST_MASK) { in usb_device_clock_init()
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/Zephyr-latest/dts/arm/nxp/
Dnxp_imx95_m7.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
8 #include <zephyr/dt-bindings/clock/imx95_clock.h>
9 #include <dt-bindings/i2c/i2c.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "arm,cortex-m7";
22 #address-cells = <1>;
23 #size-cells = <1>;
26 compatible = "arm,armv7m-mpu";
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Dnxp_rt1010.dtsi4 * SPDX-License-Identifier: Apache-2.0
10 flexram,num-ram-banks = <4>;
12 flexram,bank-spec = <FLEXRAM_OCRAM>,
19 clock-frequency = <500000000>;
35 /delete-node/ arm-podf;
37 ipg-podf {
38 clock-div = <4>;
61 irq-shared-offset = <0>;
62 dma-channels = <16>;
67 /* Remove GPIO3-GPIO9, they don't exist on RT1010 */
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Dnxp_rt10xx.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/clock/imx_ccm.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/pwm/pwm.h>
14 #include <zephyr/dt-bindings/memory-controller/nxp,flexram.h>
19 die-temp0 = &tempmon;
23 #address-cells = <1>;
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/Zephyr-latest/doc/releases/
Drelease-notes-3.2.rst13 * Added support for :ref:`bin-blobs` (also see :ref:`west-blobs`).
15 * Converted all supported boards from ``pinmux`` to :ref:`pinctrl-guide`.
31 * CVE-2022-2993: Under embargo until 2022-11-03
33 * CVE-2022-2741: Under embargo until 2022-10-14
50 ``<zephyr/...>`` header paths. The option is still available to facilitate
52 release. The :zephyr_file:`scripts/utils/migrate_includes.py` script is
56 This definition can be used by third-party code to compile code conditional
57 to Zephyr. The definition is already injected by the Zephyr build system.
58 Therefore, any third-party code integrated using the Zephyr build system will
67 * Bluetooth: Applications where :kconfig:option:`CONFIG_BT_EATT` is enabled
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Drelease-notes-3.3.rst14 * Introduced :ref:`USB-C <usbc_api>` device stack with PD (power delivery)
17 CMSIS-DSP as the default backend.
30 * CVE-2023-0359: Under embargo until 2023-04-20
32 * CVE-2023-0779: Under embargo until 2023-04-22
45 * Newlib nano variant is no longer selected by default when
46 :kconfig:option:`CONFIG_NEWLIB_LIBC` is selected.
66 removed in favor of new :dtcompatible:`zephyr,flash-disk` devicetree binding.
71 * Starting from this release ``zephyr-`` prefixed tags won't be created
81 is of the whole file being uploaded (different to the hash used when getting
82 image states). Use of a truncated hash or non-sha256 hash will still work
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/Zephyr-latest/dts/arm64/nxp/
Dnxp_mimx93_a55.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 #include <arm64/armv8-a.dtsi>
10 #include <zephyr/dt-bindings/clock/imx_ccm_rev2.h>
11 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
12 #include <zephyr/dt-bindings/gpio/gpio.h>
13 #include <zephyr/dt-bindings/i2c/i2c.h>
16 #address-cells = <1>;
17 #size-cells = <1>;
20 #address-cells = <1>;
21 #size-cells = <0>;
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/Zephyr-latest/drivers/i3c/
Di3c_npcx.c4 * SPDX-License-Identifier: Apache-2.0
103 #define I3C_BUS_TLOW_PP_MIN_NS 24 /* T_LOW period in push-pull mode */
104 #define I3C_BUS_THigh_PP_MIN_NS 24 /* T_High period in push-pull mode */
105 #define I3C_BUS_TLOW_OD_MIN_NS 200 /* T_LOW period in open-drain mode */
107 #define PPBAUD_DIV_MAX (BIT(GET_FIELD_SZ(NPCX_I3C_MCONFIG_PPBAUD)) - 1) /* PPBAUD divider max */
163 uint8_t ppbaud; /* Push-Pull high period */
164 uint8_t pplow; /* Push-Pull low period */
165 uint8_t odhpp; /* Open-Drain high period */
166 uint8_t odbaud; /* Open-Drain low period */
259 struct npcx_i3c_data *const data = dev->data; in npcx_i3c_mutex_lock()
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