4  * SPDX-License-Identifier: Apache-2.0
25 #define CODEC_OUTPUT_VOLUME_MIN		(-78 * 2)
66 	const struct codec_driver_config *const dev_cfg = dev->config;  in codec_initialize()
68 	if (!device_is_ready(dev_cfg->bus.bus)) {  in codec_initialize()
70 		return -ENODEV;  in codec_initialize()
73 	if (!gpio_is_ready_dt(&dev_cfg->reset_gpio)) {  in codec_initialize()
75 		return -ENODEV;  in codec_initialize()
84 	const struct codec_driver_config *const dev_cfg = dev->config;  in codec_configure()
87 	if (cfg->dai_type != AUDIO_DAI_TYPE_I2S) {  in codec_configure()
89 		return -EINVAL;  in codec_configure()
93 	 * de-assert the reset line and thus enable the codec.  in codec_configure()
95 	gpio_pin_configure_dt(&dev_cfg->reset_gpio, GPIO_OUTPUT_INACTIVE);  in codec_configure()
101 		ret = codec_configure_dai(dev, &cfg->dai_cfg);  in codec_configure()
104 		ret = codec_configure_filters(dev, &cfg->dai_cfg);  in codec_configure()
152 		return -EINVAL;  in codec_set_property()
171 	return -EINVAL;  in codec_set_property()
176 	/* nothing to do because there is nothing cached */  in codec_apply_properties()
183 	struct codec_driver_data *const dev_data = dev->data;  in codec_write_reg()
184 	const struct codec_driver_config *const dev_cfg = dev->config;  in codec_write_reg()
187 	if (dev_data->reg_addr_cache.page != reg.page) {  in codec_write_reg()
188 		i2c_reg_write_byte_dt(&dev_cfg->bus, 0, reg.page);  in codec_write_reg()
189 		dev_data->reg_addr_cache.page = reg.page;  in codec_write_reg()
192 	i2c_reg_write_byte_dt(&dev_cfg->bus, reg.reg_addr, val);  in codec_write_reg()
200 	struct codec_driver_data *const dev_data = dev->data;  in codec_read_reg()
201 	const struct codec_driver_config *const dev_cfg = dev->config;  in codec_read_reg()
204 	if (dev_data->reg_addr_cache.page != reg.page) {  in codec_read_reg()
205 		i2c_reg_write_byte_dt(&dev_cfg->bus, 0, reg.page);  in codec_read_reg()
206 		dev_data->reg_addr_cache.page = reg.page;  in codec_read_reg()
209 	i2c_reg_read_byte_dt(&dev_cfg->bus, reg.reg_addr, val);  in codec_read_reg()
226 	if (cfg->i2s.options & I2S_OPT_BIT_CLK_MASTER) {  in codec_configure_dai()
230 	if (cfg->i2s.options & I2S_OPT_FRAME_CLK_MASTER) {  in codec_configure_dai()
234 	switch (cfg->i2s.word_size) {  in codec_configure_dai()
249 				cfg->i2s.word_size);  in codec_configure_dai()
250 		return -EINVAL;  in codec_configure_dai()
266 	i2s = &cfg->dai_cfg.i2s;  in codec_configure_clocks()
267 	LOG_DBG("MCLK %u Hz PCM Rate: %u Hz", cfg->mclk_freq,  in codec_configure_clocks()
268 			i2s->frame_clk_freq);  in codec_configure_clocks()
270 	if (cfg->mclk_freq <= DAC_PROC_CLK_FREQ_MAX) {  in codec_configure_clocks()
271 		/* use MCLK frequency as the DAC processing clock */  in codec_configure_clocks()
274 		ndac = cfg->mclk_freq / DAC_PROC_CLK_FREQ_MAX;  in codec_configure_clocks()
277 	dac_clk = cfg->mclk_freq / ndac;  in codec_configure_clocks()
280 	osr_multiple = codec_get_osr_multiple(&cfg->dai_cfg);  in codec_configure_clocks()
283 	 * calculate MOD clock such that it is an integer multiple of  in codec_configure_clocks()
284 	 * cfg->i2s.frame_clk_freq and  in codec_configure_clocks()
287 	osr_min = (DAC_MOD_CLK_FREQ_MIN + i2s->frame_clk_freq - 1) /  in codec_configure_clocks()
288 		i2s->frame_clk_freq;  in codec_configure_clocks()
289 	osr_max = DAC_MOD_CLK_FREQ_MAX / i2s->frame_clk_freq;  in codec_configure_clocks()
297 		mod_clk = i2s->frame_clk_freq * osr;  in codec_configure_clocks()
302 		/* check if mdac is an integer */  in codec_configure_clocks()
307 		osr -= osr_multiple;  in codec_configure_clocks()
313 		return -EINVAL;  in codec_configure_clocks()
320 	if (i2s->options & I2S_OPT_BIT_CLK_MASTER) {  in codec_configure_clocks()
321 		bclk_div = osr * mdac / (i2s->word_size * 2U); /* stereo */  in codec_configure_clocks()
322 		if ((bclk_div * i2s->word_size * 2) != (osr * mdac)) {  in codec_configure_clocks()
323 			LOG_ERR("Unable to generate BCLK %u from MCLK %u",  in codec_configure_clocks()
324 				i2s->frame_clk_freq * i2s->word_size * 2U,  in codec_configure_clocks()
325 				cfg->mclk_freq);  in codec_configure_clocks()
326 			return -EINVAL;  in codec_configure_clocks()
341 	if (i2s->options & I2S_OPT_BIT_CLK_MASTER) {  in codec_configure_clocks()
346 	/* calculate MCLK divider to get ~1MHz */  in codec_configure_clocks()
347 	mclk_div = DIV_ROUND_UP(cfg->mclk_freq, 1000000);  in codec_configure_clocks()
348 	/* setup timer clock to be MCLK divided */  in codec_configure_clocks()
351 	LOG_DBG("Timer MCLK Divider: %u", mclk_div);  in codec_configure_clocks()
362 	if (cfg->i2s.frame_clk_freq >= AUDIO_PCM_RATE_192K) {  in codec_configure_filters()
365 				cfg->i2s.frame_clk_freq);  in codec_configure_filters()
366 	} else if (cfg->i2s.frame_clk_freq >= AUDIO_PCM_RATE_96K) {  in codec_configure_filters()
369 				cfg->i2s.frame_clk_freq);  in codec_configure_filters()
373 				cfg->i2s.frame_clk_freq);  in codec_configure_filters()
384 	if (cfg->i2s.frame_clk_freq >= AUDIO_PCM_RATE_192K) {  in codec_get_osr_multiple()
386 	} else if (cfg->i2s.frame_clk_freq >= AUDIO_PCM_RATE_96K) {  in codec_get_osr_multiple()
392 	LOG_INF("PCM Rate: %u OSR Multiple: %u", cfg->i2s.frame_clk_freq,  in codec_get_osr_multiple()
403 	 * AVDD is typically 3.3V  in codec_configure_output()
414 	/* route DAC output to Headphone */  in codec_configure_output()
424 	/* set headphone outputs as line-out */  in codec_configure_output()
449 		return -EINVAL;  in codec_set_output_volume()
453 	vol = -vol;  in codec_set_output_volume()
455 	/* if volume is near floor, set minimum */  in codec_set_output_volume()