1/*
2 * Copyright 2024 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <arm/armv7-m.dtsi>
8#include <zephyr/dt-bindings/clock/imx95_clock.h>
9#include <dt-bindings/i2c/i2c.h>
10#include <mem.h>
11
12/ {
13	cpus {
14		#address-cells = <1>;
15		#size-cells = <0>;
16
17		cpu@0 {
18			device_type = "cpu";
19			compatible = "arm,cortex-m7";
20			reg = <0>;
21
22			#address-cells = <1>;
23			#size-cells = <1>;
24
25			mpu: mpu@e000ed90 {
26				compatible = "arm,armv7m-mpu";
27				reg = <0xe000ed90 0x40>;
28			};
29		};
30	};
31
32	reserved-memory {
33		#address-cells = <1>;
34		#size-cells = <1>;
35
36		scmi_shmem0: memory@44611000 {
37			compatible = "arm,scmi-shmem";
38			reg = <0x44611000 0x80>;
39		};
40	};
41
42	firmware {
43		scmi {
44			compatible = "arm,scmi";
45			shmem = <&scmi_shmem0>;
46			mboxes = <&mu5 0>;
47			mbox-names = "tx";
48
49			#address-cells = <1>;
50			#size-cells = <0>;
51
52			scmi_clk: protocol@14 {
53				compatible = "arm,scmi-clock";
54				reg = <0x14>;
55				#clock-cells = <1>;
56			};
57
58			scmi_iomuxc: protocol@19 {
59				compatible = "arm,scmi-pinctrl";
60				reg = <0x19>;
61
62				pinctrl: pinctrl {
63					compatible = "nxp,imx95-pinctrl", "nxp,imx93-pinctrl";
64				};
65			};
66		};
67	};
68
69	soc {
70		itcm: itcm@0 {
71			compatible = "nxp,imx-itcm";
72			reg = <0x0 DT_SIZE_K(256)>;
73		};
74
75		dtcm: dtcm@20000000 {
76			compatible = "nxp,imx-dtcm";
77			reg = <0x20000000 DT_SIZE_K(256)>;
78		};
79
80		edma2: dma@42000000 {
81			compatible = "nxp,edma";
82			reg = <0x42000000 (DT_SIZE_K(64) * 33)>;
83			valid-channels = <30>, <31>;
84			interrupts = <143 0>, <143 0>;
85			#dma-cells = <2>;
86			status = "disabled";
87		};
88
89		tpm3: pwm@424e0000 {
90			compatible = "nxp,kinetis-tpm";
91			reg = <0x424e0000 0x88>;
92			interrupts = <73 0>;
93			clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>;
94			prescaler = <16>;
95			status = "disabled";
96			#pwm-cells = <3>;
97		};
98
99		tpm4: pwm@424f0000 {
100			compatible = "nxp,kinetis-tpm";
101			reg = <0x424f0000 0x88>;
102			interrupts = <74 0>;
103			clocks = <&scmi_clk IMX95_CLK_TPM4>;
104			prescaler = <16>;
105			status = "disabled";
106			#pwm-cells = <3>;
107		};
108
109		tpm5: pwm@42500000 {
110			compatible = "nxp,kinetis-tpm";
111			reg = <0x42500000 0x88>;
112			interrupts = <75 0>;
113			clocks = <&scmi_clk IMX95_CLK_TPM5>;
114			prescaler = <16>;
115			status = "disabled";
116			#pwm-cells = <3>;
117		};
118
119		tpm6: pwm@42510000 {
120			compatible = "nxp,kinetis-tpm";
121			reg = <0x42510000 0x88>;
122			interrupts = <76 0>;
123			clocks = <&scmi_clk IMX95_CLK_TPM6>;
124			prescaler = <16>;
125			status = "disabled";
126			#pwm-cells = <3>;
127		};
128
129		lpi2c3: i2c@42530000 {
130			compatible = "nxp,lpi2c";
131			clock-frequency = <I2C_BITRATE_STANDARD>;
132			#address-cells = <1>;
133			#size-cells = <0>;
134			reg = <0x42530000 0x4000>;
135			interrupts = <58 0>;
136			clocks = <&scmi_clk IMX95_CLK_LPI2C3>;
137			status = "disabled";
138		};
139
140		lpi2c4: i2c@42540000 {
141			compatible = "nxp,lpi2c";
142			clock-frequency = <I2C_BITRATE_STANDARD>;
143			#address-cells = <1>;
144			#size-cells = <0>;
145			reg = <0x42540000 0x4000>;
146			interrupts = <59 0>;
147			clocks = <&scmi_clk IMX95_CLK_LPI2C4>;
148			status = "disabled";
149		};
150
151		lpuart3: serial@42570000 {
152			compatible = "nxp,imx-lpuart", "nxp,lpuart";
153			reg = <0x42570000 DT_SIZE_K(64)>;
154			interrupts = <64 3>;
155			clocks = <&scmi_clk IMX95_CLK_LPUART3>;
156			status = "disabled";
157		};
158
159		lpuart4: serial@42580000 {
160			compatible = "nxp,imx-lpuart", "nxp,lpuart";
161			reg = <0x42580000 DT_SIZE_K(64)>;
162			interrupts = <65 3>;
163			clocks = <&scmi_clk IMX95_CLK_LPUART4>;
164			status = "disabled";
165		};
166
167		lpuart5: serial@42590000 {
168			compatible = "nxp,imx-lpuart", "nxp,lpuart";
169			reg = <0x42590000 DT_SIZE_K(64)>;
170			interrupts = <66 3>;
171			clocks = <&scmi_clk IMX95_CLK_LPUART5>;
172			status = "disabled";
173		};
174
175		lpuart6: serial@425a0000 {
176			compatible = "nxp,imx-lpuart", "nxp,lpuart";
177			reg = <0x425a0000 DT_SIZE_K(64)>;
178			interrupts = <67 3>;
179			clocks = <&scmi_clk IMX95_CLK_LPUART6>;
180			status = "disabled";
181		};
182
183		sai3: dai@42650000 {
184			compatible = "nxp,dai-sai";
185			reg = <0x42650000 DT_SIZE_K(64)>;
186			clocks = <&scmi_clk IMX95_CLK_SAI3>;
187			clock-names = "mclk1";
188			interrupts = <170 0>;
189			dai-index = <3>;
190			mclk-is-output;
191			dmas = <&edma2 30 60>, <&edma2 31 61>;
192			dma-names = "tx", "rx";
193			status = "disabled";
194		};
195
196		lpuart7: serial@42690000 {
197			compatible = "nxp,imx-lpuart", "nxp,lpuart";
198			reg = <0x42690000 DT_SIZE_K(64)>;
199			interrupts = <68 3>;
200			clocks = <&scmi_clk IMX95_CLK_LPUART7>;
201			status = "disabled";
202		};
203
204		lpuart8: serial@426a0000 {
205			compatible = "nxp,imx-lpuart", "nxp,lpuart";
206			reg = <0x426a0000 DT_SIZE_K(64)>;
207			interrupts = <69 3>;
208			clocks = <&scmi_clk IMX95_CLK_LPUART8>;
209			status = "disabled";
210		};
211
212		lpi2c5: i2c@426b0000 {
213			compatible = "nxp,lpi2c";
214			clock-frequency = <I2C_BITRATE_STANDARD>;
215			#address-cells = <1>;
216			#size-cells = <0>;
217			reg = <0x426b0000 0x4000>;
218			interrupts = <181 0>;
219			clocks = <&scmi_clk IMX95_CLK_LPI2C5>;
220			status = "disabled";
221		};
222
223		lpi2c6: i2c@426c0000 {
224			compatible = "nxp,lpi2c";
225			clock-frequency = <I2C_BITRATE_STANDARD>;
226			#address-cells = <1>;
227			#size-cells = <0>;
228			reg = <0x426c0000 0x4000>;
229			interrupts = <182 0>;
230			clocks = <&scmi_clk IMX95_CLK_LPI2C6>;
231			status = "disabled";
232		};
233
234		lpi2c7: i2c@426d0000 {
235			compatible = "nxp,lpi2c";
236			clock-frequency = <I2C_BITRATE_STANDARD>;
237			#address-cells = <1>;
238			#size-cells = <0>;
239			reg = <0x426d0000 0x4000>;
240			interrupts = <183 0>;
241			clocks = <&scmi_clk IMX95_CLK_LPI2C7>;
242			status = "disabled";
243		};
244
245		lpi2c8: i2c@426e0000 {
246			compatible = "nxp,lpi2c";
247			clock-frequency = <I2C_BITRATE_STANDARD>;
248			#address-cells = <1>;
249			#size-cells = <0>;
250			reg = <0x426e0000 0x4000>;
251			interrupts = <184 0>;
252			clocks = <&scmi_clk IMX95_CLK_LPI2C8>;
253			status = "disabled";
254		};
255
256		tpm1: pwm@44310000 {
257			compatible = "nxp,kinetis-tpm";
258			reg = <0x44310000 0x88>;
259			interrupts = <29 0>;
260			clocks = <&scmi_clk IMX95_CLK_BUSAON>;
261			prescaler = <16>;
262			status = "disabled";
263			#pwm-cells = <3>;
264		};
265
266		tpm2: pwm@44320000 {
267			compatible = "nxp,kinetis-tpm";
268			reg = <0x44320000 0x88>;
269			interrupts = <30 0>;
270			clocks = <&scmi_clk IMX95_CLK_TPM2>;
271			prescaler = <16>;
272			status = "disabled";
273			#pwm-cells = <3>;
274		};
275
276		lpi2c1: i2c@44340000 {
277			compatible = "nxp,lpi2c";
278			clock-frequency = <I2C_BITRATE_STANDARD>;
279			#address-cells = <1>;
280			#size-cells = <0>;
281			reg = <0x44340000 0x4000>;
282			interrupts = <13 0>;
283			clocks = <&scmi_clk IMX95_CLK_LPI2C1>;
284			status = "disabled";
285		};
286
287		lpi2c2: i2c@44350000 {
288			compatible = "nxp,lpi2c";
289			clock-frequency = <I2C_BITRATE_STANDARD>;
290			#address-cells = <1>;
291			#size-cells = <0>;
292			reg = <0x44350000 0x4000>;
293			interrupts = <14 0>;
294			clocks = <&scmi_clk IMX95_CLK_LPI2C2>;
295			status = "disabled";
296		};
297
298		lpuart1: serial@44380000 {
299			compatible = "nxp,imx-lpuart", "nxp,lpuart";
300			reg = <0x44380000 DT_SIZE_K(64)>;
301			interrupts = <19 3>;
302			clocks = <&scmi_clk IMX95_CLK_LPUART1>;
303			status = "disabled";
304		};
305
306		lpuart2: serial@44390000 {
307			compatible = "nxp,imx-lpuart", "nxp,lpuart";
308			reg = <0x44390000 DT_SIZE_K(64)>;
309			interrupts = <20 3>;
310			clocks = <&scmi_clk IMX95_CLK_LPUART2>;
311			status = "disabled";
312		};
313
314		mu5: mailbox@44610000 {
315			compatible = "nxp,mbox-imx-mu";
316			reg = <0x44610000 DT_SIZE_K(4)>;
317			interrupts = <205 0>;
318			#mbox-cells = <1>;
319		};
320	};
321};
322
323&nvic {
324	arm,num-irq-priority-bits = <4>;
325};
326