Searched +full:interrupt +full:- +full:parent (Results 1 – 25 of 268) sorted by relevance
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| /Zephyr-latest/dts/riscv/openisa/ |
| D | rv32m1_ri5cy.dtsi | 3 * SPDX-License-Identifier: Apache-2.0
11 system-lptmr = &lptmr0;
15 /delete-node/ cpu@1;
21 compatible = "fixed-partitions";
22 #address-cells = <1>;
23 #size-cells = <1>;
57 interrupt-parent = <&event0>;
62 interrupt-parent = <&event0>;
67 interrupt-parent = <&event0>;
71 interrupt-parent = <&event0>;
[all …]
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| D | rv32m1_zero_riscy.dtsi | 3 * SPDX-License-Identifier: Apache-2.0
11 system-lptmr = &lptmr2;
15 /delete-node/ cpu@0;
21 compatible = "fixed-partitions";
22 #address-cells = <1>;
23 #size-cells = <1>;
52 /delete-node/ &intmux0;
59 interrupt-parent = <&event1>;
64 interrupt-parent = <&event1>;
68 interrupt-parent = <&event1>;
[all …]
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| /Zephyr-latest/tests/drivers/counter/counter_basic_api/sysbuild/vpr_launcher/boards/ |
| D | nrf54h20dk_nrf54h20_cpuapp.overlay | 1 /* SPDX-License-Identifier: Apache-2.0 */
5 interrupt-parent = <&cpuppr_clic>;
10 interrupt-parent = <&cpuppr_clic>;
15 interrupt-parent = <&cpuppr_clic>;
20 interrupt-parent = <&cpuppr_clic>;
25 interrupt-parent = <&cpuppr_clic>;
30 interrupt-parent = <&cpuppr_clic>;
35 interrupt-parent = <&cpuppr_clic>;
40 interrupt-parent = <&cpuppr_clic>;
45 interrupt-parent = <&cpuppr_clic>;
[all …]
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| /Zephyr-latest/dts/x86/intel/ |
| D | gpio_common.dtsi | 3 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
8 #include <zephyr/dt-bindings/acpi/acpi.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
15 interrupt-parent = <&intc>;
17 gpio-controller;
18 #gpio-cells = <2>;
24 interrupt-parent = <&intc>;
26 gpio-controller;
27 #gpio-cells = <2>;
[all …]
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| D | elkhart_lake.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
9 #include <zephyr/dt-bindings/i2c/i2c.h>
10 #include <zephyr/dt-bindings/pcie/pcie.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "intel,elkhart-lake", "intel,x86_64";
20 d-cache-line-size = <64>;
38 #address-cells = <1>;
39 #interrupt-cells = <3>;
[all …]
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| D | raptor_lake_p.dtsi | 3 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
8 #include <zephyr/dt-bindings/pcie/pcie.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
18 compatible = "intel,raptor-lake", "intel,x86_64";
20 d-cache-line-size = <64>;
33 interrupt-controller;
[all …]
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| D | raptor_lake_s.dtsi | 3 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
8 #include <zephyr/dt-bindings/i2c/i2c.h>
9 #include <zephyr/dt-bindings/pcie/pcie.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "intel,raptor-lake", "intel,x86_64";
20 d-cache-line-size = <64>;
33 #address-cells = <1>;
[all …]
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| D | intel_ish5.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
8 #include <dt-bindings/interrupt-controller/intel-ioapic.h>
9 #include <dt-bindings/i2c/i2c.h>
13 power-states {
15 compatible = "zephyr,power-state";
16 power-state-name = "runtime-idle";
17 min-residency-us = <500>;
18 substate-id = <1>;
22 compatible = "zephyr,power-state";
23 power-state-name = "suspend-to-ram";
[all …]
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| /Zephyr-latest/tests/kernel/interrupt/ |
| D | multilevel_irq.overlay | 3 * SPDX-License-Identifier: Apache-2.0
8 #address-cells = < 0x1 >;
9 #size-cells = < 0x1 >;
11 test_cpu_intc: interrupt-controller {
12 compatible = "vnd,cpu-intc";
13 #address-cells = <0>;
14 #interrupt-cells = < 0x01 >;
15 interrupt-controller;
18 test_l1_irq: interrupt-controller@bbbbcccc {
21 interrupt-controller;
[all …]
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| /Zephyr-latest/dts/arc/synopsys/ |
| D | emsk.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/i2c/i2c.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
15 #address-cells = <1>;
16 #size-cells = <0>;
25 intc: arcv2-intc {
26 compatible = "snps,arcv2-intc";
27 interrupt-controller;
28 #interrupt-cells = <2>;
32 compatible = "snps,arc-timer";
[all …]
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| D | arc_iot.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/i2c/i2c.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
24 intc: arcv2-intc {
25 compatible = "snps,arcv2-intc";
26 interrupt-controller;
27 #interrupt-cells = <2>;
31 compatible = "snps,arc-timer";
[all …]
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| /Zephyr-latest/drivers/interrupt_controller/ |
| D | Kconfig.cavs | 1 # CAVS interrupt controller configuration
4 # SPDX-License-Identifier: Apache-2.0
7 bool "CAVS Interrupt Logic"
21 the ISRs for CAVS Interrupt Controller are assigned.
24 int "Parent interrupt number to which CAVS_0 maps"
28 int "Parent interrupt number to which CAVS_1 maps"
32 int "Parent interrupt number to which CAVS_2 maps"
36 int "Parent interrupt number to which CAVS_3 maps"
43 Cavs Interrupt Logic initialization priority.
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| /Zephyr-latest/dts/arm64/nxp/ |
| D | nxp_mimx93_a55.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
9 #include <arm64/armv8-a.dtsi>
10 #include <zephyr/dt-bindings/clock/imx_ccm_rev2.h>
11 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
12 #include <zephyr/dt-bindings/gpio/gpio.h>
13 #include <zephyr/dt-bindings/i2c/i2c.h>
16 #address-cells = <1>;
17 #size-cells = <1>;
20 #address-cells = <1>;
21 #size-cells = <0>;
[all …]
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| /Zephyr-latest/dts/xtensa/espressif/esp32/ |
| D | esp32_common.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/clock/esp32_clock.h>
13 #include <zephyr/dt-bindings/interrupt-controller/esp-xtensa-intmux.h>
14 #include <dt-bindings/pinctrl/esp32-pinctrl.h>
15 #include <zephyr/dt-bindings/pwm/pwm.h>
21 zephyr,flash-controller = &flash;
22 zephyr,bt-hci = &esp32_bt_hci;
[all …]
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| /Zephyr-latest/dts/riscv/microchip/ |
| D | mpfs.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
18 clock-frequency = <0>;
23 hlic0: interrupt-controller {
24 compatible = "riscv,cpu-intc";
25 #address-cells = <0>;
[all …]
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| /Zephyr-latest/dts/arm64/ti/ |
| D | ti_am62x_a53.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
9 #include <arm64/armv8-a.dtsi>
10 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
11 #include <zephyr/dt-bindings/pinctrl/ti-k3-pinctrl.h>
14 #address-cells = <1>;
15 #size-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
23 compatible = "arm,cortex-a53";
33 compatible = "arm,armv8-timer";
[all …]
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| /Zephyr-latest/dts/arm64/broadcom/ |
| D | viper-a72.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm64/armv8-a.dtsi>
8 #include <broadcom/viper-common.dtsi>
10 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "arm,cortex-a72";
25 compatible = "arm,armv8-timer";
26 interrupt-parent = <&gic>;
38 gic: interrupt-controller@42700000 {
[all …]
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| /Zephyr-latest/dts/xtensa/espressif/esp32s3/ |
| D | esp32s3_common.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/clock/esp32s3_clock.h>
13 #include <zephyr/dt-bindings/interrupt-controller/esp32s3-xtensa-intmux.h>
14 #include <dt-bindings/pinctrl/esp32s3-pinctrl.h>
19 die-temp0 = &coretemp;
25 zephyr,flash-controller = &flash;
29 #address-cells = <1>;
[all …]
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| /Zephyr-latest/dts/arm/renesas/rcar/gen3/ |
| D | rcar_gen3_cr7.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-r.dtsi>
9 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
10 #include <zephyr/dt-bindings/clock/renesas_cpg_mssr.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/pwm/pwm.h>
17 #address-cells = <1>;
18 #size-cells = <0>;
22 compatible = "arm,cortex-r7";
[all …]
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| /Zephyr-latest/dts/xtensa/espressif/esp32s2/ |
| D | esp32s2_common.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/clock/esp32s2_clock.h>
13 #include <zephyr/dt-bindings/interrupt-controller/esp32s2-xtensa-intmux.h>
14 #include <dt-bindings/pinctrl/esp32-pinctrl.h>
17 #address-cells = <1>;
18 #size-cells = <1>;
21 die-temp0 = &coretemp;
[all …]
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| /Zephyr-latest/boards/mediatek/mt8195/ |
| D | mt8195_adsp.dts | 2 * SPDX-License-Identifier: Apache-2.0
6 /dts-v1/;
9 #address-cells = <1>;
10 #size-cells = <1>;
14 compatible = "mmio-sram";
20 compatible = "mmio-sram";
25 #address-cells = <1>;
26 #size-cells = <1>;
37 compatible = "cdns,xtensa-core-intc";
39 interrupt-controller;
[all …]
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| /Zephyr-latest/dts/riscv/andes/ |
| D | andes_v5_ae350.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
8 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
16 #address-cells = <1>;
17 #size-cells = <0>;
19 compatible = "andestech,andescore-v5", "riscv";
24 mmu-type = "riscv,sv32";
25 clock-frequency = <60000000>;
[all …]
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| /Zephyr-latest/dts/riscv/espressif/esp32c6/ |
| D | esp32c6_common.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/gpio/gpio.h>
9 #include <zephyr/dt-bindings/i2c/i2c.h>
10 #include <zephyr/dt-bindings/interrupt-controller/esp-esp32c6-intmux.h>
11 #include <zephyr/dt-bindings/clock/esp32c6_clock.h>
12 #include <dt-bindings/pinctrl/esp32c6-pinctrl.h>
15 #address-cells = <1>;
16 #size-cells = <1>;
20 zephyr,flash-controller = &flash;
24 #address-cells = <1>;
[all …]
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| /Zephyr-latest/boards/mediatek/mt8196/ |
| D | mt8196_adsp.dts | 2 * SPDX-License-Identifier: Apache-2.0
6 /dts-v1/;
9 #address-cells = <1>;
10 #size-cells = <1>;
14 compatible = "mmio-sram";
20 compatible = "mmio-sram";
26 compatible = "mmio-sram";
31 #address-cells = <1>;
32 #size-cells = <1>;
35 compatible = "cdns,xtensa-core-intc";
[all …]
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| /Zephyr-latest/dts/riscv/telink/ |
| D | telink_b91.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/adc/b91-adc.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/pwm/pwm.h>
16 #address-cells = <1>;
17 #size-cells = <1>;
20 #address-cells = <1>;
[all …]
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