1/* Copyright 2023 The ChromiumOS Authors 2 * SPDX-License-Identifier: Apache-2.0 3 */ 4#include <mem.h> 5 6/dts-v1/; 7/ { 8 9 #address-cells = <1>; 10 #size-cells = <1>; 11 12 sram0: memory@40000000 { 13 device_type = "memory"; 14 compatible = "mmio-sram"; 15 reg = <0x40000000 DT_SIZE_K(256)>; 16 }; 17 18 dram0: memory@60000000 { 19 device_type = "memory"; 20 compatible = "mmio-sram"; 21 reg = <0x60000000 DT_SIZE_M(17)>; 22 }; 23 24 soc { 25 #address-cells = <1>; 26 #size-cells = <1>; 27 28 cpuclk: cpuclk@10000000 { 29 compatible = "mediatek,mt8195_cpuclk"; 30 reg = <0x10000000 380>; 31 cg_reg = <0x10720180>; 32 pll_ctrl_reg = <0x1000c7e0>; 33 freqs_mhz = <26 370 540 720>; 34 }; 35 36 core_intc: core_intc@0 { 37 compatible = "cdns,xtensa-core-intc"; 38 reg = <0 4>; 39 interrupt-controller; 40 #interrupt-cells = <3>; 41 }; 42 43 intc1: intc@10680130 { 44 compatible = "mediatek,adsp_intc"; 45 interrupt-controller; 46 #interrupt-cells = <3>; 47 reg = <0x10680130 4>; 48 status-reg = <0x10680150>; 49 interrupts = <1 0 0>; 50 mask = <0x3ffffff0>; 51 interrupt-parent = <&core_intc>; 52 }; 53 54 intc23: intc@108030f4 { 55 compatible = "mediatek,adsp_intc"; 56 interrupt-controller; 57 #interrupt-cells = <3>; 58 reg = <0x108030f4 4>; 59 status-reg = <0x108030fc>; 60 interrupts = <23 0 0>; 61 mask = <0xffff>; 62 interrupt-parent = <&core_intc>; 63 }; 64 65 ostimer64: ostimer64@1080d080 { 66 compatible = "mediatek,ostimer64"; 67 reg = <0x1080d080 28>; 68 }; 69 70 ostimer0: ostimer@1080d000 { 71 compatible = "mediatek,ostimer"; 72 reg = <0x1080d000 16>; 73 interrupt-parent = <&intc23>; 74 interrupts = <11 0 0>; 75 }; 76 77 mbox0: mbox@10816000 { 78 compatible = "mediatek,mbox"; 79 reg = <0x10816000 56>; 80 interrupt-parent = <&intc23>; 81 interrupts = <0 0 0>; 82 }; 83 84 mbox1: mbox@10817000 { 85 compatible = "mediatek,mbox"; 86 reg = <0x10817000 56>; 87 interrupt-parent = <&intc23>; 88 interrupts = <1 0 0>; 89 }; 90 }; /* soc */ 91 92 chosen { }; 93 aliases { }; 94}; 95