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/Zephyr-latest/dts/arm/nuvoton/npcx/npcx9/
Dnpcx9-miwus-int-map.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 /* Common MIWU group-interrupt mapping configurations in npcx family */
8 #include <nuvoton/npcx/npcx-miwus-int-map.dtsi>
10 /* Specific MIWU group-interrupt mapping configurations in npcx9 series */
13 npcx-miwus-int-map {
14 map_miwu0_groups: map-miwu0-groups {
15 compatible = "nuvoton,npcx-miwu-int-map";
18 group_a0: group-a0-map {
20 irq-prio = <2>;
21 group-mask = <0x01>;
[all …]
/Zephyr-latest/dts/arm/nuvoton/npcx/npcx4/
Dnpcx4-miwus-int-map.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 /* Common MIWU group-interrupt mapping configurations in npcx family */
8 #include <nuvoton/npcx/npcx-miwus-int-map.dtsi>
10 /* Specific MIWU group-interrupt mapping configurations in npcx4 series */
13 npcx-miwus-int-map {
14 map_miwu0_groups: map-miwu0-groups {
15 compatible = "nuvoton,npcx-miwu-int-map";
18 group_a0: group-a0-map {
20 irq-prio = <2>;
21 group-mask = <0x01>;
[all …]
/Zephyr-latest/dts/arm/nuvoton/npcx/npcx7/
Dnpcx7-miwus-int-map.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 /* Common MIWU group-interrupt mapping configurations in npcx family */
8 #include <nuvoton/npcx/npcx-miwus-int-map.dtsi>
10 /* Specific MIWU group-interrupt mapping configurations in npcx7 series */
13 npcx-miwus-int-map {
14 map_miwu0_groups: map-miwu0-groups {
15 compatible = "nuvoton,npcx-miwu-int-map";
18 group_ad0: group-ad0-map {
20 irq-prio = <2>;
21 group-mask = <0x09>;
[all …]
/Zephyr-latest/drivers/gpio/
Dgpio_cc13xx_cc26xx.c4 * SPDX-License-Identifier: Apache-2.0
14 #include <zephyr/dt-bindings/gpio/ti-cc13xx-cc26xx-gpio.h>
17 #include <driverlib/interrupt.h>
29 /* bits 16-18 in iocfg registers correspond to interrupt settings */
32 /* the rest are for general (non-interrupt) config */
48 uint32_t mask);
50 uint32_t mask);
72 return -ENOTSUP; in gpio_cc13xx_cc26xx_config()
92 return -ENOTSUP; in gpio_cc13xx_cc26xx_config()
106 return -EINVAL; in gpio_cc13xx_cc26xx_config()
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Dgpio_grgpio2.c4 * SPDX-License-Identifier: Apache-2.0
9 * - iflag determine pending interrupt.
10 * - interrupt map decides interrupt number if implemented.
11 * - logic or/and/xor registers used when possible
28 int interrupt; member
45 const struct cfg *cfg = dev->config; in pin_configure()
46 struct data *data = dev->data; in pin_configure()
47 volatile struct grgpio_regs *regs = cfg->regs; in pin_configure()
48 uint32_t mask = 1 << pin; in pin_configure() local
51 return -ENOTSUP; in pin_configure()
[all …]
Dgpio_grgpio.h4 * SPDX-License-Identifier: Apache-2.0
13 uint32_t imask; /* 0x0C Interrupt mask register */
14 uint32_t ipol; /* 0x10 Interrupt polarity register */
15 uint32_t iedge; /* 0x14 Interrupt edge register */
18 uint32_t irqmap[4]; /* 0x20 - 0x2C Interrupt map registers */
23 uint32_t iavail; /* 0x40 Interrupt available register */
24 uint32_t iflag; /* 0x44 Interrupt flag register */
28 uint32_t output_or; /* 0x54 I/O port output register, logical-OR */
29 uint32_t dir_or; /* 0x58 I/O port dir. register, logical-OR */
30 uint32_t imask_or; /* 0x5C Interrupt mask register, logical-OR */
[all …]
Dgpio_emul.c4 * SPDX-License-Identifier: Apache-2.0
27 * @brief GPIO Emulator interrupt capabilities
30 * model GPIO interrupt controllers with varying interrupt trigger support.
91 /** Interrupt status for each pin */
95 /** Is interrupt enabled for each pin */
97 /** Singly-linked list of callbacks associated with the controller */
102 * @brief Obtain a mask of pins that match all of the provided @p flags
109 * @param mask A mask of flags to match
112 * @return a mask of the pins with matching @p flags
115 get_pins_with_flags(const struct device *port, gpio_port_pins_t mask, in get_pins_with_flags() argument
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Dgpio_nxp_s32.c2 * Copyright 2022-2024 NXP
4 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/dt-bindings/gpio/nxp-s32-gpio.h>
33 #define GPIO_READ(r) sys_read16(config->gpio_base + (r))
34 #define GPIO_WRITE(r, v) sys_write16((v), config->gpio_base + (r))
35 #define PORT_READ(p) sys_read32(config->port_base + SIUL2_MSCR(p))
36 #define PORT_WRITE(p, v) sys_write32((v), config->port_base + SIUL2_MSCR(p))
49 struct gpio_nxp_s32_irq_map *map; member
86 const struct gpio_nxp_s32_config *config = dev->config; in nxp_s32_gpio_configure()
91 return -ENOTSUP; in nxp_s32_gpio_configure()
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Dgpio_andes_atcgpio100.c4 * SPDX-License-Identifier: Apache-2.0
16 #include <zephyr/dt-bindings/gpio/andestech-atcgpio100.h>
35 #define REG_INTE 0x50 /* Interrupt enable reg. */
36 #define REG_IMD0 0x54 /* Interrupt mode 0 ~ 7 reg. */
37 #define REG_IMD1 0x58 /* Interrupt mode 8 ~ 15 reg. */
38 #define REG_IMD2 0x5C /* Interrupt mode 16 ~ 23 reg. */
39 #define REG_IMD3 0x60 /* Interrupt mode 24 ~ 31 reg. */
40 #define REG_ISTA 0x64 /* Interrupt status reg. */
41 #define REG_DEBE 0x70 /* De-bounce enable reg. */
42 #define REG_DEBC 0x74 /* De-Bounce control reg. */
[all …]
Dgpio_mchp_xec_v2.c4 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/dt-bindings/gpio/gpio.h>
15 #include <zephyr/dt-bindings/pinctrl/mchp-xec-pinctrl.h>
52 /* Each GPIO pin 32-bit control register located consecutively in memory */
55 const struct gpio_xec_config *config = dev->config; in pin_ctrl_addr()
57 return config->pcr1_base + ((uintptr_t)pin * 4u); in pin_ctrl_addr()
60 /* GPIO Parallel input is a single 32-bit register per bank of 32 pins */
63 const struct gpio_xec_config *config = dev->config; in pin_parin_addr()
65 return config->parin_addr; in pin_parin_addr()
68 /* GPIO Parallel output is a single 32-bit register per bank of 32 pins */
[all …]
Dgpio_sifive.c2 * Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
4 * SPDX-License-Identifier: Apache-2.0
26 /* sifive GPIO register-set structure */
51 /* multi-level encoded interrupt corresponding to pin 0 */
65 ((const struct gpio_sifive_config * const)(dev)->config)
67 ((volatile struct gpio_sifive_t *)(DEV_GPIO_CFG(dev))->gpio_base_addr)
69 ((struct gpio_sifive_data *)(dev)->data)
88 * with the interrupt
98 return (plic_irq - base_irq); in gpio_sifive_plic_to_pin()
107 /* Calculate pin and mask from base level 2 line */ in gpio_sifive_irq_handler()
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/Zephyr-latest/dts/bindings/pcie/host/
Dpci-host-ecam-generic.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "pci-host-ecam-generic"
8 include: pcie-controller.yaml
14 msi-parent:
21 As described in IEEE Std 1275-1994, but must provide at least a
22 definition of non-prefetchable memory. One or both of prefetchable Memory
25 interrupt-map-mask:
28 interrupt-map:
31 bus-range:
/Zephyr-latest/dts/riscv/
Dneorv32.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
10 #include <zephyr/dt-bindings/gpio/gpio.h>
18 #address-cells = <1>;
19 #size-cells = <0>;
22 compatible = "neorv32-cpu", "riscv";
27 intc: interrupt-controller {
28 compatible = "riscv,cpu-intc";
29 interrupt-controller;
30 #address-cells = <1>;
[all …]
/Zephyr-latest/dts/bindings/interrupt-controller/
Dnuvoton,npcx-miwu-int-map.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: NPCX-MIWU group-interrupt mapping child node
6 compatible: "nuvoton,npcx-miwu-int-map"
14 child-binding:
15 description: Child node to present the mapping between MIWU group and interrupt
21 irq-prio:
25 group-mask:
28 description: group bit-mask for miwu interrupts
31 description: groups shared the same interrupt
/Zephyr-latest/samples/drivers/ethernet/eth_ivshmem/boards/
Dqemu_cortex_a53.overlay4 * SPDX-License-Identifier: Apache-2.0
9 /delete-node/ memory@40000000;
12 compatible = "mmio-sram";
16 /delete-node/ pcie@4010000000;
19 compatible = "pci-host-ecam-generic";
22 #size-cells = <0x02>;
23 #address-cells = <0x03>;
25 #interrupt-cells = <0x01>;
26 interrupt-map-mask = <0x00 0x00 0x00 0x07>;
27 interrupt-map = <
[all …]
/Zephyr-latest/include/zephyr/drivers/pcie/
Dmsi.h4 * SPDX-License-Identifier: Apache-2.0
68 * @param priority the MSI vectors base interrupt priority
84 * @param routine Interrupt service routine
86 * @param flags Arch-specific IRQ configuration flag
106 * @return A (32-bit) value for the MSI MAP register.
119 * @return A (16-bit) value for MSI MDR register.
139 * @brief Check if the given PCI endpoint supports MSI/MSI-X
142 * @return true if the endpoint support MSI/MSI-X
154 #define PCIE_MSI_MCR_MMC 0x000E0000U /* Multi Messages Capable mask */
156 #define PCIE_MSI_MCR_MME 0x00700000U /* mask of # of enabled IRQs */
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/Zephyr-latest/drivers/serial/
Duart_pl011_registers.h6 * SPDX-License-Identifier: Apache-2.0
15 * UART PL011 register map structure
45 #define PL011_BIT_MASK(x, y) (((2 << x) - 1) << y)
48 #define PL011_FR_CTS BIT(0) /* clear to send - inverted */
49 #define PL011_FR_DSR BIT(1) /* data set ready - inverted */
50 #define PL011_FR_DCD BIT(2) /* data carrier detect - inverted */
56 #define PL011_FR_RI BIT(8) /* ring indicator - inverted */
84 #define PL011_LCRH_WLEN_SIZE(x) (x - 5)
108 /* PL011 Control Register - vendor-specific fields */
118 /* PL011 Interrupt Fifo Level Select Register */
[all …]
/Zephyr-latest/scripts/dts/python-devicetree/tests/
Dtest.dts4 * SPDX-License-Identifier: BSD-3-Clause
9 /dts-v1/;
16 interrupt-parent-test {
18 compatible = "interrupt-three-cell";
19 #interrupt-cells = <3>;
20 interrupt-controller;
24 interrupt-names = "foo", "bar";
25 interrupt-parent = <&{/interrupt-parent-test/controller}>;
28 interrupts-extended-test {
29 controller-0 {
[all …]
/Zephyr-latest/drivers/sensor/bosch/bmi08x/
Dbmi08x.h5 * SPDX-License-Identifier: Apache-2.0
53 /* Accel Interrupt status0 register */
56 /* Accel Interrupt status1 register */
80 /* Accel Interrupt pin 1 configuration register */
83 /* Accel Interrupt pin 2 configuration register */
86 /* Accel Interrupt latch configuration register */
89 /* Accel Interrupt pin1 mapping register */
92 /* Accel Interrupt pin2 mapping register */
95 /* Accel Interrupt map register */
124 /* Interrupt masks */
[all …]
/Zephyr-latest/dts/x86/intel/
Dapollo_lake.dtsi2 * Copyright (c) 2017-2019 Intel Corporation.
4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
9 #include <zephyr/dt-bindings/i2c/i2c.h>
10 #include <zephyr/dt-bindings/pcie/pcie.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "intel,apollo-lake", "intel,x86_64";
20 d-cache-line-size = <64>;
33 #address-cells = <1>;
[all …]
/Zephyr-latest/boards/nxp/mimxrt1050_evk/
Dmimxrt1050_evk.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
10 #include "mimxrt1050_evk-pinctrl.dtsi"
11 #include <zephyr/dt-bindings/input/input-event-codes.h>
14 model = "NXP MIMXRT1050-EVK board";
24 mcuboot-button0 = &user_button;
31 zephyr,uart-mcumgr = &lpuart1;
33 zephyr,shell-uart = &lpuart1;
37 /* Micron MT48LC16M16A2B4-6AIT:G */
47 nxp_parallel_lcd_connector: parallel-connector {
[all …]
/Zephyr-latest/boards/nxp/mimxrt1040_evk/
Dmimxrt1040_evk.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
10 #include "mimxrt1040_evk-pinctrl.dtsi"
11 #include <zephyr/dt-bindings/input/input-event-codes.h>
14 model = "NXP MIMXRT1040-EVK board";
20 pwm-0 = &flexpwm1_pwm3;
22 mcuboot-button0 = &user_button;
30 zephyr,shell-uart = &lpuart1;
32 zephyr,flash-controller = &w25q64jvssiq;
33 zephyr,code-partition = &slot0_partition;
[all …]
/Zephyr-latest/drivers/ethernet/phy/
Dphy_dm8806_priv.h4 * SPDX-License-Identifier: Apache-2.0
9 /* 10 Mbit/s transfer with half duplex mask. */
11 /* 10 Mbit/s transfer with full duplex mask. */
13 /* 100 Mbit/s transfer with half duplex mask. */
15 /* 100 Mbit/s transfer with full duplex mask. */
38 /* Speed and duplex mode staus mask. */
40 /* Link status mask. */
53 /* Address Table Command Result flag mask */
78 /* Port number or port map mask*/
109 /* Interrupt Status Register PHY Address. */
[all …]
/Zephyr-latest/dts/arm64/qemu/
Dqemu-virt-arm64.dtsi4 * SPDX-License-Identifier: Apache-2.0
10 * qemu-system-aarch64 -machine virt,gic-version=host,accel=kvm
11 * -cpu cortex-a53 -nographic -machine dumpdtb=virt.dtb
13 * dtc -I dtb -O dts virt.dtb
17 #include <arm64/armv8-a.dtsi>
18 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
19 #include <zephyr/dt-bindings/pcie/pcie.h>
22 #address-cells = <2>;
23 #size-cells = <2>;
26 #address-cells = <1>;
[all …]
Dqemu-virt-a53.dtsi4 * SPDX-License-Identifier: Apache-2.0
10 * qemu-system-aarch64 -machine virt -cpu cortex-a53 -nographic
11 * -machine dumpdtb=virt.dtb
13 * dtc -I dtb -O dts virt.dtb
17 #include <arm64/armv8-a.dtsi>
18 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
19 #include <zephyr/dt-bindings/pcie/pcie.h>
22 #address-cells = <2>;
23 #size-cells = <2>;
26 #address-cells = <1>;
[all …]

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