Lines Matching +full:interrupt +full:- +full:map +full:- +full:mask
4 * SPDX-License-Identifier: Apache-2.0
68 * @param priority the MSI vectors base interrupt priority
84 * @param routine Interrupt service routine
86 * @param flags Arch-specific IRQ configuration flag
106 * @return A (32-bit) value for the MSI MAP register.
119 * @return A (16-bit) value for MSI MDR register.
139 * @brief Check if the given PCI endpoint supports MSI/MSI-X
142 * @return true if the endpoint support MSI/MSI-X
154 #define PCIE_MSI_MCR_MMC 0x000E0000U /* Multi Messages Capable mask */
156 #define PCIE_MSI_MCR_MME 0x00700000U /* mask of # of enabled IRQs */
158 #define PCIE_MSI_MCR_64 0x00800000U /* 64-bit MSI */
161 * The MAP follows the MCR. If PCIE_MSI_MCR_64, then the MAP
162 * is two words long. The MDR follows immediately after the MAP.
171 * As for MSI, he first word of the MSI-X capability is shared
177 #define PCIE_MSIX_MCR_EN 0x80000000U /* Enable MSI-X */
178 #define PCIE_MSIX_MCR_FMASK 0x40000000U /* Function Mask */
179 #define PCIE_MSIX_MCR_TSIZE 0x07FF0000U /* Table size mask */
184 #define PCIE_MSIX_TR_BIR 0x00000007U /* Table BIR mask */
185 #define PCIE_MSIX_TR_OFFSET 0xFFFFFFF8U /* Offset mask */
188 #define PCIE_MSIX_PBA_BIR 0x00000007U /* PBA BIR mask */
189 #define PCIE_MSIX_PBA_OFFSET 0xFFFFFFF8U /* Offset mask */