4  * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/dt-bindings/gpio/gpio.h>
15 #include <zephyr/dt-bindings/pinctrl/mchp-xec-pinctrl.h>
52 /* Each GPIO pin 32-bit control register located consecutively in memory */
55 	const struct gpio_xec_config *config = dev->config;  in pin_ctrl_addr()
57 	return config->pcr1_base + ((uintptr_t)pin * 4u);  in pin_ctrl_addr()
60 /* GPIO Parallel input is a single 32-bit register per bank of 32 pins */
63 	const struct gpio_xec_config *config = dev->config;  in pin_parin_addr()
65 	return config->parin_addr;  in pin_parin_addr()
68 /* GPIO Parallel output is a single 32-bit register per bank of 32 pins */
71 	const struct gpio_xec_config *config = dev->config;  in pin_parout_addr()
73 	return config->parout_addr;  in pin_parout_addr()
78  * reg32(addr) = (reg32(addr) & ~mask) | (val & mask)
80 static inline void xec_mask_write32(uintptr_t addr, uint32_t mask, uint32_t val)  in xec_mask_write32()  argument
82 	uint32_t r = (sys_read32(addr) & ~mask) | (val & mask);  in xec_mask_write32()
88  * NOTE: gpio_flags_t b[15:0] are defined in the dt-binding gpio header.
90  * Hardware only supports push-pull or open-drain.
96 		return -ENOTSUP;  in gpio_xec_validate_flags()
101 		return -ENOTSUP;  in gpio_xec_validate_flags()
105 		return -EINVAL;  in gpio_xec_validate_flags()
112  * Each GPIO pin has two 32-bit control registers. Control 1 configures pin
126 	const struct gpio_xec_config *config = dev->config;  in gpio_xec_configure()
134 	if (!(valid_ctrl_masks[config->port_num] & BIT(pin))) {  in gpio_xec_configure()
135 		return -EINVAL;  in gpio_xec_configure()
149 		LOG_WRN("Port:%d pin:0x%x not in GPIO mode. CTRL[%x]=%x", config->port_num, pin,  in gpio_xec_configure()
210 	 /* Control output bit becomes read-only and parallel out register bit becomes r/w */  in gpio_xec_configure()
220 		return -EINVAL;  in gen_gpio_ctrl_icfg()
244 				return -EINVAL;  in gen_gpio_ctrl_icfg()
256 		/* Enable interrupt to propagate via its GIRQ to the NVIC */  in gpio_xec_intr_en()
266 	const struct gpio_xec_config *config = dev->config;  in gpio_xec_pin_interrupt_configure()
272 	if ((valid_ctrl_masks[config->port_num] & BIT(pin)) == 0U) {  in gpio_xec_pin_interrupt_configure()
273 		return -EINVAL;  in gpio_xec_pin_interrupt_configure()
278 	    ((config->flags & GPIO_INT_ENABLE) == 0)) {  in gpio_xec_pin_interrupt_configure()
279 		return -ENOTSUP;  in gpio_xec_pin_interrupt_configure()
284 		return -EINVAL;  in gpio_xec_pin_interrupt_configure()
287 	/* Disable interrupt in the EC aggregator */  in gpio_xec_pin_interrupt_configure()
288 	mchp_soc_ecia_girq_src_dis(config->girq_id, pin);  in gpio_xec_pin_interrupt_configure()
292 	/* HW detects interrupt on input. Make sure input pad disable is cleared */  in gpio_xec_pin_interrupt_configure()
296 		gpio_xec_intr_en(pin, mode, config->girq_id);  in gpio_xec_pin_interrupt_configure()
326 	mchp_soc_ecia_girq_src_clr(config->girq_id, pin);  in gpio_xec_pin_interrupt_configure()
328 	gpio_xec_intr_en(pin, mode, config->girq_id);  in gpio_xec_pin_interrupt_configure()
334 					uint32_t mask,  in gpio_xec_port_set_masked_raw()  argument
339 	xec_mask_write32(pout_addr, mask, value);  in gpio_xec_port_set_masked_raw()
344 static int gpio_xec_port_set_bits_raw(const struct device *dev, uint32_t mask)  in gpio_xec_port_set_bits_raw()  argument
348 	sys_write32(sys_read32(pout_addr) | mask, pout_addr);  in gpio_xec_port_set_bits_raw()
354 					uint32_t mask)  in gpio_xec_port_clear_bits_raw()  argument
358 	sys_write32(sys_read32(pout_addr) & ~mask, pout_addr);  in gpio_xec_port_clear_bits_raw()
363 static int gpio_xec_port_toggle_bits(const struct device *dev, uint32_t mask)  in gpio_xec_port_toggle_bits()  argument
367 	sys_write32(sys_read32(pout_addr) ^ mask, pout_addr);  in gpio_xec_port_toggle_bits()
384 	struct gpio_xec_data *data = dev->data;  in gpio_xec_manage_callback()
386 	gpio_manage_callback(&data->callbacks, callback, set);  in gpio_xec_manage_callback()
392 static int gpio_xec_get_direction(const struct device *port, gpio_port_pins_t map,  in gpio_xec_get_direction()  argument
396 		return -EINVAL;  in gpio_xec_get_direction()
399 	const struct gpio_xec_config *config = port->config;  in gpio_xec_get_direction()
400 	uint32_t valid_msk = valid_ctrl_masks[config->port_num];  in gpio_xec_get_direction()
405 		if (!map) {  in gpio_xec_get_direction()
408 		if ((map & BIT(pin)) && (valid_msk & BIT(pin))) {  in gpio_xec_get_direction()
420 			map &= ~BIT(pin);  in gpio_xec_get_direction()
432 		return -EINVAL;  in gpio_xec_get_config()
435 	const struct gpio_xec_config *config = port->config;  in gpio_xec_get_config()
436 	uint32_t valid_msk = valid_ctrl_masks[config->port_num];  in gpio_xec_get_config()
439 		return -EINVAL;  in gpio_xec_get_config()
474 	const struct gpio_xec_config *config = dev->config;  in gpio_gpio_xec_port_isr()
475 	struct gpio_xec_data *data = dev->data;  in gpio_gpio_xec_port_isr()
482 	girq_result = mchp_soc_ecia_girq_result(config->girq_id);  in gpio_gpio_xec_port_isr()
485 	mchp_soc_ecia_girq_src_clr_bitmap(config->girq_id, girq_result);  in gpio_gpio_xec_port_isr()
487 	gpio_fire_callbacks(&data->callbacks, dev, girq_result);  in gpio_gpio_xec_port_isr()
518 		const struct gpio_xec_config *config = dev->config;	\
520 		mchp_soc_ecia_girq_aggr_en(config->girq_id, 1);		\