1 /*
2 * Copyright (c) 2019 Intel Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT microchip_xec_gpio_v2
8
9 #include <errno.h>
10 #include <zephyr/arch/cpu.h>
11 #include <zephyr/device.h>
12 #include <zephyr/drivers/gpio.h>
13 #include <zephyr/dt-bindings/gpio/gpio.h>
14 #include <zephyr/logging/log.h>
15 #include <zephyr/dt-bindings/pinctrl/mchp-xec-pinctrl.h>
16 #include <soc.h>
17 #include <zephyr/irq.h>
18
19 #include <zephyr/drivers/gpio/gpio_utils.h>
20
21 #define XEC_GPIO_EDGE_DLY_COUNT 4
22
23 LOG_MODULE_REGISTER(gpio, CONFIG_GPIO_LOG_LEVEL);
24
25 static const uint32_t valid_ctrl_masks[NUM_MCHP_GPIO_PORTS] = {
26 (MCHP_GPIO_PORT_A_BITMAP),
27 (MCHP_GPIO_PORT_B_BITMAP),
28 (MCHP_GPIO_PORT_C_BITMAP),
29 (MCHP_GPIO_PORT_D_BITMAP),
30 (MCHP_GPIO_PORT_E_BITMAP),
31 (MCHP_GPIO_PORT_F_BITMAP),
32 };
33
34 struct gpio_xec_data {
35 /* gpio_driver_data needs to be first */
36 struct gpio_driver_data common;
37 /* port ISR callback routine address */
38 sys_slist_t callbacks;
39 };
40
41 struct gpio_xec_config {
42 /* gpio_driver_config needs to be first */
43 struct gpio_driver_config common;
44 uintptr_t pcr1_base;
45 uintptr_t parin_addr;
46 uintptr_t parout_addr;
47 uint8_t girq_id;
48 uint8_t port_num;
49 uint32_t flags;
50 };
51
52 /* Each GPIO pin 32-bit control register located consecutively in memory */
pin_ctrl_addr(const struct device * dev,gpio_pin_t pin)53 static inline uintptr_t pin_ctrl_addr(const struct device *dev, gpio_pin_t pin)
54 {
55 const struct gpio_xec_config *config = dev->config;
56
57 return config->pcr1_base + ((uintptr_t)pin * 4u);
58 }
59
60 /* GPIO Parallel input is a single 32-bit register per bank of 32 pins */
pin_parin_addr(const struct device * dev)61 static inline uintptr_t pin_parin_addr(const struct device *dev)
62 {
63 const struct gpio_xec_config *config = dev->config;
64
65 return config->parin_addr;
66 }
67
68 /* GPIO Parallel output is a single 32-bit register per bank of 32 pins */
pin_parout_addr(const struct device * dev)69 static inline uintptr_t pin_parout_addr(const struct device *dev)
70 {
71 const struct gpio_xec_config *config = dev->config;
72
73 return config->parout_addr;
74 }
75
76 /*
77 * Use Zephyr system API to implement
78 * reg32(addr) = (reg32(addr) & ~mask) | (val & mask)
79 */
xec_mask_write32(uintptr_t addr,uint32_t mask,uint32_t val)80 static inline void xec_mask_write32(uintptr_t addr, uint32_t mask, uint32_t val)
81 {
82 uint32_t r = (sys_read32(addr) & ~mask) | (val & mask);
83
84 sys_write32(r, addr);
85 }
86
87 /*
88 * NOTE: gpio_flags_t b[15:0] are defined in the dt-binding gpio header.
89 * b[31:16] are defined in the driver gpio header.
90 * Hardware only supports push-pull or open-drain.
91 */
gpio_xec_validate_flags(gpio_flags_t flags)92 static int gpio_xec_validate_flags(gpio_flags_t flags)
93 {
94 if ((flags & (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN))
95 == (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE)) {
96 return -ENOTSUP;
97 }
98
99 if ((flags & (GPIO_INPUT | GPIO_OUTPUT))
100 == (GPIO_INPUT | GPIO_OUTPUT)) {
101 return -ENOTSUP;
102 }
103
104 if ((flags & GPIO_OUTPUT_INIT_LOW) && (flags & GPIO_OUTPUT_INIT_HIGH)) {
105 return -EINVAL;
106 }
107
108 return 0;
109 }
110
111 /*
112 * Each GPIO pin has two 32-bit control registers. Control 1 configures pin
113 * features except for drive strength and slew rate in Control 2.
114 * A pin's input and output state can be read/written from either the Control 1
115 * register or from corresponding bits in the GPIO parallel input/output registers.
116 * The parallel input and output registers group 32 pins into each register.
117 * The GPIO hardware restricts the pin output state to Control 1 or the parallel bit.
118 * Both output bits reflect each other on read and writes but only one is writable
119 * selected by the output control select bit in Control 1. In the configuration API
120 * we use Control 1 to configure all pin features and output state. Before exiting,
121 * we set the output select for parallel mode enabling writes to the parallel output bit.
122 */
gpio_xec_configure(const struct device * dev,gpio_pin_t pin,gpio_flags_t flags)123 static int gpio_xec_configure(const struct device *dev,
124 gpio_pin_t pin, gpio_flags_t flags)
125 {
126 const struct gpio_xec_config *config = dev->config;
127 uintptr_t pcr1_addr = 0u;
128 uint32_t pcr1 = 0u, pcr1_new = 0u;
129 uint32_t msk = (MCHP_GPIO_CTRL_PWRG_MASK
130 | MCHP_GPIO_CTRL_BUFT_MASK | MCHP_GPIO_CTRL_DIR_MASK
131 | MCHP_GPIO_CTRL_AOD_MASK | BIT(MCHP_GPIO_CTRL_POL_POS)
132 | MCHP_GPIO_CTRL_MUX_MASK | MCHP_GPIO_CTRL_INPAD_DIS_MASK);
133
134 if (!(valid_ctrl_masks[config->port_num] & BIT(pin))) {
135 return -EINVAL;
136 }
137
138 int ret = gpio_xec_validate_flags(flags);
139
140 if (ret) {
141 return ret;
142 }
143
144 pcr1_addr = pin_ctrl_addr(dev, pin);
145 pcr1 = sys_read32(pcr1_addr);
146
147 /* Check if pin is in GPIO mode */
148 if (MCHP_GPIO_CTRL_MUX_GET(pcr1) != MCHP_GPIO_CTRL_MUX_F0) {
149 LOG_WRN("Port:%d pin:0x%x not in GPIO mode. CTRL[%x]=%x", config->port_num, pin,
150 (uint32_t)pcr1_addr, pcr1);
151 }
152
153 if (flags == GPIO_DISCONNECTED) {
154 pcr1 = (pcr1 & ~MCHP_GPIO_CTRL_PWRG_MASK) | MCHP_GPIO_CTRL_PWRG_OFF;
155 sys_write32(pcr1, pcr1_addr);
156 return 0;
157 }
158
159 /* final pin state will be powered */
160 pcr1_new = MCHP_GPIO_CTRL_PWRG_VTR_IO;
161
162 /* always enable input pad */
163 if (pcr1 & BIT(MCHP_GPIO_CTRL_INPAD_DIS_POS)) {
164 pcr1 &= ~BIT(MCHP_GPIO_CTRL_INPAD_DIS_POS);
165 sys_write32(pcr1, pcr1_addr);
166 }
167
168 if (flags & GPIO_OUTPUT) {
169 pcr1_new |= BIT(MCHP_GPIO_CTRL_DIR_POS);
170 msk |= BIT(MCHP_GPIO_CTRL_OUTVAL_POS);
171 if (flags & GPIO_OUTPUT_INIT_HIGH) {
172 pcr1_new |= BIT(MCHP_GPIO_CTRL_OUTVAL_POS);
173 } else if (flags & GPIO_OUTPUT_INIT_LOW) {
174 pcr1_new &= ~BIT(MCHP_GPIO_CTRL_OUTVAL_POS);
175 } else { /* copy current input state to output state */
176 if ((pcr1 & MCHP_GPIO_CTRL_PWRG_MASK) == MCHP_GPIO_CTRL_PWRG_OFF) {
177 pcr1 &= ~(MCHP_GPIO_CTRL_PWRG_MASK);
178 pcr1 |= MCHP_GPIO_CTRL_PWRG_VTR_IO;
179 sys_write32(pcr1, pcr1_addr);
180 }
181 pcr1 = sys_read32(pcr1_addr);
182 if (pcr1 & BIT(MCHP_GPIO_CTRL_INPAD_VAL_POS)) {
183 pcr1_new |= BIT(MCHP_GPIO_CTRL_OUTVAL_POS);
184 } else {
185 pcr1_new &= ~BIT(MCHP_GPIO_CTRL_OUTVAL_POS);
186 }
187 }
188 if (flags & GPIO_LINE_OPEN_DRAIN) {
189 pcr1_new |= BIT(MCHP_GPIO_CTRL_BUFT_POS);
190 }
191 }
192
193 if (flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)) {
194 msk |= MCHP_GPIO_CTRL_PUD_MASK;
195 /* both bits specifies repeater mode */
196 if (flags & GPIO_PULL_UP) {
197 pcr1_new |= MCHP_GPIO_CTRL_PUD_PU;
198 }
199 if (flags & GPIO_PULL_DOWN) {
200 pcr1_new |= MCHP_GPIO_CTRL_PUD_PD;
201 }
202 }
203
204 /*
205 * Problem, if pin was power gated off we can't read input.
206 * How to turn on pin to read input but not glitch it?
207 */
208 pcr1 = (pcr1 & ~msk) | (pcr1_new & msk);
209 sys_write32(pcr1, pcr1_addr); /* configuration. may generate a single edge */
210 /* Control output bit becomes read-only and parallel out register bit becomes r/w */
211 sys_write32(pcr1 | BIT(MCHP_GPIO_CTRL_AOD_POS), pcr1_addr);
212
213 return 0;
214 }
215
gen_gpio_ctrl_icfg(enum gpio_int_mode mode,enum gpio_int_trig trig,uint32_t * pin_ctr1)216 static int gen_gpio_ctrl_icfg(enum gpio_int_mode mode, enum gpio_int_trig trig,
217 uint32_t *pin_ctr1)
218 {
219 if (!pin_ctr1) {
220 return -EINVAL;
221 }
222
223 if (mode == GPIO_INT_MODE_DISABLED) {
224 *pin_ctr1 = MCHP_GPIO_CTRL_IDET_DISABLE;
225 } else {
226 if (mode == GPIO_INT_MODE_LEVEL) {
227 if (trig == GPIO_INT_TRIG_HIGH) {
228 *pin_ctr1 = MCHP_GPIO_CTRL_IDET_LVL_HI;
229 } else {
230 *pin_ctr1 = MCHP_GPIO_CTRL_IDET_LVL_LO;
231 }
232 } else {
233 switch (trig) {
234 case GPIO_INT_TRIG_LOW:
235 *pin_ctr1 = MCHP_GPIO_CTRL_IDET_FEDGE;
236 break;
237 case GPIO_INT_TRIG_HIGH:
238 *pin_ctr1 = MCHP_GPIO_CTRL_IDET_REDGE;
239 break;
240 case GPIO_INT_TRIG_BOTH:
241 *pin_ctr1 = MCHP_GPIO_CTRL_IDET_BEDGE;
242 break;
243 default:
244 return -EINVAL;
245 }
246 }
247 }
248
249 return 0;
250 }
251
gpio_xec_intr_en(gpio_pin_t pin,enum gpio_int_mode mode,uint8_t girq_id)252 static void gpio_xec_intr_en(gpio_pin_t pin, enum gpio_int_mode mode,
253 uint8_t girq_id)
254 {
255 if (mode != GPIO_INT_MODE_DISABLED) {
256 /* Enable interrupt to propagate via its GIRQ to the NVIC */
257 mchp_soc_ecia_girq_src_en(girq_id, pin);
258 }
259 }
260
gpio_xec_pin_interrupt_configure(const struct device * dev,gpio_pin_t pin,enum gpio_int_mode mode,enum gpio_int_trig trig)261 static int gpio_xec_pin_interrupt_configure(const struct device *dev,
262 gpio_pin_t pin,
263 enum gpio_int_mode mode,
264 enum gpio_int_trig trig)
265 {
266 const struct gpio_xec_config *config = dev->config;
267 uintptr_t pcr1_addr = pin_ctrl_addr(dev, pin);
268 uint32_t pcr1 = 0u;
269 uint32_t pcr1_req = 0u;
270
271 /* Validate pin number range in terms of current port */
272 if ((valid_ctrl_masks[config->port_num] & BIT(pin)) == 0U) {
273 return -EINVAL;
274 }
275
276 /* Check if GPIO port supports interrupts */
277 if ((mode != GPIO_INT_MODE_DISABLED) &&
278 ((config->flags & GPIO_INT_ENABLE) == 0)) {
279 return -ENOTSUP;
280 }
281
282 pcr1_req = MCHP_GPIO_CTRL_IDET_DISABLE;
283 if (gen_gpio_ctrl_icfg(mode, trig, &pcr1_req)) {
284 return -EINVAL;
285 }
286
287 /* Disable interrupt in the EC aggregator */
288 mchp_soc_ecia_girq_src_dis(config->girq_id, pin);
289
290 /* pin configuration matches requested detection mode? */
291 pcr1 = sys_read32(pcr1_addr);
292 /* HW detects interrupt on input. Make sure input pad disable is cleared */
293 pcr1 &= ~BIT(MCHP_GPIO_CTRL_INPAD_DIS_POS);
294
295 if ((pcr1 & MCHP_GPIO_CTRL_IDET_MASK) == pcr1_req) {
296 gpio_xec_intr_en(pin, mode, config->girq_id);
297 return 0;
298 }
299
300 pcr1 &= ~MCHP_GPIO_CTRL_IDET_MASK;
301
302 if (mode == GPIO_INT_MODE_LEVEL) {
303 if (trig == GPIO_INT_TRIG_HIGH) {
304 pcr1 |= MCHP_GPIO_CTRL_IDET_LVL_HI;
305 } else {
306 pcr1 |= MCHP_GPIO_CTRL_IDET_LVL_LO;
307 }
308 } else if (mode == GPIO_INT_MODE_EDGE) {
309 if (trig == GPIO_INT_TRIG_LOW) {
310 pcr1 |= MCHP_GPIO_CTRL_IDET_FEDGE;
311 } else if (trig == GPIO_INT_TRIG_HIGH) {
312 pcr1 |= MCHP_GPIO_CTRL_IDET_REDGE;
313 } else if (trig == GPIO_INT_TRIG_BOTH) {
314 pcr1 |= MCHP_GPIO_CTRL_IDET_BEDGE;
315 }
316 } else {
317 pcr1 |= MCHP_GPIO_CTRL_IDET_DISABLE;
318 }
319
320 sys_write32(pcr1, pcr1_addr);
321 /* delay for HW to synchronize after it ungates its clock */
322 for (int i = 0; i < XEC_GPIO_EDGE_DLY_COUNT; i++) {
323 sys_read32(pcr1_addr);
324 }
325
326 mchp_soc_ecia_girq_src_clr(config->girq_id, pin);
327
328 gpio_xec_intr_en(pin, mode, config->girq_id);
329
330 return 0;
331 }
332
gpio_xec_port_set_masked_raw(const struct device * dev,uint32_t mask,uint32_t value)333 static int gpio_xec_port_set_masked_raw(const struct device *dev,
334 uint32_t mask,
335 uint32_t value)
336 {
337 uintptr_t pout_addr = pin_parout_addr(dev);
338
339 xec_mask_write32(pout_addr, mask, value);
340
341 return 0;
342 }
343
gpio_xec_port_set_bits_raw(const struct device * dev,uint32_t mask)344 static int gpio_xec_port_set_bits_raw(const struct device *dev, uint32_t mask)
345 {
346 uintptr_t pout_addr = pin_parout_addr(dev);
347
348 sys_write32(sys_read32(pout_addr) | mask, pout_addr);
349
350 return 0;
351 }
352
gpio_xec_port_clear_bits_raw(const struct device * dev,uint32_t mask)353 static int gpio_xec_port_clear_bits_raw(const struct device *dev,
354 uint32_t mask)
355 {
356 uintptr_t pout_addr = pin_parout_addr(dev);
357
358 sys_write32(sys_read32(pout_addr) & ~mask, pout_addr);
359
360 return 0;
361 }
362
gpio_xec_port_toggle_bits(const struct device * dev,uint32_t mask)363 static int gpio_xec_port_toggle_bits(const struct device *dev, uint32_t mask)
364 {
365 uintptr_t pout_addr = pin_parout_addr(dev);
366
367 sys_write32(sys_read32(pout_addr) ^ mask, pout_addr);
368
369 return 0;
370 }
371
gpio_xec_port_get_raw(const struct device * dev,uint32_t * value)372 static int gpio_xec_port_get_raw(const struct device *dev, uint32_t *value)
373 {
374 uintptr_t pin_addr = pin_parin_addr(dev);
375
376 *value = sys_read32(pin_addr);
377
378 return 0;
379 }
380
gpio_xec_manage_callback(const struct device * dev,struct gpio_callback * callback,bool set)381 static int gpio_xec_manage_callback(const struct device *dev,
382 struct gpio_callback *callback, bool set)
383 {
384 struct gpio_xec_data *data = dev->data;
385
386 gpio_manage_callback(&data->callbacks, callback, set);
387
388 return 0;
389 }
390
391 #ifdef CONFIG_GPIO_GET_DIRECTION
gpio_xec_get_direction(const struct device * port,gpio_port_pins_t map,gpio_port_pins_t * inputs,gpio_port_pins_t * outputs)392 static int gpio_xec_get_direction(const struct device *port, gpio_port_pins_t map,
393 gpio_port_pins_t *inputs, gpio_port_pins_t *outputs)
394 {
395 if (!port) {
396 return -EINVAL;
397 }
398
399 const struct gpio_xec_config *config = port->config;
400 uint32_t valid_msk = valid_ctrl_masks[config->port_num];
401
402 *inputs = 0u;
403 *outputs = 0u;
404 for (uint8_t pin = 0; pin < 32; pin++) {
405 if (!map) {
406 break;
407 }
408 if ((map & BIT(pin)) && (valid_msk & BIT(pin))) {
409 uintptr_t pcr1_addr = pin_ctrl_addr(port, pin);
410 uint32_t pcr1 = sys_read32(pcr1_addr);
411
412 if (!((pcr1 & MCHP_GPIO_CTRL_PWRG_MASK) == MCHP_GPIO_CTRL_PWRG_OFF)) {
413 if (outputs && (pcr1 & BIT(MCHP_GPIO_CTRL_DIR_POS))) {
414 *outputs |= BIT(pin);
415 } else if (inputs && !(pcr1 & BIT(MCHP_GPIO_CTRL_INPAD_DIS_POS))) {
416 *inputs |= BIT(pin);
417 }
418 }
419
420 map &= ~BIT(pin);
421 }
422 }
423
424 return 0;
425 }
426 #endif
427
428 #ifdef CONFIG_GPIO_GET_CONFIG
gpio_xec_get_config(const struct device * port,gpio_pin_t pin,gpio_flags_t * flags)429 int gpio_xec_get_config(const struct device *port, gpio_pin_t pin, gpio_flags_t *flags)
430 {
431 if (!port || !flags) {
432 return -EINVAL;
433 }
434
435 const struct gpio_xec_config *config = port->config;
436 uint32_t valid_msk = valid_ctrl_masks[config->port_num];
437
438 if (!(valid_msk & BIT(pin))) {
439 return -EINVAL;
440 /* Or should we set *flags = GPIO_DISCONNECTED and return success? */
441 }
442
443 uintptr_t pcr1_addr = pin_ctrl_addr(port, pin);
444 uint32_t pcr1 = sys_read32(pcr1_addr);
445 uint32_t pin_flags = 0u;
446
447 if (pcr1 & BIT(MCHP_GPIO_CTRL_DIR_POS)) {
448 pin_flags |= GPIO_OUTPUT;
449 if (pcr1 & BIT(MCHP_GPIO_CTRL_OUTVAL_POS)) {
450 pin_flags |= GPIO_OUTPUT_INIT_HIGH;
451 } else {
452 pin_flags |= GPIO_OUTPUT_INIT_LOW;
453 }
454
455 if (pcr1 & BIT(MCHP_GPIO_CTRL_BUFT_POS)) {
456 pin_flags |= GPIO_OPEN_DRAIN;
457 }
458 } else if (!(pcr1 & BIT(MCHP_GPIO_CTRL_INPAD_DIS_POS))) {
459 pin_flags |= GPIO_INPUT;
460 }
461
462 if (pin_flags) {
463 *flags = pin_flags;
464 } else {
465 *flags = GPIO_DISCONNECTED;
466 }
467
468 return 0;
469 }
470 #endif
471
gpio_gpio_xec_port_isr(const struct device * dev)472 static void gpio_gpio_xec_port_isr(const struct device *dev)
473 {
474 const struct gpio_xec_config *config = dev->config;
475 struct gpio_xec_data *data = dev->data;
476 uint32_t girq_result;
477
478 /*
479 * Figure out which interrupts have been triggered from the EC
480 * aggregator result register
481 */
482 girq_result = mchp_soc_ecia_girq_result(config->girq_id);
483
484 /* Clear source register in aggregator before firing callbacks */
485 mchp_soc_ecia_girq_src_clr_bitmap(config->girq_id, girq_result);
486
487 gpio_fire_callbacks(&data->callbacks, dev, girq_result);
488 }
489
490 /* GPIO driver official API table */
491 static DEVICE_API(gpio, gpio_xec_driver_api) = {
492 .pin_configure = gpio_xec_configure,
493 .port_get_raw = gpio_xec_port_get_raw,
494 .port_set_masked_raw = gpio_xec_port_set_masked_raw,
495 .port_set_bits_raw = gpio_xec_port_set_bits_raw,
496 .port_clear_bits_raw = gpio_xec_port_clear_bits_raw,
497 .port_toggle_bits = gpio_xec_port_toggle_bits,
498 .pin_interrupt_configure = gpio_xec_pin_interrupt_configure,
499 .manage_callback = gpio_xec_manage_callback,
500 #ifdef CONFIG_GPIO_GET_DIRECTION
501 .port_get_direction = gpio_xec_get_direction,
502 #endif
503 #ifdef CONFIG_GPIO_GET_CONFIG
504 .pin_get_config = gpio_xec_get_config,
505 #endif
506 };
507
508 #define XEC_GPIO_PORT_FLAGS(n) \
509 ((DT_INST_IRQ_HAS_CELL(n, irq)) ? GPIO_INT_ENABLE : 0)
510
511 #define XEC_GPIO_PORT(n) \
512 static int gpio_xec_port_init_##n(const struct device *dev) \
513 { \
514 if (!(DT_INST_IRQ_HAS_CELL(n, irq))) { \
515 return 0; \
516 } \
517 \
518 const struct gpio_xec_config *config = dev->config; \
519 \
520 mchp_soc_ecia_girq_aggr_en(config->girq_id, 1); \
521 \
522 IRQ_CONNECT(DT_INST_IRQN(n), \
523 DT_INST_IRQ(n, priority), \
524 gpio_gpio_xec_port_isr, \
525 DEVICE_DT_INST_GET(n), 0U); \
526 \
527 irq_enable(DT_INST_IRQN(n)); \
528 \
529 return 0; \
530 } \
531 \
532 static struct gpio_xec_data gpio_xec_port_data_##n; \
533 \
534 static const struct gpio_xec_config xec_gpio_config_##n = { \
535 .common = { \
536 .port_pin_mask = \
537 GPIO_PORT_PIN_MASK_FROM_DT_INST(n), \
538 }, \
539 .pcr1_base = (uintptr_t)DT_INST_REG_ADDR_BY_IDX(n, 0), \
540 .parin_addr = (uintptr_t)DT_INST_REG_ADDR_BY_IDX(n, 1), \
541 .parout_addr = (uintptr_t)DT_INST_REG_ADDR_BY_IDX(n, 2),\
542 .port_num = DT_INST_PROP(n, port_id), \
543 .girq_id = DT_INST_PROP_OR(n, girq_id, 0), \
544 .flags = XEC_GPIO_PORT_FLAGS(n), \
545 }; \
546 \
547 DEVICE_DT_INST_DEFINE(n, gpio_xec_port_init_##n, NULL, \
548 &gpio_xec_port_data_##n, &xec_gpio_config_##n, \
549 PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY, \
550 &gpio_xec_driver_api);
551
552 DT_INST_FOREACH_STATUS_OKAY(XEC_GPIO_PORT)
553
