1/*
2 * Copyright 2023 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8
9#include <nxp/nxp_rt1040.dtsi>
10#include "mimxrt1040_evk-pinctrl.dtsi"
11#include <zephyr/dt-bindings/input/input-event-codes.h>
12
13/ {
14	model = "NXP MIMXRT1040-EVK board";
15	compatible = "nxp,mimxrt1042";
16
17	aliases {
18		led0 = &green_led;
19		sw0 = &user_button;
20		pwm-0 = &flexpwm1_pwm3;
21		accel0 = &fxls8974;
22		mcuboot-button0 = &user_button;
23	};
24
25	chosen {
26		zephyr,sram = &sdram0;
27		zephyr,itcm = &itcm;
28		zephyr,dtcm = &dtcm;
29		zephyr,console = &lpuart1;
30		zephyr,shell-uart = &lpuart1;
31		zephyr,flash = &w25q64jvssiq;
32		zephyr,flash-controller = &w25q64jvssiq;
33		zephyr,code-partition = &slot0_partition;
34		zephyr,uart-mcumgr = &lpuart1;
35		zephyr,bt-hci = &bt_hci_uart;
36	};
37
38	sdram0: memory@80000000 {
39		/* Winbond W9825G6KH SDRAM */
40		device_type = "memory";
41		reg = <0x80000000 DT_SIZE_M(32)>;
42	};
43
44	/*
45	 * This node describes the GPIO pins of the parallel FPC interface,
46	 * This interface is standard to several NXP EVKs, and is used with
47	 * several parallel LCD displays (available as zephyr shields)
48	 */
49	nxp_parallel_lcd_connector: parallel-connector {
50		compatible = "nxp,parallel-lcd-connector";
51		#gpio-cells = <2>;
52		gpio-map-mask = <0xffffffff 0xffffffc0>;
53		gpio-map-pass-thru = <0 0x3f>;
54		gpio-map =	<0  0 &gpio2 31 0>;	/* Pin 1, BL+ */
55	};
56
57	/*
58	 * This node describes the GPIO pins of the I2C display FPC interface,
59	 * This interface is standard to several NXP EVKs, and is used with
60	 * several parallel LCD displays (available as zephyr shields)
61	 */
62	nxp_i2c_touch_fpc: i2c-touch-connector {
63		compatible = "nxp,i2c-tsc-fpc";
64		#gpio-cells = <2>;
65		gpio-map-mask = <0xffffffff 0xffffffc0>;
66		gpio-map-pass-thru = <0 0x3f>;
67		gpio-map =	<1  0 &gpio1 19 0>,	/* Pin 2, LCD touch RST */
68				<2  0 &gpio1 11 0>;	/* Pin 3, LCD touch INT */
69	};
70
71	leds {
72		compatible = "gpio-leds";
73		green_led: led_0 {
74			gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
75			label = "User LD1";
76		};
77	};
78
79	gpio_keys {
80		compatible = "gpio-keys";
81		user_button: button_0 {
82			label = "User SW8";
83			gpios = <&gpio5 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
84			zephyr,code = <INPUT_KEY_0>;
85		};
86	};
87
88	arduino_header: connector {
89		compatible = "arduino-header-r3";
90		#gpio-cells = <2>;
91		gpio-map-mask = <0xffffffff 0xffffffc0>;
92		gpio-map-pass-thru = <0 0x3f>;
93		gpio-map = <0 0 &gpio1 14 0>,	/* A0 */
94			   <1 0 &gpio1 15 0>,	/* A1 */
95			   <2 0 &gpio1 20 0>,	/* A2 */
96			   <3 0 &gpio1 21 0>,	/* A3 */
97			   <4 0 &gpio1 22 0>,	/* A4 */
98			   <5 0 &gpio1 23 0>,	/* A5 */
99			   <6 0 &gpio3 1 0>,	/* D0 */
100			   <7 0 &gpio3 0 0>,	/* D1 */
101			   <8 0 &gpio1 11 0>,	/* D2 */
102			   <9 0 &gpio3 2 0>,	/* D3 */
103			   <10 0 &gpio1 9 0>,	/* D4 */
104			   <11 0 &gpio1 10 0>,	/* D5 */
105			   <12 0 &gpio1 18 0>,	/* D6 */
106			   <13 0 &gpio1 19 0>,	/* D7 */
107			   <14 0 &gpio2 30 0>,	/* D8 */
108			   <15 0 &gpio2 31 0>,	/* D9 */
109			   <16 0 &gpio3 13 0>,	/* D10 */
110			   <17 0 &gpio3 14 0>,	/* D11 */
111			   <18 0 &gpio3 15 0>,	/* D12 */
112			   <19 0 &gpio3 12 0>,	/* D13 */
113			   <20 0 &gpio1 17 0>,	/* D14 */
114			   <21 0 &gpio1 16 0>;	/* D15 */
115	};
116};
117
118&flexspi {
119	status = "okay";
120	reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(8)>;
121	/* Winbond external flash */
122	w25q64jvssiq: w25q64jvssiq@0 {
123		compatible = "nxp,imx-flexspi-nor";
124		size = <(DT_SIZE_M(8) * 8)>;
125		reg = <0>;
126		spi-max-frequency = <133000000>;
127		status = "okay";
128		jedec-id = [ef 40 17];
129		erase-block-size = <4096>;
130		write-block-size = <1>;
131		partitions {
132			compatible = "fixed-partitions";
133			#address-cells = <1>;
134			#size-cells = <1>;
135			boot_partition: partition@0 {
136				label = "mcuboot";
137				reg = <0x00000000 DT_SIZE_K(128)>;
138			};
139			/* The MCUBoot swap-move algorithm uses the last 2 sectors
140			 * of the primary slot0 for swap status and move.
141			 */
142			slot0_partition: partition@20000 {
143				label = "image-0";
144				reg = <0x00020000 (DT_SIZE_M(3) + DT_SIZE_K(8))>;
145			};
146			slot1_partition: partition@322000 {
147				label = "image-1";
148				reg = <0x00322000 DT_SIZE_M(3)>;
149			};
150			storage_partition: partition@622000 {
151				label = "storage";
152				reg = <0x00622000 (DT_SIZE_M(2) - DT_SIZE_K(136))>;
153			};
154		};
155	};
156};
157
158&lpuart1 {
159	status = "okay";
160	current-speed = <115200>;
161	pinctrl-0 = <&pinmux_lpuart1>;
162	pinctrl-1 = <&pinmux_lpuart1_sleep>;
163	pinctrl-names = "default", "sleep";
164};
165
166&flexpwm1_pwm3 {
167	status = "okay";
168	pinctrl-0 = <&pinmux_flexpwm1_pwm3>;
169	pinctrl-names = "default";
170};
171
172&adc1 {
173	status = "okay";
174	pinctrl-0 = <&pinmux_adc1>;
175	pinctrl-names = "default";
176};
177
178&lpspi1 {
179	status = "okay";
180	/* DMA channels 0 and 1, muxed to LPSPI1 RX and TX */
181	dmas = <&edma0 0 13>, <&edma0 1 14>;
182	dma-names = "rx", "tx";
183	pinctrl-0 = <&pinmux_lpspi1>;
184	pinctrl-names = "default";
185};
186
187&edma0 {
188	status = "okay";
189};
190
191&lpi2c1 {
192	status = "okay";
193	pinctrl-0 = <&pinmux_lpi2c1>;
194	pinctrl-names = "default";
195};
196
197nxp_touch_i2c: &lpi2c1 {};
198
199zephyr_lcdif: &lcdif {
200	pinctrl-0 = <&pinmux_lcdif>;
201	pinctrl-names = "default";
202};
203
204lpi2c3: &lpi2c3 {
205	pinctrl-0 = <&pinmux_lpi2c3>;
206	pinctrl-names = "default";
207	status = "okay";
208
209	fxls8974: fxls8974@18 {
210		compatible = "nxp,fxls8974";
211		reg = <0x18>;
212		status = "okay";
213
214		/* Two zero ohm resistors (R115 and R122) isolate sensor
215		 * interrupt gpios from the soc and are unpopulated by default.
216		 * Note that if you populate them, they conflict with JTAG_TDO and
217		 * ethernet PHY interrupt signals.
218		 * int1-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
219		 * int2-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
220		 */
221	};
222};
223
224/* GPT and Systick are enabled. If power management is enabled, the GPT
225 * timer will be used instead of systick, as allows the core clock to
226 * be gated.
227 */
228&gpt_hw_timer {
229	status = "okay";
230};
231
232&systick {
233	status = "okay";
234};
235
236m2_hci_uart: &lpuart3 {
237	pinctrl-0 = <&pinmux_lpuart3_flowcontrol>;
238	pinctrl-1 = <&pinmux_lpuart3_sleep>;
239	pinctrl-names = "default", "sleep";
240
241	bt_hci_uart: bt_hci_uart {
242		compatible = "zephyr,bt-hci-uart";
243
244		m2_bt_module {
245			compatible = "nxp,bt-hci-uart";
246			sdio-reset-gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
247			w-disable-gpios = <&gpio3 2 GPIO_ACTIVE_HIGH>;
248			hci-operation-speed = <115200>;
249			hw-flow-control;
250			fw-download-primary-speed = <115200>;
251			fw-download-secondary-speed = <3000000>;
252			fw-download-secondary-flowcontrol;
253		};
254	};
255};
256
257&m2_hci_uart {
258	status = "okay";
259	current-speed = <115200>;
260};
261