2  * Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
4  * SPDX-License-Identifier: Apache-2.0
26 /* sifive GPIO register-set structure */
51 	/* multi-level encoded interrupt corresponding to pin 0 */
65 	((const struct gpio_sifive_config * const)(dev)->config)
67 	((volatile struct gpio_sifive_t *)(DEV_GPIO_CFG(dev))->gpio_base_addr)
69 	((struct gpio_sifive_data *)(dev)->data)
88  * with the interrupt
98 	return (plic_irq - base_irq);  in gpio_sifive_plic_to_pin()
107 	/* Calculate pin and mask from base level 2 line */  in gpio_sifive_irq_handler()
108 	uint8_t pin = 1 + (riscv_plic_get_irq() -  in gpio_sifive_irq_handler()
109 			   (uint8_t)(cfg->gpio_irq_base >> CONFIG_1ST_LEVEL_INTERRUPT_BITS));  in gpio_sifive_irq_handler()
116 	 * It is certainly possible, especially on double-edge, that  in gpio_sifive_irq_handler()
124 	gpio->rise_ip = BIT(pin);  in gpio_sifive_irq_handler()
125 	gpio->fall_ip = BIT(pin);  in gpio_sifive_irq_handler()
126 	gpio->high_ip = BIT(pin);  in gpio_sifive_irq_handler()
127 	gpio->low_ip = BIT(pin);  in gpio_sifive_irq_handler()
130 	gpio_fire_callbacks(&data->cb, dev, BIT(pin));  in gpio_sifive_irq_handler()
148 	/* We cannot support open-source open-drain configuration */  in gpio_sifive_config()
150 		return -ENOTSUP;  in gpio_sifive_config()
153 	/* We only support pull-ups, not pull-downs */  in gpio_sifive_config()
155 		return -ENOTSUP;  in gpio_sifive_config()
158 	/* Set pull-up if requested */  in gpio_sifive_config()
159 	WRITE_BIT(gpio->pue, pin, flags & GPIO_PULL_UP);  in gpio_sifive_config()
165 		gpio->out_val |= BIT(pin);  in gpio_sifive_config()
168 		gpio->out_val &= ~BIT(pin);  in gpio_sifive_config()
172 	WRITE_BIT(gpio->out_en, pin, flags & GPIO_OUTPUT);  in gpio_sifive_config()
173 	WRITE_BIT(gpio->in_en, pin, flags & GPIO_INPUT);  in gpio_sifive_config()
183 	*value = gpio->in_val;  in gpio_sifive_port_get_raw()
189 					   gpio_port_pins_t mask,  in gpio_sifive_port_set_masked_raw()  argument
194 	gpio->out_val = (gpio->out_val & ~mask) | (value & mask);  in gpio_sifive_port_set_masked_raw()
200 					 gpio_port_pins_t mask)  in gpio_sifive_port_set_bits_raw()  argument
204 	gpio->out_val |= mask;  in gpio_sifive_port_set_bits_raw()
210 					   gpio_port_pins_t mask)  in gpio_sifive_port_clear_bits_raw()  argument
214 	gpio->out_val &= ~mask;  in gpio_sifive_port_clear_bits_raw()
220 					gpio_port_pins_t mask)  in gpio_sifive_port_toggle_bits()  argument
224 	gpio->out_val ^= mask;  in gpio_sifive_port_toggle_bits()
237 	gpio->rise_ie &= ~BIT(pin);  in gpio_sifive_pin_interrupt_configure()
238 	gpio->fall_ie &= ~BIT(pin);  in gpio_sifive_pin_interrupt_configure()
239 	gpio->high_ie &= ~BIT(pin);  in gpio_sifive_pin_interrupt_configure()
240 	gpio->low_ie  &= ~BIT(pin);  in gpio_sifive_pin_interrupt_configure()
244 		irq_disable(gpio_sifive_pin_irq(cfg->gpio_irq_base, pin));  in gpio_sifive_pin_interrupt_configure()
249 			gpio->high_ip = BIT(pin);  in gpio_sifive_pin_interrupt_configure()
250 			gpio->high_ie |= BIT(pin);  in gpio_sifive_pin_interrupt_configure()
253 			gpio->low_ip = BIT(pin);  in gpio_sifive_pin_interrupt_configure()
254 			gpio->low_ie  |= BIT(pin);  in gpio_sifive_pin_interrupt_configure()
256 		irq_enable(gpio_sifive_pin_irq(cfg->gpio_irq_base, pin));  in gpio_sifive_pin_interrupt_configure()
263 			gpio->rise_ip = BIT(pin);  in gpio_sifive_pin_interrupt_configure()
264 			gpio->rise_ie |= BIT(pin);  in gpio_sifive_pin_interrupt_configure()
267 			gpio->fall_ip = BIT(pin);  in gpio_sifive_pin_interrupt_configure()
268 			gpio->fall_ie |= BIT(pin);  in gpio_sifive_pin_interrupt_configure()
270 		irq_enable(gpio_sifive_pin_irq(cfg->gpio_irq_base, pin));  in gpio_sifive_pin_interrupt_configure()
274 		return -ENOTSUP;  in gpio_sifive_pin_interrupt_configure()
286 	return gpio_manage_callback(&data->cb, callback, set);  in gpio_sifive_manage_callback()
290 static int gpio_sifive_port_get_dir(const struct device *dev, gpio_port_pins_t map,  in gpio_sifive_port_get_dir()  argument
295 	map &= cfg->common.port_pin_mask;  in gpio_sifive_port_get_dir()
298 		*inputs = map & DEV_GPIO(dev)->in_en;  in gpio_sifive_port_get_dir()
302 		*outputs = map & DEV_GPIO(dev)->out_en;  in gpio_sifive_port_get_dir()
338 	gpio->in_en   = 0U;  in gpio_sifive_init()
339 	gpio->out_en  = 0U;  in gpio_sifive_init()
340 	gpio->pue     = 0U;  in gpio_sifive_init()
341 	gpio->rise_ie = 0U;  in gpio_sifive_init()
342 	gpio->fall_ie = 0U;  in gpio_sifive_init()
343 	gpio->high_ie = 0U;  in gpio_sifive_init()
344 	gpio->low_ie  = 0U;  in gpio_sifive_init()
345 	gpio->iof_en  = 0U;  in gpio_sifive_init()
346 	gpio->iof_sel = 0U;  in gpio_sifive_init()
347 	gpio->invert  = 0U;  in gpio_sifive_init()
350 	cfg->gpio_cfg_func();  in gpio_sifive_init()