1 /* 2 * Copyright (c) 2023 Frontgrade Gaisler AB 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef ZEPHYR_DRIVERS_GPIO_GPIO_GRGPIO_H_ 7 #define ZEPHYR_DRIVERS_GPIO_GPIO_GRGPIO_H_ 8 9 struct grgpio_regs { 10 uint32_t data; /* 0x00 I/O port data register */ 11 uint32_t output; /* 0x04 I/O port output register */ 12 uint32_t dir; /* 0x08 I/O port direction register */ 13 uint32_t imask; /* 0x0C Interrupt mask register */ 14 uint32_t ipol; /* 0x10 Interrupt polarity register */ 15 uint32_t iedge; /* 0x14 Interrupt edge register */ 16 uint32_t bypass; /* 0x18 Bypass register */ 17 uint32_t cap; /* 0x1C Capability register */ 18 uint32_t irqmap[4]; /* 0x20 - 0x2C Interrupt map registers */ 19 uint32_t res_30; /* 0x30 Reserved */ 20 uint32_t res_34; /* 0x34 Reserved */ 21 uint32_t res_38; /* 0x38 Reserved */ 22 uint32_t res_3C; /* 0x3C Reserved */ 23 uint32_t iavail; /* 0x40 Interrupt available register */ 24 uint32_t iflag; /* 0x44 Interrupt flag register */ 25 uint32_t res_48; /* 0x48 Reserved */ 26 uint32_t pulse; /* 0x4C Pulse register */ 27 uint32_t res_50; /* 0x50 Reserved */ 28 uint32_t output_or; /* 0x54 I/O port output register, logical-OR */ 29 uint32_t dir_or; /* 0x58 I/O port dir. register, logical-OR */ 30 uint32_t imask_or; /* 0x5C Interrupt mask register, logical-OR */ 31 uint32_t res_60; /* 0x60 Reserved */ 32 uint32_t output_and; /* 0x64 I/O port output register, logical-AND */ 33 uint32_t dir_and; /* 0x68 I/O port dir. register, logical-AND */ 34 uint32_t imask_and; /* 0x6C Interrupt mask register, logical-AND */ 35 uint32_t res_70; /* 0x70 Reserved */ 36 uint32_t output_xor; /* 0x74 I/O port output register, logical-XOR */ 37 uint32_t dir_xor; /* 0x78 I/O port dir. register, logical-XOR */ 38 uint32_t imask_xor; /* 0x7C Interrupt mask register, logical-XOR */ 39 }; 40 41 #define GRGPIO_CAP_PU_BIT 18 42 #define GRGPIO_CAP_IER_BIT 17 43 #define GRGPIO_CAP_IFL_BIT 16 44 #define GRGPIO_CAP_IRQGEN_BIT 8 45 #define GRGPIO_CAP_NLINES_BIT 0 46 47 #define GRGPIO_CAP_PU (0x1 << GRGPIO_CAP_PU_BIT) 48 #define GRGPIO_CAP_IER (0x1 << GRGPIO_CAP_IER_BIT) 49 #define GRGPIO_CAP_IFL (0x1 << GRGPIO_CAP_IFL_BIT) 50 #define GRGPIO_CAP_IRQGEN (0x1f << GRGPIO_CAP_IRQGEN_BIT) 51 #define GRGPIO_CAP_NLINES (0x1f << GRGPIO_CAP_NLINES_BIT) 52 53 #endif /* ZEPHYR_DRIVERS_GPIO_GPIO_GRGPIO_H_ */ 54
