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/Zephyr-latest/dts/arm/atmel/
Dsamd20.dtsi21 clocks = <&gclk 0x13>, <&pm 0x20 8>;
22 clock-names = "GCLK", "PM";
30 clocks = <&gclk 0x14>, <&pm 0x20 10>;
31 clock-names = "GCLK", "PM";
39 clocks = <&gclk 0x16>, <&pm 0x20 14>;
40 clock-names = "GCLK", "PM";
48 clocks = <&gclk 26>, <&pm 0x20 18>;
49 clock-names = "GCLK", "PM";
54 clocks = <&gclk 0xd>, <&pm 0x20 2>;
55 clock-names = "GCLK", "PM";
[all …]
Dsaml21.dtsi22 clocks = <&gclk 25>, <&mclk 0x1c 5>;
23 clock-names = "GCLK", "MCLK";
34 clocks = <&gclk 25>, <&mclk 0x1c 6>;
35 clock-names = "GCLK", "MCLK";
46 clocks = <&gclk 26>, <&mclk 0x1c 7>;
47 clock-names = "GCLK", "MCLK";
58 clocks = <&gclk 32>, <&mclk 0x1c 12>;
59 clock-names = "GCLK", "MCLK";
64 clocks = <&gclk 18>, <&mclk 0x1c 0>;
65 clock-names = "GCLK", "MCLK";
[all …]
Dsamd21.dtsi41 clocks = <&gclk 0x1d>, <&pm 0x20 14>;
42 clock-names = "GCLK", "PM";
50 clocks = <&gclk 26>, <&pm 0x20 8>;
51 clock-names = "GCLK", "PM";
62 clocks = <&gclk 26>, <&pm 0x20 9>;
63 clock-names = "GCLK", "PM";
74 clocks = <&gclk 27>, <&pm 0x20 10>;
75 clock-names = "GCLK", "PM";
86 clocks = <&gclk 33>, <&pm 0x20 18>;
87 clock-names = "GCLK", "PM";
[all …]
Dsamc21.dtsi23 clocks = <&gclk 34>, <&mclk 0x1c 18>;
24 clock-names = "GCLK", "MCLK";
29 gclk = <0>;
37 clocks = <&gclk 23>, <&mclk 0x1c 5>;
38 clock-names = "GCLK", "MCLK";
46 clocks = <&gclk 25>, <&mclk 0x1c 6>;
47 clock-names = "GCLK", "MCLK";
56 clocks = <&gclk 26>, <&mclk 0x10 8>;
57 clock-names = "GCLK", "MCLK";
69 clocks = <&gclk 27>, <&mclk 0x10 9>;
[all …]
Dsamd5x.dtsi97 gclk: gclk@40001c00 { label
98 compatible = "atmel,samd5x-gclk";
169 clocks = <&gclk 7>, <&mclk 0x14 12>;
170 clock-names = "GCLK", "MCLK";
178 clocks = <&gclk 8>, <&mclk 0x14 13>;
179 clock-names = "GCLK", "MCLK";
187 clocks = <&gclk 23>, <&mclk 0x18 9>;
188 clock-names = "GCLK", "MCLK";
196 clocks = <&gclk 24>, <&mclk 0x18 10>;
197 clock-names = "GCLK", "MCLK";
[all …]
Dsamc2x.dtsi87 gclk: gclk@40001c00 { label
88 compatible = "atmel,samc2x-gclk";
125 clocks = <&gclk 33>, <&mclk 0x1c 17>;
126 clock-names = "GCLK", "MCLK";
131 gclk = <0>;
139 clocks = <&gclk 19>, <&mclk 0x1c 1>;
140 clock-names = "GCLK", "MCLK";
148 clocks = <&gclk 20>, <&mclk 0x1c 2>;
149 clock-names = "GCLK", "MCLK";
157 clocks = <&gclk 21>, <&mclk 0x1c 3>;
[all …]
Dsame5x.dtsi37 clocks = <&gclk 27>, <&mclk 0x10 17>;
38 clock-names = "GCLK", "MCLK";
50 clocks = <&gclk 28>, <&mclk 0x10 18>;
51 clock-names = "GCLK", "MCLK";
Dsamd2x.dtsi87 gclk: gclk@40000c00 { label
88 compatible = "atmel,samd2x-gclk";
204 * 8 MHz GCLK / 4 = 2 MHz
206 gclk = <3>;
Dsaml2x.dtsi98 gclk: gclk@40001800 { label
99 compatible = "atmel,saml2x-gclk";
216 gclk = <3>;
/Zephyr-latest/soc/atmel/sam0/common/
Dsoc_samd2x.c17 * Reference -> GCLK Gen 1 -> DFLL48M -> GCLK Gen 0 -> GCLK_MAIN
19 * GCLK Gen 0 -> GCLK_MAIN
20 * GCLK Gen 1 -> DFLL48M (variable)
21 * GCLK Gen 2 -> WDT @ 32768 Hz
22 * GCLK Gen 3 -> ADC @ 8 MHz
60 GCLK->GENDIV.reg = GCLK_GENDIV_ID(0) in osc8m_init()
63 while (GCLK->STATUS.bit.SYNCBUSY) { in osc8m_init()
66 GCLK->GENCTRL.reg = GCLK_GENCTRL_ID(0) in osc8m_init()
71 while (GCLK->STATUS.bit.SYNCBUSY) { in osc8m_init()
152 GCLK->GENCTRL.reg = GCLK_GENCTRL_ID(1) in dfll48m_init()
[all …]
Dsoc_samd5x.c37 GCLK->GENCTRL[1].reg = GCLK_GENCTRL_SRC(GCLK_SOURCE_XOSC32K) in osc32k_init()
44 GCLK->GENCTRL[1].reg = GCLK_GENCTRL_SRC(GCLK_SOURCE_OSCULP32K) in osc32k_init()
62 GCLK->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL0 + n].reg = GCLK_PCHCTRL_GEN(1) | GCLK_PCHCTRL_CHEN; in dpll_init()
63 while (!(GCLK->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL0 + n].reg & GCLK_PCHCTRL_CHEN)) { in dpll_init()
101 GCLK->CTRLA.bit.SWRST = 1; in gclk_reset()
102 while (GCLK->SYNCBUSY.bit.SWRST) { in gclk_reset()
106 static void gclk_connect(uint8_t gclk, uint8_t src, uint8_t div) in gclk_connect() argument
108 GCLK->GENCTRL[gclk].reg = GCLK_GENCTRL_SRC(src) in gclk_connect()
Dsoc_saml2x.c24 * Reference -> GCLK Gen 1 -> DFLL48M -> GCLK Gen 0 -> GCLK_MAIN
26 * GCLK Gen 0 -> GCLK_MAIN @ 48 Mhz
27 * GCLK Gen 1 -> DFLL48M (variable)
28 * GCLK Gen 2 -> USB @ 48 MHz
29 * GCLK Gen 3 -> ADC @ 24 MHz (further /2 in the ADC peripheral)
38 GCLK->GENCTRL[0].bit.SRC = GCLK_GENCTRL_SRC_OSCULP32K_Val; in gclk_reset()
112 GCLK->GENCTRL[1].reg = 0 in dfll48m_init()
133 GCLK->PCHCTRL[0].reg = 0 in dfll48m_init()
211 GCLK->GENCTRL[0].bit.SRC = GCLK_GENCTRL_SRC_DFLL48M_Val; in gclk_main_configure()
219 GCLK->GENCTRL[2].reg = 0 in gclk_usb_configure()
[all …]
Dsoc_samc2x.c41 GCLK->GENCTRL[0].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_OSC48M) in gclks_init()
/Zephyr-latest/dts/bindings/clock/
Datmel,samc2x-gclk.yaml4 description: Atmel SAMC2x Generic Clock Controller (GCLK)
6 compatible: "atmel,samc2x-gclk"
Datmel,samd2x-gclk.yaml4 description: Atmel SAMD2x Generic Clock Controller (GCLK)
6 compatible: "atmel,samd2x-gclk"
Datmel,samd5x-gclk.yaml4 description: Atmel SAMD5x Generic Clock Controller (GCLK)
6 compatible: "atmel,samd5x-gclk"
Datmel,saml2x-gclk.yaml4 description: Atmel SAML2x Generic Clock Controller (GCLK)
6 compatible: "atmel,saml2x-gclk"
/Zephyr-latest/drivers/pwm/
Dpwm_sam0_tcc.c111 GCLK->PCHCTRL[cfg->gclk_id].reg = in pwm_sam0_init()
115 GCLK->CLKCTRL.reg = cfg->gclk_clkctrl_id | GCLK_CLKCTRL_GEN_GCLK0 | in pwm_sam0_init()
147 .gclk_id = DT_INST_CLOCKS_CELL_BY_NAME(inst, gclk, periph_ch)
151 .gclk_clkctrl_id = DT_INST_CLOCKS_CELL_BY_NAME(inst, gclk, clkctrl_id)
Dpwm_sam0_tc.c142 GCLK->PCHCTRL[cfg->gclk_id].reg = in pwm_sam0_init()
146 GCLK->CLKCTRL.reg = cfg->gclk_clkctrl_id | GCLK_CLKCTRL_GEN_GCLK0 | in pwm_sam0_init()
192 .gclk_id = DT_INST_CLOCKS_CELL_BY_NAME(inst, gclk, periph_ch)
196 .gclk_clkctrl_id = DT_INST_CLOCKS_CELL_BY_NAME(inst, gclk, clkctrl_id)
/Zephyr-latest/drivers/dac/
Ddac_sam0.c80 /* Enable the GCLK */ in dac_sam0_init()
81 GCLK->CLKCTRL.reg = cfg->gclk_clkctrl_id | GCLK_CLKCTRL_GEN_GCLK0 | in dac_sam0_init()
124 DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, clkctrl_id), \
/Zephyr-latest/drivers/adc/
Dadc_sam0.c55 uint32_t gclk; member
453 GCLK->PCHCTRL[cfg->gclk_id].reg = cfg->gclk_mask | GCLK_PCHCTRL_CHEN; in adc_sam0_init()
459 GCLK->CLKCTRL.reg = cfg->gclk | GCLK_CLKCTRL_CLKEN; in adc_sam0_init()
521 DT_INST_PROP(n, gclk)), \
522 .gclk_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, periph_ch), \
538 .gclk = UTIL_CAT(GCLK_CLKCTRL_GEN_GCLK, DT_INST_PROP(n, gclk)) |\
569 DT_INST_PROP(n, gclk)), \
/Zephyr-latest/drivers/timer/
Dsam0_rtc_timer.c69 /* Helper macro to get the correct GCLK GEN based on configuration. */
257 /* Set up bus clock and GCLK generator. */ in sys_clock_driver_init()
259 GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(RTC_GCLK_ID) | GCLK_CLKCTRL_CLKEN in sys_clock_driver_init()
262 /* Synchronize GCLK. */ in sys_clock_driver_init()
263 while (GCLK->STATUS.bit.SYNCBUSY) { in sys_clock_driver_init()
/Zephyr-latest/drivers/can/
Dcan_sam0.c115 GCLK->GENCTRL[7].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_DFLL) in can_sam0_clock_enable()
120 GCLK->GENCTRL[7].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_OSC48M) in can_sam0_clock_enable()
126 GCLK->PCHCTRL[cfg->gclk_core_id].reg = GCLK_PCHCTRL_GEN_GCLK7 in can_sam0_clock_enable()
216 .gclk_core_id = DT_INST_CLOCKS_CELL_BY_NAME(inst, gclk, periph_ch), \
/Zephyr-latest/drivers/counter/
Dcounter_sam0_tc32.c340 /* Enable the GCLK */ in counter_sam0_tc32_initialize()
341 GCLK->PCHCTRL[cfg->gclk_id].reg = GCLK_PCHCTRL_GEN_GCLK0 | in counter_sam0_tc32_initialize()
347 /* Enable the GCLK */ in counter_sam0_tc32_initialize()
348 GCLK->CLKCTRL.reg = cfg->gclk_clkctrl_id | GCLK_CLKCTRL_GEN_GCLK0 | in counter_sam0_tc32_initialize()
410 .gclk_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, periph_ch),
414 .gclk_clkctrl_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, clkctrl_id),
/Zephyr-latest/dts/bindings/adc/
Datmel,sam0-adc.yaml25 gclk:

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