Lines Matching full:gclk
17 * Reference -> GCLK Gen 1 -> DFLL48M -> GCLK Gen 0 -> GCLK_MAIN
19 * GCLK Gen 0 -> GCLK_MAIN
20 * GCLK Gen 1 -> DFLL48M (variable)
21 * GCLK Gen 2 -> WDT @ 32768 Hz
22 * GCLK Gen 3 -> ADC @ 8 MHz
60 GCLK->GENDIV.reg = GCLK_GENDIV_ID(0) in osc8m_init()
63 while (GCLK->STATUS.bit.SYNCBUSY) { in osc8m_init()
66 GCLK->GENCTRL.reg = GCLK_GENCTRL_ID(0) in osc8m_init()
71 while (GCLK->STATUS.bit.SYNCBUSY) { in osc8m_init()
152 GCLK->GENCTRL.reg = GCLK_GENCTRL_ID(1) in dfll48m_init()
166 while (GCLK->STATUS.bit.SYNCBUSY) { in dfll48m_init()
169 GCLK->GENDIV.reg = GCLK_GENDIV_ID(1) in dfll48m_init()
172 while (GCLK->STATUS.bit.SYNCBUSY) { in dfll48m_init()
176 GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(0) in dfll48m_init()
225 GCLK->GENDIV.reg = GCLK_GENDIV_ID(0) in gclk_main_configure()
228 while (GCLK->STATUS.bit.SYNCBUSY) { in gclk_main_configure()
231 GCLK->GENCTRL.reg = GCLK_GENCTRL_ID(0) in gclk_main_configure()
236 while (GCLK->STATUS.bit.SYNCBUSY) { in gclk_main_configure()
246 GCLK->GENDIV.reg = GCLK_GENDIV_ID(3) in gclk_adc_configure()
249 while (GCLK->STATUS.bit.SYNCBUSY) { in gclk_adc_configure()
252 GCLK->GENCTRL.reg = GCLK_GENCTRL_ID(3) in gclk_adc_configure()
257 while (GCLK->STATUS.bit.SYNCBUSY) { in gclk_adc_configure()
267 GCLK->GENDIV.reg = GCLK_GENDIV_ID(2) in gclk_wdt_configure()
270 GCLK->GENCTRL.reg = GCLK_GENCTRL_ID(2) in gclk_wdt_configure()
275 while (GCLK->STATUS.bit.SYNCBUSY) { in gclk_wdt_configure()