1 /*
2  * Copyright (c) 2022 Kamil Serwus
3  * Copyright (c) 2023 Gerson Fernando Budke <nandojve@gmail.com>
4  *
5  * SPDX-License-Identifier: Apache-2.0
6  */
7 
8 /**
9  * @file
10  * @brief Atmel SAMC MCU series initialization code
11  */
12 
13 #include <zephyr/device.h>
14 #include <zephyr/init.h>
15 #include <zephyr/kernel.h>
16 #include <soc.h>
17 
flash_waitstates_init(void)18 static void flash_waitstates_init(void)
19 {
20 	/* Two wait state at 48 MHz. */
21 	NVMCTRL->CTRLB.bit.RWS = NVMCTRL_CTRLB_RWS_DUAL_Val;
22 }
23 
osc48m_init(void)24 static void osc48m_init(void)
25 {
26 	/* Turn off the prescaler */
27 	OSCCTRL->OSC48MDIV.bit.DIV = 0;
28 	while (OSCCTRL->OSC48MSYNCBUSY.bit.OSC48MDIV) {
29 	}
30 	while (!OSCCTRL->STATUS.bit.OSC48MRDY) {
31 	}
32 }
33 
mclk_init(void)34 static void mclk_init(void)
35 {
36 	MCLK->CPUDIV.reg = MCLK_CPUDIV_CPUDIV_DIV1_Val;
37 }
38 
gclks_init(void)39 static void gclks_init(void)
40 {
41 	GCLK->GENCTRL[0].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_OSC48M)
42 			     | GCLK_GENCTRL_DIV(1)
43 			     | GCLK_GENCTRL_GENEN;
44 }
45 
soc_reset_hook(void)46 void soc_reset_hook(void)
47 {
48 	flash_waitstates_init();
49 	osc48m_init();
50 	mclk_init();
51 	gclks_init();
52 }
53