| /Zephyr-latest/subsys/logging/backends/ |
| D | Kconfig.swo | 14 int "SWO reference clock frequency"
15 …default $(dt_node_int_prop_int,$(dt_nodelabel_path,itm),swo-ref-frequency) if $(dt_nodelabel_enabl…
16 …ault $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) if $(dt_node_has_prop,/cpus/cpu@0,clock-f…
19 Set SWO reference frequency. In most cases it is equal to CPU
20 frequency.
23 int "Set SWO output frequency"
26 Set SWO output frequency. Value 0 will select maximum frequency
28 frequency SWO operation. In this case the frequency has to be set
32 viewer programs will configure SWO frequency when attached to the
34 reset. To ensure flawless operation the frequency configured here and
[all …]
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| /Zephyr-latest/tests/drivers/rtc/rtc_api_helpers/src/ |
| D | test_rtc_calibration_from_frequency.c | 11 uint32_t frequency; member
17 .frequency = 1000000000,
21 .frequency = 1000000001,
25 .frequency = 999999999,
29 .frequency = 2000000000,
33 .frequency = 500000000,
40 uint32_t frequency; in ZTEST() local
45 frequency = test_samples[i].frequency; in ZTEST()
47 result = rtc_calibration_from_frequency(frequency); in ZTEST()
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| /Zephyr-latest/tests/drivers/build_all/sensor/ |
| D | spi.dtsi | 16 spi-max-frequency = <0>;
23 spi-max-frequency = <0>;
30 spi-max-frequency = <0>;
36 spi-max-frequency = <0>;
43 spi-max-frequency = <0>;
49 spi-max-frequency = <0>;
56 spi-max-frequency = <0>;
63 spi-max-frequency = <0>;
70 spi-max-frequency = <0>;
77 spi-max-frequency = <0>;
[all …]
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| /Zephyr-latest/subsys/lorawan/ |
| D | Kconfig | 48 bool "Asia 923MHz Frequency band"
51 bool "Australia 915MHz Frequency band"
54 bool "China 470MHz Frequency band"
57 bool "China 779MHz Frequency band"
60 bool "Europe 433MHz Frequency band"
63 bool "Europe 868MHz Frequency band"
66 bool "South Korea 920MHz Frequency band"
69 bool "India 865MHz Frequency band"
72 bool "North America 915MHz Frequency band"
75 bool "Russia 864MHz Frequency band"
|
| /Zephyr-latest/dts/bindings/counter/ |
| D | andestech,atcpit100.yaml | 21 clock-frequency:
30 The prescaler value defines the counter frequency
31 (clock-frequency/prescaler) in atcpit100 counter driver, the prescaler
32 value could be in range [1 .. clock-frequency] and 1 means no prescaler
33 for the PIT clock-frequency.
35 Defaults to 1 to use the PIT clock-frequency as the counter frequency.
38 larger than a counter tick period, reducing the counter frequency to
|
| D | nordic,nrf-timer.yaml | 27 max-frequency:
31 Maximum timer frequency in Hz.
33 The default value is 16MHz which was the maximum frequency for all nRF TIMER peripherals
34 up to the nRF54 series, and still remains the most typical maximum frequency for nRF54
40 description: Prescaler value determines frequency (max-frequency/2^prescaler)
|
| /Zephyr-latest/dts/bindings/clock/ |
| D | nuvoton,npcm-pcc.yaml | 7 Oscillator Frequency Multiplier Clock (OFMCLK), which is derived from
8 High-Frequency Clock Generator (HFCG), is the source clock of Cortex-M4 core
14 clock-frequency = <DT_FREQ_M(96)>; /* OFMCLK runs at 96MHz */
32 clock-frequency:
36 Default frequency in Hz for HFCG output clock (OFMCLK). Currently,
60 Core clock prescaler (FPRED). It sets the Core frequency, CORE_CLK, by
62 - The maximum CLK frequency is either the MCLK frequency divided by 1 or 100 MHz.
90 APB1 prescaler. It sets the APB1 bus frequency, APB1_CLK, by dividing
92 - The maximum APB1_CLK frequency is either the MCLK frequency divided by 1 or 100 MHz.
120 APB2 prescaler. It sets the APB2 bus frequency, APB2_CLK, by dividing
[all …]
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| D | nordic,nrf-hsfll-global.yaml | 7 The lowest supported clock frequency is the default
8 clock frequency.
16 clock-frequency = <320000000>;
40 clock-frequency:
43 Optional fixed frequency specified if used in fixed
44 frequency mode.
|
| D | pwm-clock.yaml | 19 frequency to time (nanoseconds units). This may result in rounding
20 errors if the clock frequency is not an integer number of nanoseconds.
21 The clock frequency can be explicitly set using the clock-frequency
37 clock-frequency:
40 Exact output frequency, in case the PWM period is not exact
|
| D | st,stm32wba-rcc.yaml | 13 Core clock frequency should also be defined, using "clock-frequency" property.
15 Core clock frequency = SYSCLK / AHB prescaler
22 clock-frequency = <DT_FREQ_M(40)>; /* = SYSCLK / AHB prescaler */
66 clock-frequency:
70 default frequency in Hz for clock output (HCLK1)
82 Common AHB1, AHB2, AHB4 prescaler. Defines actual core clock frequency
83 (HCLK) based on system frequency input. AKA HPRE.
95 AHB5 prescaler. Defines actual core clock frequency (HCLK5) based on
96 system frequency input. It is used to limit HCLK5 below 32MHz.
|
| D | st,stm32wb0-lsi-clock.yaml | 7 The STM32WB0 MCUs are equipped with a regular RC LSI clock with a frequency of 24~40kHz.
8 The SoCs are also equipped with hardware to perform LSI frequency measurement, which
9 allows to adapt all frequency-based calculations to a somewhat accurate value, ensuring
12 Several LSI frequency measurement options can be configured via Kconfig.
|
| D | st,stm32h7-rcc.yaml | 13 As part of this node configuration, SYSCLK frequency should also be defined, using
14 "clock-frequency" property.
20 clock-frequency = <DT_FREQ_M(480)>; /* SYSCLK runs at 480MHz */
42 clock-frequency:
46 default frequency in Hz for clock output
54 D1 Domain, CPU1 clock prescaler. Sets a HCLK frequency (feeding Cortex-M Systick)
55 lower than SYSCLK frequency (actual core frequency).
|
| D | st,stm32h7rs-rcc.yaml | 13 As part of this node configuration, SYSCLK frequency should also be defined, using
14 "clock-frequency" property.
20 clock-frequency = <DT_FREQ_M(280)>; /* SYSCLK runs at 280MHz */
42 clock-frequency:
46 default frequency in Hz for clock output
62 CPU clock prescaler. Sets a HCLK frequency (feeding Cortex-M Systick)
63 lower than SYSCLK frequency (actual core frequency).
|
| /Zephyr-latest/soc/silabs/ |
| D | Kconfig | 220 prompt "High Frequency Clock Selection"
224 bool "External high frequency crystal oscillator"
226 Set this option to use the external high frequency crystal oscillator
227 as high frequency clock.
230 bool "External low frequency crystal oscillator"
233 Set this option to use the external low frequency crystal oscillator
234 as high frequency clock.
237 bool "Internal high frequency RC oscillator"
239 Set this option to use the internal high frequency RC oscillator as high frequency clock.
244 int "External high frequency oscillator frequency"
[all …]
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| /Zephyr-latest/modules/hal_nordic/nrfs/dvfs/ |
| D | ld_dvfs_handler.h | 17 * @brief Function to request LD frequency change.
19 * @param frequency requested frequency setting from enum dvfs_frequency_setting.
20 * @return EBUSY Frequency change request pending.
22 * @return ENXIO Not supported frequency settings.
32 * @param new_setting applied frequency setting
37 * @brief Register callback function which will be called when new dvfs frequency is applied.
|
| /Zephyr-latest/dts/bindings/display/ |
| D | sharp,ls0xx.yaml | 18 extcomin-frequency:
20 description: EXTCOMIN pin toggle frequency
22 The frequency with which the EXTCOMIN pin should be toggled. See
23 datasheet of particular display. Higher frequency gives better
24 contrast while low frequency saves power.
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| /Zephyr-latest/dts/bindings/rtc/ |
| D | rtc.yaml | 9 clock-frequency:
11 description: Clock frequency information for RTC operation
17 description: RTC frequency equals clock-frequency divided by the prescaler value
|
| /Zephyr-latest/tests/drivers/clock_control/nrf_clock_control/src/ |
| D | main.c | 21 .frequency = MHZ(128),
26 .frequency = MHZ(320),
31 .frequency = MHZ(64),
40 .frequency = MHZ(16),
45 .frequency = MHZ(16),
50 .frequency = MHZ(16),
66 .frequency = MHZ(16),
71 .frequency = MHZ(19),
76 .frequency = MHZ(16),
109 .frequency = MHZ(320),
[all …]
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| /Zephyr-latest/dts/bindings/timer/ |
| D | nuclei,systimer.yaml | 24 clk-divider specifies the division ratio to the CPU frequency that
30 For example, the CPU clock frequency is 108MHz, and the system timer
32 In this case, the CPU clock frequency is defined in the CPU node
35 clock-frequency = <108000000>;
38 The relationship with the frequency division ratio is as
45 that CPU clock frequency divided by (2^2=)4, or 27MHz.
|
| /Zephyr-latest/tests/drivers/build_all/adc/boards/ |
| D | native_sim.overlay | 41 clock-frequency = <100000>;
140 clock-frequency = <2000000>;
171 spi-max-frequency = <0>;
178 spi-max-frequency = <0>;
186 spi-max-frequency = <0>;
194 spi-max-frequency = <0>;
202 spi-max-frequency = <0>;
210 spi-max-frequency = <0>;
218 spi-max-frequency = <0>;
226 spi-max-frequency = <0>;
[all …]
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| /Zephyr-latest/soc/atmel/sam0/samr21/ |
| D | soc.h | 42 /** Processor Clock (HCLK) Frequency */
45 /** Master Clock (MCK) Frequency */
56 /** GCLK1 source frequency selector */
71 /** Dividers and frequency for GCLK0 */
76 /** DFLL48M output frequency */
80 /** Dividers and frequency for GCLK1 */
90 /** Frequency for GCLK2 */
93 /** Dividers and frequency for GCLK3 */
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| /Zephyr-latest/soc/atmel/sam0/samd21/ |
| D | soc.h | 56 /** Processor Clock (HCLK) Frequency */
59 /** Master Clock (MCK) Frequency */
70 /** GCLK1 source frequency selector */
85 /** Dividers and frequency for GCLK0 */
90 /** DFLL48M output frequency */
94 /** Dividers and frequency for GCLK1 */
104 /** Frequency for GCLK2 */
107 /** Dividers and frequency for GCLK3 */
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| /Zephyr-latest/dts/bindings/usb/uac2/ |
| D | zephyr,uac2-clock-source.yaml | 14 clock or an internal clock with either fixed frequency, variable
15 frequency, or programmable frequency.
28 frequency-control:
30 description: Clock Frequency Control capabilities
|
| /Zephyr-latest/soc/intel/intel_adsp/common/include/ |
| D | adsp_clk.h | 20 /** @brief Set cAVS clock frequency
24 * @param freq Clock frequency index to be set
81 uint32_t frequency; member
86 * @param freq Clock frequency index
92 /** @brief Get clock source frequency
94 * @param freq Clock frequency index
96 * @return frequency on success, 0 on error
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| /Zephyr-latest/drivers/clock_control/ |
| D | clock_control_nrf2_hsfll.c | 30 /* Clock options sorted from lowest to highest frequency */
32 uint32_t frequency; member
36 .frequency = HSFLL_FREQ_LOW,
40 .frequency = HSFLL_FREQ_MEDLOW,
44 .frequency = HSFLL_FREQ_HIGH,
107 uint32_t frequency; in hsfll_find_mgr() local
118 frequency = spec->frequency == NRF_CLOCK_CONTROL_FREQUENCY_MAX in hsfll_find_mgr()
120 : spec->frequency; in hsfll_find_mgr()
123 if (frequency > clock_options[i].frequency) { in hsfll_find_mgr()
130 LOG_ERR("invalid frequency"); in hsfll_find_mgr()
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