1 /* 2 * Copyright (c) 2017 Google LLC. 3 * Copyright (c) 2023 Ionut Catalin Pavel <iocapa@iocapa.com> 4 * Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com> 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 */ 8 9 #ifndef _SOC_ATMEL_SAM0_SAMR21_SOC_H_ 10 #define _SOC_ATMEL_SAM0_SAMR21_SOC_H_ 11 12 #ifndef _ASMLANGUAGE 13 14 #define DONT_USE_CMSIS_INIT 15 16 #include <zephyr/types.h> 17 18 #if defined(CONFIG_SOC_SAMR21E16A) 19 #include <samr21e16a.h> 20 #elif defined(CONFIG_SOC_SAMR21E17A) 21 #include <samr21e17a.h> 22 #elif defined(CONFIG_SOC_SAMR21E18A) 23 #include <samr21e18a.h> 24 #elif defined(CONFIG_SOC_SAMR21E19A) 25 #include <samr21e19a.h> 26 #elif defined(CONFIG_SOC_SAMR21G16A) 27 #include <samr21g16a.h> 28 #elif defined(CONFIG_SOC_SAMR21G17A) 29 #include <samr21g17a.h> 30 #elif defined(CONFIG_SOC_SAMR21G18A) 31 #include <samr21g18a.h> 32 #else 33 #error Library does not support the specified device. 34 #endif 35 36 #endif /* _ASMLANGUAGE */ 37 38 #include "adc_fixup_sam0.h" 39 #include "../common/soc_port.h" 40 #include "../common/atmel_sam0_dt.h" 41 42 /** Processor Clock (HCLK) Frequency */ 43 #define SOC_ATMEL_SAM0_HCLK_FREQ_HZ ATMEL_SAM0_DT_CPU_CLK_FREQ_HZ 44 45 /** Master Clock (MCK) Frequency */ 46 #define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ 47 48 /** Known values */ 49 #define SOC_ATMEL_SAM0_DFLL48M_MAX_FREQ_HZ 48000000 50 #define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 51 #define SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ 32768 52 #define SOC_ATMEL_SAM0_OSC8M_FREQ_HZ 8000000 53 #define SOC_ATMEL_SAM0_OSCULP32K_FREQ_HZ 32768 54 #define SOC_ATMEL_SAM0_GCLK1_TARGET_FREQ_HZ 31250 55 56 /** GCLK1 source frequency selector */ 57 #if defined(CONFIG_SOC_ATMEL_SAMD_DEFAULT_AS_MAIN) 58 #define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_GCLK1_TARGET_FREQ_HZ 59 #elif defined(CONFIG_SOC_ATMEL_SAMD_OSC32K_AS_MAIN) 60 #define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 61 #elif defined(CONFIG_SOC_ATMEL_SAMD_XOSC32K_AS_MAIN) 62 #define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ 63 #elif defined(CONFIG_SOC_ATMEL_SAMD_OSC8M_AS_MAIN) 64 #define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_OSC8M_FREQ_HZ 65 #elif defined(CONFIG_SOC_ATMEL_SAMD_XOSC_AS_MAIN) 66 #define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ CONFIG_SOC_ATMEL_SAMD_XOSC_FREQ_HZ 67 #else 68 #error Unsupported GCLK1 clock source. 69 #endif 70 71 /** Dividers and frequency for GCLK0 */ 72 #define SOC_ATMEL_SAM0_GCLK0_DIV \ 73 (SOC_ATMEL_SAM0_DFLL48M_MAX_FREQ_HZ / SOC_ATMEL_SAM0_MCK_FREQ_HZ) 74 #define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ 75 76 /** DFLL48M output frequency */ 77 #define SOC_ATMEL_SAM0_DFLL48M_FREQ_HZ \ 78 (SOC_ATMEL_SAM0_MCK_FREQ_HZ * SOC_ATMEL_SAM0_GCLK0_DIV) 79 80 /** Dividers and frequency for GCLK1 */ 81 #define SOC_ATMEL_SAM0_GCLK1_DIV \ 82 (SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ / SOC_ATMEL_SAM0_GCLK1_TARGET_FREQ_HZ) 83 #define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ \ 84 (SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ / SOC_ATMEL_SAM0_GCLK1_DIV) 85 86 /** DFLL48M output multiplier */ 87 #define SOC_ATMEL_SAM0_DFLL48M_MUL \ 88 (SOC_ATMEL_SAM0_DFLL48M_FREQ_HZ / SOC_ATMEL_SAM0_GCLK1_FREQ_HZ) 89 90 /** Frequency for GCLK2 */ 91 #define SOC_ATMEL_SAM0_GCLK2_FREQ_HZ SOC_ATMEL_SAM0_OSCULP32K_FREQ_HZ 92 93 /** Dividers and frequency for GCLK3 */ 94 #define SOC_ATMEL_SAM0_GCLK3_FREQ_HZ SOC_ATMEL_SAM0_OSC8M_FREQ_HZ 95 #define SOC_ATMEL_SAM0_GCLK3_DIV \ 96 (SOC_ATMEL_SAM0_DFLL48M_FREQ_HZ / SOC_ATMEL_SAM0_GCLK3_FREQ_HZ) 97 98 #define SOC_ATMEL_SAM0_APBA_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ 99 #define SOC_ATMEL_SAM0_APBB_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ 100 #define SOC_ATMEL_SAM0_APBC_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ 101 102 #endif /* _SOC_ATMEL_SAM0_SAMR21_SOC_H_ */ 103
