Lines Matching full:frequency

7   Oscillator Frequency Multiplier Clock (OFMCLK), which is derived from
8   High-Frequency Clock Generator (HFCG), is the source clock of Cortex-M4 core
14       clock-frequency = <DT_FREQ_M(96)>; /* OFMCLK runs at 96MHz */
32   clock-frequency:
36       Default frequency in Hz for HFCG output clock (OFMCLK). Currently,
60       Core clock prescaler (FPRED). It sets the Core frequency, CORE_CLK, by
62       - The maximum CLK frequency is either the MCLK frequency divided by 1 or 100 MHz.
90       APB1 prescaler. It sets the APB1 bus frequency, APB1_CLK, by dividing
92       - The maximum APB1_CLK frequency is either the MCLK frequency divided by 1 or 100 MHz.
120       APB2 prescaler. It sets the APB2 bus frequency, APB2_CLK, by dividing
122       - The maximum APB2_CLK frequency is either the MCLK frequency divided by 1 or 100 MHz.
150       APB3 prescaler. It sets the APB3 bus frequency, APB3_CLK, by dividing
152       - The maximum APB3_CLK frequency is either the MCLK frequency divided by 1 or 100 MHz.
182       Its frequency must be set according to the following rules:
183       - The maximum AHB6_CLK frequency is either the CLK frequency divided by 1 or 100 MHz.
199       Its frequency must be set according to the following rules:
200       - The maximum FIUCLK frequency is either the CLK frequency divided by 1 or 100MHz.
214       I3C prescaler. It sets the I3C clk_slow_tc frequency, by dividing